Robust QCA full-adders using an efficient fault-tolerant five-input majority gate

Quantum-dot cellular automata (QCA) is considered as a top candidate for nanoscale technologies with unique features such as very low occupancy and ultralow power consumption. Despite the potential benefits of QCA technology over CMOS technology, QCA circuits are highly prone to defects. Therefore, a demand has risen in designing fault-tolerant circuits. In this research, a novel fault-tolerant five-input majority gate is first suggested, and then it is evaluated by implementing a variety of faults such as cell omission, cell displacement, and extra-cell deposition. The evaluation results reveal that the proposed structure is 100%, 51.85%, and 18.8% fault-tolerant under extra-cell deposition, single-cell omission, and double-cell omission, respectively. Moreover, two single-layer and coplanar fault-tolerant QCA full-adders are offered using the suggested fault-tolerant structure. The stability of the presented single-layer full-adder has also been investigated under single and double cell omission defects. The evaluation outcomes show that the suggested fault-tolerant single-layer full-adder has a high stability in Sum and C_out outputs compared with other full-adders. In order to validate the functionality of the suggested fault-tolerant five-input majority gate, a number of physical investigations are given. The QCADesigner 2.0.3 software has been used to evaluate the simulation results.     

A novel QCA implementation of MUX-based universal shift register

QCA (Quantum-dot Cellular Automata) is an alternative technology for CMOS that has a low power consumption and high density. QCA extensively supports the new plans in the field of nanotechnology. Applications of QCA technology as an alternative method for CMOS technology in nano-scale have a hopeful future. This paper presents the successful design, implementation and simulation of 2 to 1, 4 to 1 and 8 to 1 multiplexer with the minimum area as compared to the previous models in QCA technology. In this paper, by means of 4 to 1 multiplexers including D-Flip Flop (D-FF) structure in QCA, we present an 8-bit universal shift register. The structure of the 8-bit universal register is extendable to 16-bit, 32-bit and etc. In this paper, the successful simulation of 2 to 1, 4 to 1 and 8 to 1 multiplexers, including D-FF and finally 8-bit universal register structure in QCADesigner is provided. The multiplexers and D-FF presented in this paper have the minimum complexity, area and delay compared to the previous models. In this paper, the implementation of 8-bit universal shift register, by means of 4 to 1 multiplexers and D-FF are presented in QCA technique which have the minimum complexity and delay. In the proposed design of the 8-bit universal shift register, the faults are likely to occur at 2 to 1 multiplexers and D-FF. In this article, 2 to 1 multiplexers and D-FF are investigated from the cell missing and possible defects. Considering the pipeline being the virtue of QCA, the 8-bit universal shift register has a high speed function. This 8-bit universal shift register may be used in the high speed processors as well as cryptography circuits.     

Calculating the steady-state polarizations of quantum cellular automata (QCA) circuits

We present on the use of well-known stochastic methods for computing the steady-state polarizations of quantum cellular automata (QCA) circuits. Typically, a Boltzmann distribution, which requires the exploration of the complete configuration space of an \(N\) -cell QCA circuit, is used to compute the \(2^N\) steady-states of the QCA circuit. However, the exponential growth in states as the circuit size grows makes computing the Boltzmann distribution infeasible for large circuits. Thus, we approximate the Boltzmann distribution of a QCA circuit by conducting a partial exploration of the complete configuration space by means of a Monte Carlo method, simulated annealing, and a genetic algorithm. The approximated Boltzmann distribution from each method was able to compute the steady-state polarizations with a very high degree of accuracy, with the simulated annealing algorithm producing the best results.     

Modular design of QCA carry flow adders and multiplier with reduced wire crossing and number of logic gates

Quantum‐dot cellular automata (QCA) is an emerging technology with the rapid development of low‐power high‐performance digital circuits. In order to reduce the wire crossings and the number of logic gates in QCA circuits, this paper proposes a full adder named Tile full adder based on a 3 × 3 grid module, a Tile bit‐serial adder based on the new full adder and a Diverse Clock Tile bit serial adder (DC Tile bit‐serial) adder based on the new full adder and a DC multiplier network. Based on previously mentioned circuit units an improved carry flow adder (CFA) named Tile CFA and two types of carry delay multiplier (CDM) named Tile CDM and DC Tile CDM (DC Tile CDM) with different sizes are presented. All of the proposed QCA circuits are designed and simulated with QCADesigner. Simulation results show that these circuit designs not only implement the logic functions correctly but also achieve a significant performance improvement. Copyright © 2015 John Wiley & Sons, Ltd.     

Innovative design methodologies in quantum‐dot cellular automata

Current transistor‐based IC fabrication technology faces many trivial issues such as those of excess power dissipation, expensive fabrication and short channel effects at very low device size [1]. Quantum‐dot cellular automata (QCA)‐based digital electronics on the other hand provide scope for further development in the future by shrinking the device size. Current QCA logic circuits are based on logic synthesis using Inverters and (three or five input) Majority Gates. In this paper, a new design methodology has been described that can be used to create circuits with even greater device substrate densities than what are currently achieved in existing QCA designs. Based on the proposed methodology, a new QCA inverter is proposed. It is further tested through simulations on QCA Designer. Through the simulations, it is subsequently proved to be much more reliable and robust than the presently used common QCA inverter(s). In the second section of this paper, simple QCA circuits such as ring oscillators using odd number of inverters in daisy chains are described and designed using the proposed inverter design. Copyright © 2013 John Wiley & Sons, Ltd.     

Monte-Carlo Simulation of Clocked and Non-Clocked QCA Architectures

We present a Monte Carlo simulation of two implementations of Quantum Cellular Automaton (QCA) circuits: one based on simple ground state relaxation and the other on the clocked cell scheme that has recently been proposed by Tóth and Lent. We focus on the time-dependent behavior of two basic circuits, a binary wire and a majority voting gate, and assess their maximum operating speed and temperature requirements for different sets of fabrication parameters.     

Analysis of field-driven clocking for molecular quantum-dot cellular automata based circuits

Molecular quantum-dot cellular automaton (QCA) offers an alternative paradigm for computing at the nano-scale. QCA circuits require an external clock which can be generated using a network of submerged electrodes to synchronize information flow and provide the required power to drive the computation. In this paper, the effect of electrode separation and applied potential on the likelihood of different QCA cell states of molecular cells located above and in between two adjacent electrodes is analyzed. Using this analysis, estimates of operational ranges are developed for the placement, applied potential, and relative phase between adjacent clocking electrodes to ensure that only those states that are used in the computation are energetically favorable. Conclusions on the trade-off between cell size, cell-to-cell distance, and applied clocking potential are drawn and the temperature dependence of the operation of fundamental QCA building blocks is considered.     

A companion macromodelling approach for the transient analysis of MOS large-scale integrated circuits

Purpose of this work is to present a new macromodelling approach for the simulation at the device level of large MOS integrated circuits, requiring only marginal modifications to be implemented in the widely used circuit simulator SPICE. This method results in a substantial saving in computing time and guarantees the same accuracy of SPICE. A prototype simulator based on this method has been developed and used to analyse several significant circuits. In addition, since the method is particularly suitable to be implemented in parallel computers, some results obtained with the CRAY-YMP/432 computer are provided.     

A hybrid time-domain technique for simulation of high-density integrated optical circuits

This paper presents a new simulation method for modeling and simulation of high-density integrated optical circuits based on high index contrast (HIC) waveguides with complex topology. The method combines the time-domain reflective beam propagation method (TD-RBPM) and the slow-wave finite-difference time-domain method and is hence referred to as the time-domain hybrid BPM (TD-HBPM). It is capable of handling arbitrary optical integrated circuits with perpendicularly located input and output ports. The application to the two HIC optical circuits shows the accuracy and efficiency of this method.     

Design of a reversible structure for memory in quantum-dot cellular automata

Complementary metal oxide semiconductor (CMOS) technology has limitations in reducing the area and size of circuits. The disadvantages of this technology include high power consumption and temperature problems. Quantum-dot cellular automata (QCA) is a new technology that can overcome these shortcomings. Reversible logic is technology used to reduce the power loss in QCA. QCA can be used to design memories that require high operating speed. In this paper, we propose a structure for the reversible memory in QCA. The proposed structure utilizes three-layer technology, which has a significant impact on circuit size reduction. The proposed structure for the reversible memory has 63% improvement in cell number, a 75% improvement in area occupancy, and a 60% reduction in delay compared to the previous best structure.     

A novel robust exclusive-OR function implementation in QCA nanotechnology with energy dissipation analysis

Numerous scientific and fundamental hindrances have resulted in a slow down of silicon technology and opened new possibilities for emerging research devices and structures. The need has arisen to expedite new methods to interface these nanostructures for computing applications. Quantum-dot Cellular Automata (QCA) is one of such computing paradigm and means of encoding binary information. QCA computing offers potential advantages of ultra-low power dissipation, improved speed and highly density structures. This paper presents a novel two-input Exclusive-OR (XOR) gate implementation in quantum-dot cellular automata nanotechnology with minimum area and power dissipation as compared to previous designs. The proposed novel QCA based XOR structure uses only 28 QCA cells with an area of \(0.02\,\upmu \hbox {m}^{2}\) and latency of 0.75 clock cycles. Also the proposed novel XOR gate is implemented in single layer without using any coplanar and multi-layer cross-over wiring facilitating highly robust and dense QCA circuit implementations. To investigate the efficacy of our proposed design in complex array of QCA structures, 4, 8, 16 and 32-bit even parity generator circuits were implemented. The proposed 4-bit even parity design occupies 9 and 50 % less area and has 12.5 and 22.22 % less latency as compared to previous designs. The 32-bit even parity design occupies 22 % less area than the best reported previous design. The proposed novel XOR structure has 28 % less switching energy dissipation, 10 % less average leakage energy dissipation and 19 % less average energy dissipation than best reported design. The simulation results verified that the proposed design offers significant improvements in terms of area, latency, energy dissipation and structural implementation requirements. All designs have been functionally verified in the QCADesigner tool for GaAs/AlGaAs heterostructure based semiconductor implementations. The energy dissipation results have been computed using an accurate QCAPro tool.     

k-NN based fault detection andclassification methods for powertransmission systems

This paper deals with two new methods, based on k-NN algorithm, for fault detection and classification in distance protection. In these methods, by finding the distance between each sample and its fifth nearest neighbor in a predefault window, the fault occurrence time and the faulty phases are determined. The maximum value of the distances in case of detection and classification procedures is compared with pre-defined threshold values. The main advantages of these methods are: simplicity, low calculation burden, acceptable accuracy, and speed. The performance of the proposed scheme is tested on a typical system in MATLAB Simulink. Various possible fault types in different fault resistances, fault inception angles, fault locations, short circuit levels, X/R ratios, source load angles are simulated. In addition, the performance of similar six well-known classification techniques is compared with the proposed classification method using plenty of simulation data     

k-NN based fault detection and classification methods for power transmission systems

This paper deals with two new methods, based on k-NN algorithm, for fault detection and classification in distance protection. In these methods, by finding the distance between each sample and its fifth nearest neighbor in a predefault window, the fault occurrence time and the faulty phases are determined. The maximum value of the distances in case of detection and classification procedures is compared with pre-defined threshold values. The main advantages of these methods are: simplicity, low calculation burden, acceptable accuracy, and speed. The performance of the proposed scheme is tested on a typical system in MATLAB Simulink. Various possible fault types in different fault resistances, fault inception angles, fault locations, short circuit levels, X/R ratios, source load angles are simulated. In addition, the performance of similar six well-known classification techniques is compared with the proposed classification method using plenty of simulation data     

Modelling an insulated gate bipolar transistor using bond graph techniques

Simulators in power electronics are less developed than in other electronic fields. The main modelling methods are between the numerical simulation of semiconductor device equations that hardly simulate circuits, and equivalent circuit models that show poor accuracy. We propose the application of the bond graph techniques to model modular power semiconductor devices. Furthermore, the IGBT is a new power device which combines a bipolar transistor with a MOSFET transistor. We develop a new IGBT bond graph model. The bond graph techniques give us good primary simulation results. We present in this paper the principle and the results of this modelling method.     

Novel quantum‐dot cellular automata implementation of flip‐flop and phase‐frequency detector based on nand‐nor‐inverter gates

CMOS technology faces fundamental challenges such as frequency and power consumption due to the impossibility of further reducing dimensions. For these reasons, researchers have been thinking replacement of this technology with other technologies such as quantum‐dot cellular automata (QCA) technology. Many studies have been done to design digital circuits using QCA technology. Phase‐frequency detector (PFD) is one of the main blocks in electrical and communication circuits. In this paper, a novel structure for PFDs in QCA technology is proposed. In the proposed design, the novel D flip‐flop (D‐FF) with reset ability is used. The D‐FF is designed by the proposed D latch which is based on nand‐nor‐inverter (NNI) and an inverter gate. This proposed D latch has 22 cells and 0.5 clock cycle latency and 0.018‐μm² area. The inverter gate of the D‐FF has output signal with high polarization level and lower area than previous inverters, and the NNI gate of the D‐FF is a universal gate. The proposed PFD has 141 cells, 0.17‐μm² occupied area, and two clock cycle latency that is smaller compared with PFD and is based on common inverter and majority gates.     

Towards the design of hybrid QCA tiles targeting high fault tolerance

The increasing fabrication cost of CMOS-based computing devices and the ever-approaching limits of their fabrication have led to the search for feasible options with high device density and low power waste. Quantum-dot cellular automata (QCA) is an emerging technology with such potential to match the design target beyond the limits of state-of-the-art CMOS. But nanotechnologies, like QCA are extremely susceptible to various forms of flaws and variations during fabrication at nano scale. Thus, the exploration of ingenious fault tolerant structure around QCA is gaining high importance. This work targets a new robust QCA tile structure hybridizing rotated and non-rotated cell together resulting lesser kink energy. Different QCA logic primitives (majority/minority logic, fanout tiles, etc.) are made using such hybrid cell structure. The functional characterization using the kink energy and the polarization level of such QCA structures under different cell defects have been thoroughly investigated. The results suggest that the proposed QCA logic primitives have achieved high fault tolerance of 97.43 %. Also, 100 % fault tolerance can be ascertained if the proposed logic circuit drives the correct output with the application of \(\langle \)001, 011\(\rangle \) as a primitive test vector only. A comparative performance of the proposed logic over existing structure makes it more reliable.     

基于相关分析和小波包的配网选线方法的研究

配网系统发生单相接地故障时,单一选线算法都存在着一定的动作死区。基于此提出了融合相关系数分析和小波包单频带分析的双重判据的综合选线算法。通过PSCAD/EMTDC仿真软件,搭建了一个35kV的配网模型验证了2种选线算法的可行性,并通过一次接地实例验证算法的准确性。     

A symmetric quantum-dot cellular automata design for 5-input majority gate

By the inevitable scaling down of the feature size of the MOS transistors which are deeper in nanoranges, the CMOS technology has encountered many critical challenges and problems such as very high leakage currents, reduced gate control, high power density, increased circuit noise sensitivity and very high lithography costs. Quantum-dot cellular automata (QCA) owing to its high device density, extremely low power consumption and very high switching speed could be a feasible competitive alternative. In this paper, a novel 5-input majority gate, an important fundamental building block in QCA circuits, is designed in a symmetric form. In addition to the majority gate, a SR latch, a SR gate and an efficient one bit QCA full adder are implemented employing the new 5-input majority gate. In order to verify the functionality of the proposed designs, QCADesigner tool is used. The results demonstrate that the proposed SR latch and full adder perform equally well or in many cases better than previous circuits.     

Simplified equivalent‐circuit modelling for decoupled and partial decoupled methods in semiconductor device simulation

In this paper, we study the decoupled method which requires less memory on semiconductor device simulation. The decoupled method decouples the three equivalent circuits of semiconductor and solves them sequentially. The three equivalent circuits are formed by formulating the three partial differential equations that describe the electrical behaviour of semiconductor. Since the decoupled method solves one equation in each stage, the decoupled method uses one‐ninth memory space of the coupled method. When decoupling the three equivalent circuits, the decoupled method yields a boundary condition limitation. In order to overcome the limitation, we propose a compromising partial decoupled method which has complete boundary condition and requires four‐ninth memory space of the coupled method. The three methods are compared for computational efficiency and accuracy in the simulation of BJT. The simulation results are identical. Copyright © 2004 John Wiley & Sons, Ltd.     

输电线路工频参数在线测量方法的研究

对比分析几种输电线路工频参数的在线测量方法,认为牛拉法和基于传输线方程的测量方法精确度比较高;通过鲁棒性分析,对这2种算法进一步比较后认为基于传输线方程的算法的鲁棒性相对较好。为了进一步验证该算法,用MATLAB搭建双回线路的模型,仿真计算各参数值,在对两端输入量迭加一定误差后,发现计算结果的误差在可接受范围内,该算法具有一定的实际使用价值。