A simulation study of short channel effects with a QET model based on Fermi–Dirac statistics and nonparabolicity for high-mobility MOSFETs

In this paper, the quantum confinement and short channel effects of Si, Ge, and \(\hbox {In}_{0.53}\hbox {Ga}_{0.47}\)As n-MOSFETs are evaluated. Both bulk and double-gate structures are simulated using a quantum energy transport model based on Fermi–Dirac statistics. Nonparabolic band effects are further considered. The QET model allows us to simulate carrier transport including quantum confinement and hot carrier effects. The charge control by the gate is reduced in the Ge and \(\hbox {In}_{0.53}\hbox {Ga}_{0.47}\)As bulk n-MOSFETs due to the low effective mass and high permittivity. This charge control reduction induces the degradation of short channel effects. In double-gate structures, different improvements of drain induced barrier lowering (DIBL) and subthreshold slope (SS) are seen. The double-gate structure is effective in the suppression of DIBL for all channel materials. The SS degradation depends on channel materials even in double-gate structure.     

An analytical model of triple‐material double‐gate metal–oxide–semiconductor field‐effect transistor to suppress short‐channel effects

This paper presents an analytical subthreshold model for surface potential and threshold voltage of a triple‐material double‐gate (DG) metal–oxide–semiconductor field‐effect transistor. The model is developed by using a rectangular Gaussian box in the channel depletion region with the required boundary conditions at the source and drain end. The model is used to study the effect of triple‐material gate structure on the electrical performance of the device in terms of changes in potential and electric field. The device immunity against short‐channel effects is evaluated by comparing the relative performance parameters such as drain‐induced barrier lowering, threshold voltage roll‐off, and subthreshold swing with its counterparts in the single‐material DG and double‐material DG metal–oxide–semiconductor field‐effect transistors. The developed surface potential model not only provides device physics insight but is also computationally efficient because of its simple compact form that can be utilized to study and characterize the gate‐engineered devices. Furthermore, the effects of quantum confinement are analyzed with the development of a quantum‐mechanical correction term for threshold voltage. The results obtained from the model are in close agreement with the data extracted from numerical Technology Computer Aided Design device simulation. Copyright © 2015 John Wiley & Sons, Ltd.     

Robust Computational Models of Quantum Transport in Electronic Devices

A family of efficient quantum transport models for simulation of modern nanoscale devices is presented. These models are used for quantitative calculations of quantum currents in nanoscale electronic devices within our device simulator software. Specifically, we used them to simulate the tunneling current through thin barrier in vertical-cavity surface-emitting laser (VCSEL), direct and reverse tunnel currents through the tunnel junction, Schottky contact characteristics, and gate induced drain leakage (GIDL).     

Gate leakage behavior of source/drain-to-gate non-overlapped MOSFET structure

In this paper, novel nanoscale MOSFET with Source/Drain-to-Gate Non-overlapped and high-k spacer structure has been demonstrated to reduce the gate leakage current for the first time. The gate leakage behavior of novel MOSFET structure has been investigated with help of compact analytical model and Sentaurus Simulation. Fringing gate electric field through the dielectric spacer induces inversion layer in the non-overlap region to act as extended source/drain region. It is found that optimal source/drain-to-gate non-overlapped and high-k spacer structure has reduced the gate leakage current to great extent as compared to those of an overlapped structure. Further, the proposed structure had improved off current, subthreshold slope and drain induced barrier lowering characteristic with a slight degradation in source/drain series resistance and effective gate capacitance.     

Dual material gate junctionless tunnel field effect transistor

This paper proposes a junctionless tunnel field effect transistor (JLTFET) with dual material gate (DMG) structure and the performance was studied on the basis of energy band profile modulation. The two-dimensional simulation was carried out to show the effect of conduction band minima on the abruptness of transition between the ON and OFF states, which results in low subthreshold slope (SS). Appropriate selection of work function for source and drain side gate metal of a double metal gate JLTFET can also significantly reduce the subthreshold slope (SS), OFF state leakage and hence gives improved I _ON/I _OFF.     

Numerical Analysis of Coaxial Double Gate Schottky Barrier Carbon Nanotube Field Effect Transistors

Carbon nanotube field-effect transistors (CNTFETs) have been studied in recent years as a potential alternative to CMOS devices, because of the capability of ballistic transport. The ambipolar behavior of Schottky barrier CNTFETs limits the performance of these devices. A double gate design is proposed to suppress this behavior. In this structure the first gate located near the source contact controls carrier injection and the second gate located near the drain contact suppresses parasitic carrier injection. To avoid the ambipolar behavior it is necessary that the voltage of the second gate is higher or at least equal to the drain voltage. The behavior of these devices has been studied by solving the coupled Schrödinger-Poisson equation system. We investigated the effect of the second gate voltage on the performance of the device and finally the advantages and disadvantages of these options are discussed.     

The Effective Conduction Band Edge Method of Quantum Correction to the Monte Carlo Device Simulation

To include quantum effects, a quantum correction is made to the semi-classical Monte Carlo (MC) simulation by the effective conduction band edge (ECBE) method. The quantum corrected potential energy can be calculated from the classical potential energy by the ECBE equation and thus the quantum mechanical force in the simulation replaces the classical force. Under the non-equilibrium condition, carriers have a temperature different from the lattice. For the simulation of a double-gate MOSFET, we replace thermal energy in the ECBE equation with the average value of the stress tensor along each transverse line, to account for the variation of the electron “temperature” along the longitudinal direction. A 3 nm thick double gate nMOSFET is simulated. The result shows that electrons now see a higher barrier from the source to the drain if the carrier temperature is considered, resulting in a smaller drain current compared to that obtained from the previous ECBE method.     

Quantum Corrections in the Monte Carlo Simulations of Scaled PHEMTs with Multiple Delta Doping

The effective potential approach which can represent quantum mechanical (QM) confinement at a heterointerface has been incorporated into our Monte Carlo device simulator MC/H2F. The simulator is used to investigate the impact of the quantum corrections on the performance of single and double -doped pseudomorphic high electron mobility transistors scaled to decanano dimensions. The QM confinement in the device channel results in reduction of the drive current and the device transconductance. Its influence increases with the device scaling from 120 to 30 nm gate length and also with increasing the carrier sheet density in the double -doped structures.     

Fully 3D self-consistent quantum transport simulation of Double-gate and Tri-gate 10 nm FinFETs

We utilize a fully self-consistent 3D quantum mechanical simulator based on the Contact Block Reduction (CBR) method to investigate the effects of fin height and unintentional dopant on the device characteristics of a 10-nm FinFET device. The per-fin height off-current is found to be relatively insensitive to fin height while the corresponding per fin height on-current may significantly depend on fin height due to the stronger confinement with decreasing fin height. Also gate leakage is found to show similar behavior as device on-current with decreasing fin height. Tri-gate (TG) FinFET is found to show better performance compared to Double-gate (DG) FinFET, with the exception of gate leakage current. Simulation results show that an unintentional dopant within the channel can significantly alter device characteristics depending on its position and applied biases. In addition, the effects of unintentional dopant are found to be stronger at high drain bias than at low drain bias.     

The impact of high-k gate dielectric and FIBL on performance of nano DG-MOSFETs with underlapped source/drain regions

The impact of high-k gate dielectrics and fringing induced barrier lowering (FIBL) effects on a nano double gate MOSFET is studied over a wide range of dielectric permittivity using ballistic quantum simulation. The simulations are based on self-consistent solution of 2D Poisson equation and Schrödinger equation with open boundary conditions, within the Non-equilibrium Green’s Function formalism. The numerical results show that the use of high-k gate at fixed equivalent oxide thickness (EOT), deteriorates the short channel effects due to FIBL effect. We show that the FIBL can be effectively suppressed by using underlapped source/drain region.     

Quantum Simulation Study of a New Carbon Nanotube Field-Effect Transistor With Electrically Induced Source/Drain Extension

In this paper, we present the unique features exhibited by a proposed structure of coaxially gated carbon nanotube field-effect transistor (CNTFET) with doped source and drain extensions using the self-consistent and atomistic scale simulations, within the nonequilibrium Green's function formalism. In this novel CNTFET structure, three adjacent metal cylindrical gates are used, where two side metal gates with lower workfunction than the main gate as an extension of the source/drain on either side of the main metal gate are biased, independent of the main gate, to create virtual extensions to the source and the drain and also to provide an effective electrical screen for the channel region from the drain voltage variations. We demonstrate that the proposed structure of CNTFET shows improvement in device performance focusing on leakage current, on–off current ratio, and voltage gain. In addition, the investigation of short-channel effects for the proposed structure shows improved drain-induced barrier lowering, hot-carrier effect, and subthreshold swing, all of which can affect the reliability of CMOS devices.      

Monte Carlo analysis of dynamic characteristics and high‐frequency noise performances of nanoscale double‐gate MOSFETs

In this paper, a full‐band Monte Carlo simulator is employed to study the dynamic characteristics and high‐frequency noise performances of a double‐gate (DG) metal–oxide–semiconductor field‐effect transistor (MOSFET) with 30 nm gate length. Admittance parameters (Y parameters) are calculated to characterize the dynamic response of the device. The noise behaviors of the simulated structure are studied on the basis of the spectral densities of the instantaneous current fluctuations at the drain and gate terminals, together with their cross‐correlation. Then the normalized noise parameters (P, R, and C), minimum noise figure (NF_min), and so on are employed to evaluate the noise performances. To show the outstanding radio‐frequency performances of the DG MOSFET, a single‐gate silicon‐on‐insulator MOSFET with the same gate length is also studied for comparison. The results show that the DG structure provides better dynamic characteristics and superior high‐frequency noise performances, owing to its inherent short‐channel effect immunity, better gate control ability, and lower channel noise. Copyright © 2012 John Wiley & Sons, Ltd.     

Analysis of tunneling currents in multilayer black phosphorous and $$\hbox {MoS}_{2}$$ non-volatile flash memory cells

This paper presents a theoretical study of tunneling current density and the leakage current through multi-layer (stacked) trapping layer in the gate dielectric in MOS non-volatile memory devices. Two different 2D materials (\(\hbox {MoS}_{2}\) and black phosphorous) with a combination of high-k dielectric (\(\hbox {HfO}_{2}\)) have been used for the study with differently ordered stacks i.e., as trapping layer and substrate. The material properties of 2D materials like density of states, effective mass and band structure has been evaluated using density functional theory simulations. Using the Maxwell–Garnett effective medium theory we have calculated the effective barrier height, effective bandgap, effective dielectric constant and effective mass of the gate dielectric stacks. By applying WKB approximation in the multi-layer trapping layer we have studied the effect of the direct and Fowler–Nordheim tunneling currents. The leakage current in all the different stack combinations used has also been evaluated. The results obtained have shown to match the required dynamics of a memory device.     

Device circuit co‐design to reduce gate leakage current in VLSI logic circuits in nano regime

In this paper, nanoscale metal–oxide–semiconductor field‐effect transistor (MOSFET) device circuit co‐design is presented with an aim to reduce the gate leakage curren t in VLSI logic circuits. Firstly, gate leakage current is modeled through high‐k spacer underlap MOSFET (HSU MOSFET). In this HSU MOSFET, inversion layer is induced in underlap region by the gate fringing field through high‐k dielectric (high‐k) spacer, and this inversion layer in the underlap region acts as extended source/drain region. The analytical model results are compared with the two‐dimensional Sentaurus device simulation. Good agreement is obtained between the model and Sentaurus simulation. It is observed that modified HSU MOSFET had improved off current, subthreshold slope, and drain‐induced barrier lowering characteristics. Further, modified HSU MOSFET is also analyzed for gate leakage in generic logic circuits. Copyright © 2015 John Wiley & Sons, Ltd.     

Nanoscale circuit implementation using tri-metal gate engineered nanowire MOSFET with gate stack for analog/RF applications

In this work, the potential benefit of tri-metal gate engineered nanowire MOSFET with gate stack for analog/RF applications is developed and presented. A systematic, quantitative investigation of main figure of merit for the device is carried out to demonstrate its improved RF/analog performance. The results show an improvement in drain current, \(I_{\mathrm{on}} /I_{\mathrm{off}}\) ratio, transconductance, unity-gain frequency (\(f_{\mathrm{T}}\)), maximum oscillation frequency (\(f_{\mathrm{max}}\)) providing superior RF performance as compared to single and dual-metal gate stack nanowire MOSFET. The suitability of the device for analog/RF applications is also analyzed by implementing the device in a low-noise amplifier circuit, and the S-parameter values are estimated.     

Accurate modeling of Metal/HfO<Subscript>2</Subscript>/Si capacitors

In this work, we study the differences caused in the Capacitance-Voltage (C-V) characteristics of MOS devices when SiO₂ is replaced by HfO₂ as the gate dielectric. A self-consistent Schrödinger-Poisson solver has been developed to include the effects of quantum confinement and the influence of different parameters such as the effective mass, barrier height, and dielectric constant (κ) of the gate insulator material. Two different devices are considered: A Double Gate MOSFET and a Surrounding Gate Transistor. The validity of the Equivalent Oxide Thickness (EOT) is studied.     

A new F(ast)-CMS NEGF algorithm for efficient 3D simulations of switching characteristics enhancement in constricted tunnel barrier silicon nanowire MuGFETs

In this paper, we present 3D quantum simulations based on Non-Equilibrium Green’s Function (NEGF) formalism using the Comsol Multiphysics^? software and on the implementation of a new Fast Coupled Mode-Space (FCMS) approach. The FCMS algorithm allows one to simulate transport in nanostructures presenting discontinuities, as the normal Coupled Mode-Space (CMS) algorithm does, but with the speed of a Fast Uncoupled-Mode Space (FUMS) algorithm (a faster algorithm that cannot handle discontinuities). We then use this new algorithm to explore the effect of local constrictions on the performance of nanowire MultiGate Field-Effect Transistors (MuGFETs). We show that cross-section variations in a nanowire result in the formation of energy barriers that can be used to improve the on/off current ratio and switching characteristics of transistors: (1) A small constriction resulting in a barrier of the order of a 0.1 eV can be used as an effective means to improve the subthreshold slope and minimize the on/off current ratio degradation resulting from SD tunneling in ultra scaled transistor, and (2) We also report a new variable barrier transistor (VBT) device concept that is able to achieve sub-kT/q subthreshold slope without using impact ionization or band-to-band tunneling. Intra-band tunneling through constriction barriers is used instead. The device is, therefore, fully symmetrical and can operate at very low supply voltages. A subthreshold slope as low as 56.5 mV/decade is reported at T=300 K. The VBT reported here breaks the 60 mV/dec barrier over more than five decades of subthreshold current, which is the widest current range reported so far.     

An analytic drain current model for long‐channel undoped gate stack surrounding‐gate MOSFETs including interface fixed charges

On the basis of the exact solution of Poisson's equation and Pao–Sah double integral for long‐channel bulk MOSFETs, a continuous and analytic drain current model for the undoped gate stack (GS) surrounding‐gate (SRG) metal–oxide–semiconductor field‐effect transistor (MOSFET) including positive or negative interface fixed charges near the drain junction is presented. Considering the effect of the interface fixed charges on the flat‐band voltage and the electron mobility, the model, which is expressed with the surface and body center potentials evaluated at the source and drain ends, describes the drain current from linear region to saturation region through a single continuous expression. It is found that the surface and body center potentials are increased/decreased in the case of positive/negative interface fixed charges, respectively, and the positive/negative interface fixed charges can decrease/increase the drain current. The model agrees well with the 3D numerical simulations and can be efficiently used to explore the effects of interface fixed charges on the drain current of the gate stack surrounding‐gate MOSFETs of the charge‐trapped memory device. Copyright © 2013 John Wiley & Sons, Ltd.     

Impact of high-k spacer on device performance of a junctionless transistor

The impact of spacer dielectric on both sides of gate oxide on the device performance of a symmetric double-gate junctionless transistor (DGJLT) is reported for the first time. The digital and analog performance parameters of the device considered in this study are drain current (I _D ), ON-state to OFF-state current ratio (I _ON /I _OFF ), subthreshold slope (SS), drain induced barrier lowering (DIBL), intrinsic gain (G _m R _O ), output conductance (G _D ), transconductance/drain current ratio (G _m /I _D ) and unity gain cut-off frequency (f _T ). The effects of varying the spacer dielectric constant (k _sp ) on the electrical characteristics of the device are studied. It is observed that the use of a high-k dielectric as a spacer brings an improvement in the OFF-state current by more than one order of magnitude thereby making the device more scalable. However, the ON-state current is only marginally affected by increasing dielectric constant of spacer. The effects of spacer width (W _sp ) on device performance are also studied. ON-state current marginally decreases with spacer width.     

Numerical study of the thermoelectric power factor in ultra-thin Si nanowires

Low dimensional structures have demonstrated improved thermoelectric (TE) performance because of a drastic reduction in their thermal conductivity, ?? _l . This has been observed for a variety of materials, even for traditionally poor thermoelectrics such as silicon. Other than the reduction in ?? _l , further improvements in the TE figure of merit ZT could potentially originate from the thermoelectric power factor. In this work, we couple the ballistic (Landauer) and diffusive linearized Boltzmann electron transport theory to the atomistic sp³d⁵s*-spin-orbit-coupled tight-binding (TB) electronic structure model. We calculate the room temperature electrical conductivity, Seebeck coefficient, and power factor of narrow 1D Si nanowires (NWs). We describe the numerical formulation of coupling TB to those transport formalisms, the approximations involved, and explain the differences in the conclusions obtained from each model. We investigate the effects of cross section size, transport orientation and confinement orientation, and the influence of the different scattering mechanisms. We show that such methodology can provide robust results for structures including thousands of atoms in the simulation domain and extending to length scales beyond 10?nm, and point towards insightful design directions using the length scale and geometry as a design degree of freedom. We find that the effect of low dimensionality on the thermoelectric power factor of Si NWs can be observed at diameters below ??7?nm, and that quantum confinement and different transport orientations offer the possibility for power factor optimization.