改进型高速高精度CORDIC算法及其在DDFS中的应用

提出了一种新的选择迭代式高速高精度CORDIC（COrdinate Rotation Digital Computer）算法.基于表驱动法缩小目标旋转角度,通过改进的基本角度选择方法旁路不必要的迭代;并以移位和减法实现幅度校正,减小硬件资源消耗.设定角度误差小于10^-5rad时,迭代次数减小至7次以下.在DDFS（Direct Digital Frequency Synthesizer）的应用中,利用区间压缩技术在Xilinx的FPGA中实现20位定点小数电路设计.仿真及实测结果表明,该算法幅度误差小于2×10^-5,输出延时不大于43.5ns,同时硬件资源消耗不增加.     

基于改进Scaling-Free CORDIC算法的DDS

直接数字频率合成器(Direct Digital Synthesizer,DDS)在现代数字通信系统中有非常重要的应用。基于CORDIC算法的DDS在高速、高精度信号源领域已得到广泛应用,但传统的CORDIC算法存在迭代次数多、硬件消耗资源大、缩放因子补偿误差等问题。文章提出固定角度的传统迭代预旋转和分段双步SF(Scaling-Free)CORDIC算法旋转方式,有效减少了算法的迭代次数,并且采用区间映射将收敛区间扩展到[0,2π]。结果表明,该算法在保持高计算精度的同时减少了迭代次数和面积消耗。基于此算法的DDS产生的正交信号具有精度高、噪声低、线性度好等优点。     

免缩放因子双步旋转CORDIC算法

集成电路设计中经常使用CORDIC算法实现高效的向量旋转操作.当前对该算法的研究热点集中在减少该算法的迭代次数、扩展其收敛范围以及降低缩放因子补偿操作的代价等问题上.本文提出免缩放因子的双步旋转CORDIC算法使用双步旋转策略,减少了免缩放因子CORDIC算法的迭代次数,将收敛区间扩展到了整个圆周区间.实验结果表明,该算法保持高计算精度的同时减少了迭代次数和面积消耗.     

基于Parallel_CORDIC的高精度高速度直接数字频率合成器的FPGA实现

本文提出了一种直接数字频率合成器（DDFS）的设计,以Parallel_CORDIC（COrdinate Rotation Digital Computer）算法模块替代传统的查找表方式,实现了相位与幅度的一一对应,输出相位完全正交的正余弦波形;同时应用旋转角度预测及4：2的进位保存加法器（CSA）技术,将速度比传统CORDIC算法提高41.7%,精度提高到10^-4.最后以Xilinx的FPGA硬件实现整个设计.     

一种优化的最大逼近角的CORDIC算法改进

本文提出了一种优化的最大逼近角的CORDIC算法改进,低位通过最高非零位最大逼近角的计算方法实现,高位通过高速进位加法器的结构实现.采用基本角度线性编码方式,不但使流水线方式容易实现,而且旋转方向也容易确定,同时减少了迭代次数和增加迭代速度,精度越高优势越明显.算法实现不需要ROM,能大大节省硬件资源,可以应用在高精度高速度的运算领域.     

一种80位扩展双精度浮点三角函数运算单元的设计

三角函数求值这一运算计算过程复杂,硬件较难实现.针对这一问题,通过改进CORDIC算法,实现了兼容SPARC处理器和INTEL处理器浮点标准的80位高精度浮点三角函数的计算.在算法设计中,将函数的计算范围扩展至-π~+π,并且实现了迭代次数的可配置.最后验证了算法的正确性与完整性,分析了运算过程中迭代次数与精度的关系.结果表明,运算的精度提高到10-14.     

一种基于贪婪算法的CORDIC改进算法

针对传统串行坐标旋转数字计算方法(CORDIC)耗时且占用较多资源的缺点,提出了一种旋转模式下CORDIC算法的新型改进算法,该改进算法可用来代替直接数字频率合成器(DDS)查找表进行正余弦的计算。通过采用贪婪算法实现对CORDIC旋转方向与旋转角度的优化,从而可以达到串行转并行和减少迭代次数、节约资源的目的。该算法可以应用于三角函数的复杂函数的硬件实现中。仿真结果表明,在迭代次数相同的情况下,改进算法较传统算法可以获得更高的精度。最后,在Xilinx FPGA的Spartan-3E芯片上实现了改进的CORDIC结构。与传统CORDIC算法相比,在运算精度为10-5时,可以节省Slices、LUTs(Look Up Tables)资源分别为28%和25%。     

基于FPGA的CORDIC算法实现

针对传统CORDIC算法延时大,消耗资源多的缺点,在平行CORDIC算法的基础上提出了一种优化的平行算法,利用二进制转两极算法和微旋转角度编码对低部和高部的旋转方向进行预测,并在高部旋转中利用正反旋转抵消的策略来进一步减少旋转次数,提高运算速度。采用FPGA对提出的算法进行了硬件设计和验证,结果表明,计算迭代次数少,资源消耗少,精度较传统算法来说都有了明显改善。     

改进型CORDIC算法的研究与实现

CORDIC的运算速度问题是研究的热点。为了解决CORDIC运算速度慢的问题,采用跳过零点思想,跳过输入相位值中为0的位,有效的减少了迭代次数。利用ISE仿真技术多次仿真综合。验证出改进型的CORDIC算法,在保证算法的运算精度基础上,明显地改善了CORDIC的运算速度,尤其针对于一些特殊的旋转角度,利用极少的旋转就达到结果。最终利用FPGA实现改进后CORDIC算法。     

高性能HPOR CORDIC算法及实现

CORDIC算法在通信和图像处理等各个领域有着广泛的应用,但是浮点CORDIC由于迭代延时大且实现复杂没有得到很好的应用,本文提出了一种修正浮点CORDIC算法：高精度顺序迭代HPORCORDIC。该算法以接近定点的运算代价完成浮点运算迭代,运算速度和硬件实现规模与定点CORDIC相当,运算精度与浮点CORDIC相当,克服了定点CORDIC运算精度差,浮点CORDIC迭代延时大、实现复杂的问题。该算法既可用于通用微处理器的设计,也可用于高性能DSP的设计。     

基于CORDIC算法的数字中频检波技术研究

为了解决模拟包络检波器受温度影响大、测试精度不高且丢失相位信息等问题,提出了一种基于CORDIC算法的数字中频检波方案,完成幅度、相位及频率检测功能.首先讨论了数字检波的工作原理,分析了其数学模型,然后给出了基于CORDIC算法的幅度和相位检测方案,并在数字鉴相基础上,介绍了使用一阶差分结构实现数字鉴频的方法,同时分析了差分鉴频中出现的相位模糊问题,给出了如何提高鉴频精度的方法.最后,使用FPGA实现了基于CORDIC算法的数字检波器.通过计算机仿真和应用实例表明,基于CORDIC算法的数字中频检波方案是可行的,并且可以获得较高的测量精度.     

Fast and precise Fourier transforms

Many applications of fast Fourier transforms (FFTs), such as computer tomography, geophysical signal processing, high-resolution imaging radars, and prediction filters, require high-precision output. An error analysis reveals that the usual method of fixed-point computation of FFTs of vectors of length 2^l leads to an average loss of l/2 bits of precision. This phenomenon, often referred to as computational noise, causes major problems for arithmetic units with limited precision which are often used for real-time applications. Several researchers have noted that calculation of FFTs with algebraic integers avoids computational noise entirely. We combine a new algorithm for approximating complex numbers by cyclotomic integers with Chinese remaindering strategies to give an efficient algorithm to compute b-bit precision FFTs of length L. More precisely, we approximate complex numbers by cyclotomic integers in Z[e(2πi/2ⁿ)] whose coefficients, when expressed as polynomials in e(2πi/2ⁿ), are bounded in absolute value by some integer M. For fixed n our algorithm runs in time O(log(M)), and produces an approximation with worst case error of O(1/M(2^n-2-1)). We prove that this algorithm has optimal worst case error by proving a corresponding lower bound on the worst case error of any approximation algorithm for this task. The main tool for designing the algorithms is the use of the cyclotomic units, a subgroup of finite index in the unit group of the cyclotomic field. First implementations of our algorithms indicate that they are fast enough to be used for the design of low-cost high-speed/high-precision FFT chips     

On multilevel codes and iterative multistage decoding

This paper develops an approach to iterative multistage decoding of multilevel codes. This involves passing reliability information to previous and subsequent decoders instead of only hard decisions to subsequent decoders. The paper also develops an adaptive version of the suboptimal soft output decoding algorithm of Picart and Pyndiah (1996). This adaptive algorithm provides a gain of approximately 0.24 dB at a bit error rate (BER) of 10^-5 after four iterations and approximately 0.43 dB after ten iterations over the algorithm of Picart et al. If the adaptive algorithm is used in conjunction with iterative multistage decoding then a gain of approximately 0.62 dB is obtained at a BER of 10^-5 after four iterations and approximately 0.9 dB after ten iterations over the algorithm of Picart et al     

Simple MAP acceleration using pre-decoding for punctured turbo code

A simple algorithm that accelerates maximum a posteriori (MAP) decoding of a punctured turbo code is proposed. A turbo code consists of a data bit stream and a plurality of parity bit streams, some of which possibly had components removed by puncturing. The proposed method performs pre-decoding and re-encoding to find omitted parity symbols of the received sequence. This protocol provides a turbo-coded system of between rate-1/2 and rate-1/3. Simulation results show that the proposed algorithm reduces the number of iterations, which is equivalent to the decoding delay, to 50% for approaching a bit error rate (BER) of approximately 3.38 times 10^-3 at 1.0 dB.     

MB-OFDM-UWB系统基于时域扩展的盲频率跟踪算法

对多频带正交频分复用超宽带系统同步技术进行研究,提出一种基于时域扩展技术（TDS）的盲载波频偏（CFO）跟踪算法。利用数据符号与其时域扩展符号的特殊映射关系,在时域和频域分别推导出残余载波频偏的盲估计公式,并构建相应的时频跟踪环路。仿真结果表明,该盲算法具有比导频辅助法更优的跟踪性能。10dB信噪比下,基于TDS进行时频跟踪的残余CFO均方根误差均达到2×10?4,系统误比特率可达10?6数量级。     

CORDIC Processor for Variable-Precision Interval Arithmetic

In this paper we present a specific CORDIC processor for variable-precision coordinates. This system allows us to specify the precision to perform the CORDIC operation, and control the accuracy of the result, in such a way that re-computation of inaccurate results can be carried out with higher precision. It permits a reliable and accurate evaluation of a wide range of elementary functions. The specific architecture designed greatly improves the computational time of previous solutions based on classic polynomial approximation. For controlling error in numerical computation (where intervals are normally narrow) the proposed design performs an interval operation in a time close to that of a point operation.     

Mixed-radix,virtually scaling-free CORDIC algorithm based rotator for DSP applications

In this work, we proposed a novel Coordinate Rotation DIgital Computer (CORDIC) rotator algorithm that converges faster by performing radix-2,4 and 16 CORDIC iterations while maintaining the scale factor implicitly constant. A mixed-radix is used to achieve convergence faster to reduce the computational latency of the CORDIC algorithm. The main concern of the higher radix CORDIC algorithm is the compensation of a variable scale factor. To solve this problem, the Taylor series approximation of sine and cosine is proposed for a higher radix CORDIC algorithm to achieve the scaling-free rotation of the two-dimensional vector. The scaling-free rotation of the proposed CORDIC algorithm removes the read-only memory (ROM) needed to store scale factor of higher radix CORDIC algorithm. Further, the proposed CORDIC algorithm is designed in rotation mode and optimized by removing the Z datapath for the digital signal processing (DSP) applications for which the angle of rotation is known in advance. Finally, the multipath delay commutator (MDC) fast Fourier transform (FFT) algorithm is implemented with the proposed CORDIC algorithm based rotator on FPGA. The proposed design is compared with existing designs. In a comparison between the radix-16 CORDIC rotator based FFT implementation and our proposed implementation, it has been found out that implementation proposed in this article has used 17% fewer resources.     

基于改进CORDIC算法的数字预失真实现

针对传统CRODIC算法存在的角度扩展、迭代复杂度等问题,在旋转模式下提出一种改进型CORDIC算法。对于旋转角度范围的扩展,采取将向量限制在第一和第四象限,旋转最后再根据输入向量符号判断旋转角度值;对于迭代复杂度,采用跳跃旋转方式来减少迭代次数。最后在Quartus软件上实现了该改进算法,并且将改进后的CORDIC算法应用于数字预失真技术,在FPGA上设计实现。仿真与实验结果表明:与传统的CORDIC算法相比,改进算法减少了硬件的开销,运算速度和精度都有很大改进,能够快速提取预失真参数,显著提高功率放大器的线性度。