一种NAND型三维多层1TXR阻变存储器设计

随着存储器市场逐渐受消费电子的驱动,对高密度低成本的存储需求正在不断增加.阻变存储器正在成为新型非挥发存储器的研究热点.提出一种适用于未来高密度应用的与非(NAND)型共享选通管的三维多层1TXR阻变存储器概念.在0.13 μm工艺下,以一个使用8层金属堆叠的1T64R结构为例,其存储密度比传统的单层1T1R结构高500%.提出了相关的读写操作方法来防止由漏电流造成的误写和误读并且降低功耗.     

一种有效的3D存储器内建自修复方案

与2D存储器相比,3D存储器能够提供更大的容量、更高的带宽、更低的延迟和功耗,但成品率低。为了解决这个问题,提出一种有效的3D存储器内建自修复方案。将存储阵列的每一行或每一列划分成几个行块或列块,在不同层的行块或列块之间进行故障单元的映射,使不同层同一行或同一列的故障在逻辑上映射到同一层中,从而使一个冗余行或冗余列能够修复更多的故障,大大增加了冗余资源利用率和故障修复率。实验结果表明,与其他修复方案相比,该方案的修复率更高,实现相同修复率所需的冗余资源更少,增加的面积开销几乎可忽略不计。     

试论视频服务器技术及其应用

理想的网络存储系统为服务器提供一种共享式存储结构，它通过同时为每个服务器提供共享存储空间，而减少所需的存储器总数，而且与各自独立的存储系统相比自动简化基本的网络存储结构如右图所示.     

试论视频服务器技术及其应用

一、视频服务器网络存储系统1.系统描述 理想的网络存储系统为服务器提供一种共享式存储结构。它通过同时为每个服务器提供共享存储空间,而减少所需的存储器总数,而且与各自独立的存储系统相比自动简化。基本的网络存储结构如右图     

基于DWL概念的嵌入式存储器内建自修复方法

嵌入式存储器在SoC技术中逐渐成为主体设计结构,由于存储器存在成品率的问题,所以在存储器中设计了内建自测试和内建自修复的策略来解决,其中主要是:基于冗余行的修复策略、基于冗余列的修复策略和基于冗余字的修复策略,然而,在存储器中采用一维冗余块修复策略需要增加更多的冗余块,如果采用二维冗余块修复虽然提高了修复率,但是使得其稳定性和可靠性降低了,为此改进了一种基于DWL修复概念的策略,使其不仅保持了DWL结构的低功耗、提高了冗余资源的利用率,而且快速访问的特性,从而提高了存储器的故障修复率。     

三维存储器的存储单元形状对其性能的影响北大核心

简要介绍了三维存储器出现的背景和几种得到广泛关注的三维存储器;建立模型分析了位成本缩减(BiCS)、垂直堆叠存储阵列(VSAT)和垂直栅型与非闪存阵列(VG-NAND)三种代表性的三维存储器的存储单元的形状对其性能的影响,从理论分析的角度比较了三种存储单元结构对其存储性能的影响;采用Sentaurus软件对三种存储单元的性能进行仿真,从编程/擦除时间、存储窗口和保持性能三个方面比较了三种存储单元结构的存储性能。理论分析结果和仿真结果都一致地表明BiCS结构的圆柱孔形存储单元比其他两种存储单元更有优势。     

波导多层只读光卡及其软刻印制作方法研究

将波导多层存储与光卡存储技术相结合,提出了一种波导多层光卡存储器的结构方案和软刻印制作方法.采用折射率高的薄波片作为芯层材料、折射率低的透明硅橡胶作为包层材料,利用软刻印方法将信息复制在硅橡胶表面,制作出10层光卡.信息检测结果表明,每一层数据清晰可见,相邻层间无明显干扰.     

基于跨度和虚拟层的三维芯核测试外壳扫描链优化方法

为减少三维芯核绑定前和绑定后的测试时间,降低测试成本,提出了基于跨度和虚拟层的三维芯核测试外壳扫描链优化方法.所提方法首先通过最大化每条测试外壳扫描链的跨度,使得绑定前高层电路和低层电路的测试外壳扫描链数量尽可能相等.然后,在TSVs(Through Silicon Vias)数量的约束下,逐层的将虚拟层中的扫描元素分配到测试外壳扫描链中,以平衡绑定前后各条测试外壳扫描链的长度.实验结果表明,所提方法有效地减少了三维芯核绑定前后测试的总时间和硬件开销.     

异构多核SoC处理器内部存储架构优化

异构多核技术的发展使微处理器的性能有了较大提升,而处理器与外部存储器之间的带宽差异限制了处理器的性能发挥,“存储墙”问题日益严重。针对一种用于高密度计算的异构多核SoC系统,文中提出了一套存储设计方案。该方案通过复用一些长时间闲置的本地空闲存储资源作为二级共享缓存来增加访存带宽,减少访问外部存储频率。分布式高速共享二级缓存结合多路并行访问外部存储的层次化存储结构,缓解了系统处理数据与外部存储器间的速度差异,提高了数据的存取效率,优化了系统的性能。综合资源消耗和计算效率,文中所提设计相比普通二级缓存节约了69.36%的片上SRAM资源,相比无缓存结构提高了41.2%的加速比,整体任务计算时间平均减少了约40.6%。     

多处理器的多重处理软件

世界上最美妙的编程工作是程序员编写应用软件时不必考虑运行的目标系统;处理器所依赖的诸如高速缓存大小、存储器带宽及其他一些因素将被忽略;与多处理器(MP)结构相关的存储器共享、处理器数量和网络带宽等也不用考虑;当然,还提供以最小工作量就可以自动给出高效执行程序的工具。今天使用的编译技术能优化处理器结构,编译程序甚至在共享存储的多处理器系统上也可以工作得很好。但是在下一个世纪,我们将不得不研制工具简化分布式存储的多处理器系统的工作。简化数据流软件库使用的努力正在进行之中。甚至在致力于使这种性能标准化,这将导致应用软件具有可移植性。真正的挑战在于自动地分解应用软件,使它在多处理器上运行。研究已经开始,适用的解决方案将不会     

A Die‐Selection Method Using Search‐Space Conditions for Yield Enhancement in 3D Memory

Three‐dimensional (3D) memories using through‐silicon vias (TSVs) as vertical buses across memory layers will likely be the first commercial application of 3D integrated circuit technology. The memory dies to stack together in a 3D memory are selected by a die‐selection method. The conventional die‐selection methods do not result in a high‐enough yields of 3D memories because 3D memories are typically composed of known‐good‐dies (KGDs), which are repaired using self‐contained redundancies. In 3D memory, redundancy sharing between neighboring vertical memory dies using TSVs is an effective strategy for yield enhancement. With the redundancy sharing strategy, a known‐bad‐die (KBD) possibly becomes a KGD after bonding. In this paper, we propose a novel die‐selection method using KBDs as well as KGDs for yield enhancement in 3D memory. The proposed die‐selection method uses three search‐space conditions, which can reduce the search space for selecting memory dies to manufacture 3D memories. Simulation results show that the proposed die‐selection method can significantly improve the yield of 3D memories in various fault distributions.     

Yield Enhancement Techniques for 3D Memories by Redundancy Sharing among All Layers

Three‐dimensional (3D) memories using through‐silicon vias (TSVs) will likely be the first commercial applications of 3D integrated circuit technology. A 3D memory yield can be enhanced by vertical redundancy sharing strategies. The methods used to select memory dies to form 3D memories have a great effect on the 3D memory yield. Since previous die‐selection methods share redundancies only between neighboring memory dies, the opportunity to achieve significant yield enhancement is limited. In this paper, a novel die‐selection method is proposed for multi‐layer 3D memories that shares redundancies among all of the memory dies by using additional TSVs. The proposed method uses three selection conditions to form a good multi‐layer 3D memory. Furthermore, the proposed method considers memory fault characteristics, newly detected faults after bonding, and multiple memory blocks in each memory die. Simulation results show that the proposed method can significantly improve the multi‐layer 3D memory yield in a variety of situations. The TSV overhead for the proposed method is almost the same as that for the previous methods.     

A new accurate yield prediction method for system-LSI embedded memories

The authors propose a new accurate yield prediction method for system-LSI embedded memories to improve the productivity of chips. Their new method is based on the failure-related yield prediction method in which failure bits in memory are tested to see whether they are repairable or not by using built-in redundancies. The important concept of the new method is called "repairable matrix' (RM). In RM, rm/sub ij/=1 means that i row redundancy sets and j column redundancy sets are needed for repair, where rm/sub ij/ is an element of the matrix. Here, RM can indicate all the candidate combinations of the number of row and column redundancy sets for repair. The new yield prediction method using RM solves two problems, "asymmetric repair' and "link set.' These have a significant effect on accurate yield prediction but have not yet been approached by conventional analytical methods. The calculation of yield by the new method is demonstrated in two kinds of advanced memory devices that have different design rules, failure situations, and redundancy designs. The calculated results are consistent with the actual yield. On average, the difference in accuracy between the new method and conventional analytical methods is about 5%.     

Fault tolerance techniques for high capacity RAM

As the complexity and size of the embedded memories keep increasing, improving the yield of embedded memories is the key step toward improving the overall chip yield of a SOC design. The most well known way to improve the memory yield is by using redundant elements to replace the faulty cells. However, the repair efficiency mainly depends on the type, and the amount of redundancy; and on the redundancy analysis algorithms. Therefore, new types of redundancy based on divided bit-line (DBL), and divided word-line (DWL) techniques are proposed in this work. A memory column (row), including the redundant column (row), is partitioned into column blocks (row blocks), respectively. A row/column block is used as the basic replacement element instead of a row/column for the traditional approaches. Based on the new types of redundancy, three types of fault-tolerant memory (FTM) systems are also proposed. If a redundant row/column block is used as the basic replacement element, then the row block-based FTM (RBFTM)/column block-based (CBFTM) system is used. If both the DWL, and DBL techniques are implemented onto a memory chip, then the hybrid FTM (HFTM) system is achieved. The storage and remapping of faulty addresses can be implemented with a CAM (content addressable memory) block. To achieving better repair efficiency, a novel hybrid block-repair (HBR) algorithm is also proposed. This algorithm is suitable for hardware implementation with negligible overhead. For the HFTM system, the hardware overheads are less than 0.65%, and 0.7% for 64-Kbit SRAM, and 8-Mbit DRAM, respectively. Moreover, the repair rate can be improved significantly. Experimental results show that our approaches can improve the memory fabrication yield significantly. The characteristics of low power and fast access time of DBL and DWL techniques are also preserved.     

Yield enhancement techniques for 3-dimensional random access memories

As the advances of process technology keep growing, three-dimensional (3D) integration with through silicon vias is a new alternative solution to extend Moore’s law especially for random access memories (RAMs). In general, the reliability and fabrication yield of the traditional 2D memories can be improved by the incorporation of some form of redundancy. However, for 3D integration, the scenarios for the repair process are totally different. The redundancy exclusively added in a memory tier can also be reused to repair defects in the other memory tier after the bonding process. That is, the concept of inter-tier redundancy can be exploited to further increase the yield of 3D memories. Die-to-die and die-to-wafer bonding can be adopted. In this paper, we propose an efficient die-stacking flow and the corresponding built-in self-repair architectures for yield enhancement of 3D memories. The matching problem for die stacking can be converted into a bipartite graph maximal matching problem and the traditional algorithm can be used to solve this problem. Experimental results show that the proposed stacking flow, algorithm, and the corresponding BISR (built-in self-repair) architecture can improve fabrication yield significantly.     

Efficient BISR Techniques for Embedded Memories Considering Cluster Faults

Instead of the traditional spare row/column redundancy architectures, block-based redundancy architectures are proposed in this paper. The redundant rows/columns are divided into row/column blocks. Therefore, the repair of faulty memory cells can be performed at the row/column-block level. Moreover, the redundant row/column blocks can be used to replace faulty cells anywhere in the memory array. This global characteristic is helpful for repairing cluster faults. The proposed redundancy architecture can be easily integrated with the embedded memory cores. Based on the proposed global redundancy architecture, a heuristic modified essential spare pivoting (MESP) algorithm suitable for built-in implementation is also proposed. According to experimental results, the area overhead for implementing the MESP algorithm is very low. Due to efficient usage of redundancy, the manufacturing yield, repair rate, and reliability can be improved significantly.      

Optimization Methods for Post-Bond Testing of 3D Stacked ICs

Testing of three-dimensional (3D) stacked ICs (SICs) is starting to receive considerable attention in the semiconductor industry. Since the die-stacking steps of thinning, alignment, and bonding can introduce defects, there may be a need to test multiple subsequent partial stacks during 3D assembly. We address the problem of test-architecture optimization for 3D stacked ICs to minimize overall test time when either the complete stack only, or the complete stack and multiple partial stacks, need to be tested. A general solution to this problem provides several options for 3D stack testing in a unified framework. We show that optimal test-architecture solutions and test schedules for multiple test insertions are different from their counterparts for a single final stack test. In addition, we present optimization techniques for the testing of TSVs and die-external logic in combination with the dies in the stack.