基于增强型延时感知CSE算法的AES S盒电路优化设计

针对高级加密标准（AES）S-盒优化,提出了一种增强型延时感知公共项消除（CSE）算法.该算法能够在不同延时约束条件下优化多常数乘法运算电路,并给出从最小延时到最小面积全范围的面积-延时设计折中.采用该算法优化了基于冗余有限域算术的S盒实现电路,确定了延时最优、面积最优的两种S盒构造.实例优化结果表明所提出算法的优化效率高、优化结果整体延时小.所设计的S盒电路基于65nm CMOS工艺库综合,结果表明,对比于已有文献中S盒复合域实现电路,所提出面积最优S盒电路的面积-延时积最小,比目前最小面积与最短延时的S盒组合逻辑分别减少了17.58%和19.74%.     

利用奇偶树实现测试响应压缩

为了减少利用奇偶树压缩测试响应时的邦联覆盖损失,提出了一种输出端分组压缩的方法。遇敏感邦联对输出端的影响把电路的输出疝集合分成若干子集,依然再把每个子集中的输出连接到各自的奇偶树,构成一个奇偶树集,从而可以实现对偶敏感故障的检测,进而提高对可检测邦联的覆盖。最后,分析了由于奇偶树的引入带来的故障覆盖率的损失及奇偶树中故障的检测。     

基于March X算法的SRAM BIST的设计

针对LS-DSP中嵌入的128kb SRAM模块,讨论了基于March X算法的BIST电路的设计.根据SRAM的故障模型和测试算法的故障覆盖率,讨论了测试算法的选择、数据背景的产生:完成了基于March X算法的BIST电路的设计.128kb SRAM BIST电路的规模约为2000门,仅占存储器面积的1.2%,故障覆盖率高于80%.     

基于多项式基的Camellia算法S盒硬件优化

该文提出一种基于不可约多项式的Camellia算法S盒的代数表达式，并给出了该表达式8种不同的同构形式。然后，结合Camellia算法S盒的特点，基于理论证明给出一种基于多项式基的S盒优化方案，此方法省去了表达式中的部分线性操作。相对于同一种限定门的方案，在中芯国际(SMIC)130 nm工艺库中，该文方案减少了9.12%的电路面积；在SMIC 65 nm工艺库中，该文方案减少了8.31%的电路面积。最后，根据Camellia算法S盒设计中的计算冗余，给出了2类完全等价的有限域的表述形式，此等价形式将对Camellia算法S盒的优化产生积极影响。     

H.264帧内模式快速选择算法研究

在对校验模型帧内预测算法分析的基础上,提出了一种帧内模式快速选择算法:在帧内编码中采用亮色分离方案对模式进行选择,在帧间编码中利用最佳帧间模式信息对帧内预测模式进行选择.实验证明,与原校验模型JM72相比,平均编码速度提高约29%,亮度PSNR平均下降在0.01 dB之内,平均比特率上升约0.34%.     

我国互联网用户数预测研究

文章研究了利用Bass模型预测我国互联网用户数的方法.首先对Bass模型进行了描述,然后通过已有数据确定了Bass模型参数,最后利用该模型预测了我国互联网用户数并进行了误差分析.从预测结果中可以大致看出我国互联网用户达到饱和的时间,为今后带宽的预测打下了基础.文章最后给出了Bass模型的适用范围与参数确定方法,同时也提出了几种改善预测精度的方案.     

量子逻辑电路故障检测定位及自修复方法研究

针对量子逻辑电路规模逐渐增大,电路可靠性逐渐下降的问题,提出基于单个量子逻辑门在线故障检测定位方法,该方法使用新构造的检测信号生成门与故障检测门,利用奇偶保持特性判断待测量子逻辑门是否发生故障,同时在设计过程中对信号检测电路进行检验,保证检测电路的正确性。此外提出了基于硬件冗余的量子逻辑电路自修复设计方法。实验结果表明,文中故障检测方法在量子门和垃圾位等性能指标上相对已有方法均有了改进,首次实现的量子逻辑电路的自修复设计大大提高了电路的容错能力和可靠性。     

一种基于耦合线和环形微带线的负群时延电路

负群时延电路(NGDC)在微波系统中有着广泛应用,文中提出了一种基于有损耦合线和环形微带线的负群时延电路。该电路由耦合线和微带传输线组成。基于射频领域中偶模-奇模分析方法,分析该电路的偶模和奇模的输入导纳,得到电路的S 参数。利用HFSS 电磁仿真软件对该负群时延电路结构做了优化设计,实物加工并测试。测试结果表明:在中心频率2.36 GHz 时,该电路的负群时延值约为-1.4 ns,插入损耗S21约为-3.9 dB,反射系数S11约为-9.5 dB,实测与仿真结果吻合。这种新颖的负群时延电路结构简单、信号损耗小、易于加工,可用于微波和无线通信等领域。     

高精度光纤陀螺检测电路串扰自检测研究

光纤陀螺检测电路应用过程中,受到自检测方案的影响,导致串扰故障检测所需测试矢量较多。因此,提出高精度光纤陀螺检测电路串扰自检测研究。分析光纤陀螺数字闭环检测原理,并提取检测电路串扰特征。根据闭环电路的连续信号微分方程,计算等效模拟输入转速。结合数字阶梯波算法,设计电路串扰检测方案。再计算地球自转角速率的分量测量死区,得到电路串扰测量结果。仿真结果表明：所提出的串扰自检测方法,与嵌入式“反射器”的新型谐振陀螺仪和多导体传输线串扰不确定性问题的计算方法相比,当串扰故障覆盖率为80%,本文方法的矢量数量为46个,降低了自测试所需的成本。     

基于可配置LFSR的低功耗确定性矢量生成技术的研究

针对组合电路内建自测试过程中的功耗和故障覆盖率等问题,提出了一种能获得较高故障覆盖率的低功耗测试矢量生成方案。该方案先借助A talanta测试矢量生成工具,针对不同的被测电路生成故障覆盖率较高的测试矢量,再利用插入单跳变测试矢量的方法以及可配置线性反馈移位寄存器生成确定性测试向量的原理,获得低功耗测试矢量。通过对组合电路集ISCAS’85的实验,证实了这种测试生成方案的有效性。     

Fault Detection Structures of the S-boxes and the Inverse S-boxes for the Advanced Encryption Standard

Fault detection schemes for the Advanced Encryption Standard are aimed at detecting the internal and malicious faults in its hardware implementations. In this paper, we present fault detection structures of the S-boxes and the inverse S-boxes for designing high performance architectures of the Advanced Encryption Standard. We avoid utilizing the look-up tables for implementing the S-boxes and the inverse S-boxes and their parity predictions. Instead, logic gate implementations based on composite fields are used. We modify these structures and suggest new fault detection schemes for the S-boxes and the inverse S-boxes. Using the closed formulations for the predicted parity bits, the proposed fault detection structures of the S-boxes and the inverse S-boxes are simulated and it is shown that the proposed schemes detect all single faults and almost all random multiple faults. We have also synthesized the modified S-boxes, inverse S-boxes, mixed S-box/inverse S-box structures, and the whole AES encryption using the 0.18 μ CMOS technology and have obtained the area, delay, and power consumption overheads for their fault detection schemes. Furthermore, the fault coverage and the overheads in terms of the space complexity and time delay are compared to those of the previously reported ones.     

A Binary Decision Diagram based on-line testing of digital VLSI circuits for feedback bridging faults

Classical manufacturing test verifies that a circuit is fault free during fabrication, however, cannot detect any fault that occurs after deployment or during operation. As complexity of integration rises, frequency of such failures is increasing for which on-line testing (OLT) is becoming an essential part in design for testability. In majority of the works on OLT, single stuck at fault model is considered. However in modern integration technology, single stuck at fault model can capture only a small fraction of real defects and as a remedy, advanced fault models such as bridging faults, transition faults, delay faults, etc. are now being considered. In this paper we concentrate on bridging faults for OLT. The reported works on OLT using bridging fault model have considered non-feedback faults only. The basic idea is, as feedback bridging faults may cause oscillations, detecting them on-line using logic testing is difficult. However, not all feedback bridging faults create oscillations and even if some does, there are test patterns for which the fault effect is manifested logically. In this paper it is shown that the number of such cases is not insignificant and discarding them impacts OLT in terms of fault coverage and detection latency. The present work aims at developing an OLT scheme for bridging faults including the feedback bridging faults also, that can be detected using logic test patterns. The proposed scheme is based on Binary Decision Diagrams, which enables it to handle fairly large circuits. Results on ISCAS 89 benchmarks illustrate that consideration of feedback bridging faults along with non-feedback ones improves fault coverage, however, increase in area overhead is marginal, compared to schemes only involving non-feedback faults.     

On the generation of test patterns for multiple faults

This article presents a new method to generate test patterns for multiple stuck-at faults in combinational circuits. We assume the presence of all multiple faults of all multiplicities and we do not resort to their explicit enumeration: the target fault is a single component of possibly several multiple faults. New line and gate models are introduced to handle multiple fault effect propagation through the circuits. The method tries to generate test conditions that propagate the effect of the target fault to primary outputs. When these conditions are fulfilled, the input vector is a test for the target fault and it is guaranteed that all multiple faults of all multiplicities containing the target fault as component are also detected. The method uses similar techniques to those in FAN and SOCRATES algorithms to guide the search part of the algorithm, and includes several new heuristics to enhance the performance and fault detection capability. Experiments performed on the ISCAS'85 benchmark circuits show that test sets for multiple faults can be generated with high fault coverage and a reasonable increase in cost over test generation for single stuck-at faults.     

IEEE Standard 1500 Compatible Oscillation Ring Test Methodology for Interconnect Delay and Crosstalk Detection

A novel oscillation ring (OR) test scheme and architecture for testing interconnects in SOC is proposed and demonstrated. In addition to stuck-at and open faults, this scheme can also detect delay faults and crosstalk glitches, which are otherwise very difficult to be tested under the traditional test schemes. IEEE Std. 1500 wrapper cells are modified to accommodate the test scheme. An efficient algorithm is proposed to construct ORs for SOC based on a graph model. Experimental results on MCNC benchmark circuits have been included to show the effectiveness of the algorithm. In all experiments, the scheme achieves 100% fault coverage with a small number of tests.     

Fault coverage requirement in production testing of LSI circuits

A technique is described for evaluating the effectiveness of production tests for large scale integrated (LSI) circuit chips. It is based on a model for the distribution of faults on a chip. The model requires two parameters, the average number (n/SUB 0/) of faults on a faulty chip and the yield (y) of good chips. It is assumed that the yield either is known or can be calculated from the available formulas. The other parameter, n/SUB 0/, is determined from an experimental procedure. Once the model is fully characterized, it allows calculation of the field reject rate as a function of the fault coverage. The technique implicitly takes into account such variables as fault simulator characteristics, the feature size, and the manufacturing environment. An actual LSI circuit is used as an example.     

Fault detection of plasma etchers using optical emission spectra

The objective of this paper is to investigate the suitability of using optical emission spectroscopy (OES) for the fault detection and classification of plasma etchers. The OES sensor system used in this study can collect spectra at up to 512 different wavelengths. Multiple scans of the spectra are taken from a wafer, and the spectra data are available for multiple wafers. As a result, the amount of the OES data is typically large. This poses a difficulty in extracting relevant information for fault detection and classification. In this paper, we propose the use of multiway principal component analysis (PCA) to analyze the sensitivity of the multiple scans within a wafer with respect to typical faults such as etch stop, which is a fault that occurs when the polymer deposition rate is larger than the etch rate. Several PCA-based schemes are tested for the purpose of fault detection and wavelength selection. A sphere criterion is proposed for wavelength selection and compared with an existing method in the literature. To construct the final monitoring model, the OES data of selected wavelengths are properly scaled to calculate fault detection indices. Reduction in the number of wavelengths implies reduced cost for implementing the fault detection system. All experiments are conducted on an Applied Materials 5300 oxide etcher at Advanced Micro Devices (AMD) in Austin, TX     

Design, analysis, and evaluation of concurrent checking sortingnetworks

In this brief, we propose two new concurrent error-detection (CED) schemes for a class of sorting networks, e.g., odd-even transposition, bitonic, and perfect shuffle sorting networks. A probabilistic method is developed to analyze the fault coverage, and the hardware overhead is evaluated. We first propose a CED scheme by which all errors caused by single faults in a concurrent checking sorting network can be detected. This scheme is the first one available to use significantly less hardware overhead than duplication without compromising throughput. From this scheme, we develop another fault detection scheme which sharply reduces the hardware overhead (using an additional 10%~30% hardware) but still achieves virtually 1001 fault coverage     

两种联邦滤波系统级故障检测方案对比与仿真

从联邦滤波的故障检测特点出发,以SINS/GPS/ADS/TACAN/RADAR组合导航系统为对象,对基于量测一致性和残差χ2检测的两级故障检测法、双状态递推故障检测法两种系统级故障检测方案进行了较为详细的分析比较,并通过预设故障模型进行了仿真.仿真结果表明:故障检测部分的加入可有效地提高多传感器组合导航系统的容错性和可靠性.两种检测方案对软、硬故障都有较高的灵敏度,但都不同程度出现误警和漏检情况,总体而言,基于量测一致性和残差χ2检测的检测方案更有优势.     

Design of self-testing and on-line fault detection combinational circuits with weakly independent outputs

In this article we propose a structure dependent method for the systematic design of combinational selftesting fault detection circuits that is well adapted to the arbitrarily chosen technical fault model. According to the fault model considered the outputs of the circuit are partitioned into different generally nondisjoint groups of weakly independent outputs. The parities of these groups of weakly independent outputs are compared in test mode as well as in normal operation mode with the corresponding predicted parities by use of a self-checking checker. For on-line detection, the hardware is in normal operation mode, and for testing, it is in test mode. In the test mode, these fault detection circuits guarantee a 100% fault coverage for single stuck-at-0/1 faults and a high fault coverage for arbitrary faults. In normal operation mode all technical faults considered will be detected possibly, with some degree of latency.Partially presented at the VLSI Test Symposium, Atlantic City, 1992.     

Multiple Stuck-at Fault Testability Analysis of ROBDD Based Combinational Circuit Design

Automatic test pattern generation (ATPG) is the next step after synthesis in the process of chip manufacturing. The ATPG may not be successful in generating tests for all multiple stuck-at faults since the number of fault combinations is large. Hence a need arises for highly testable designs which have 100% fault efficiency under the multiple stuck-at fault(MSAF) model. In this paper we investigate the testability of ROBDD based 2×1 mux implemented combinational circuit design. We show that the ROBDD based 2×1 mux implemented circuit is fully testable under multiple stuck-at fault model. Principles of pseudoexhaustive testing and multiple stuck-at fault testing of two level AND-OR gates are applied to one sub-circuit(2×1 mux). We show that the composite test vector set derived for all 2×1 muxes is capable of detecting multiple stuck-at faults of the circuit as a whole. Algorithms to derive test set for multiple stuck-at faults are demonstrated. The multiple stuck-at fault test set is larger than the single stuck-at fault test set. We show that the multiple stuck-at fault test set can be derived from the Disjoint Sum of Product expression which allows test pattern generation at design time, eliminating the need of an ATPG after the synthesis stage.