Degradation behavior of 600 V–200 A IGBT modules under power cycling and high temperature environment conditions

One challenge for automotive hybrid traction application is the use of high power IGBT modules that can withstand high ambient temperatures, from 90 °C to 120 °C, for reliability purpose. The paper presents ageing tests of 600 V–200 A IGBT modules subjected to power cycling with 60 °C junction temperature swings at 90 °C ambient temperature. Failure modes are described and obtained results on the module characteristics are detailed. Especially, physical degradations are described not only at the package level, like solder attach delaminations, but also at the chip level, with a shift on electrical characteristics such as threshold voltage. Finally, numerical investigations are performed in order to assess the thermal and thermo-mechanical constraints on silicon dies during power cycling and also to estimate the effect of ambient temperature on the mechanical stresses.     

Comparison of IGBT short-circuit failure “ohmic mode”: Epoxy molded package versus silicone gel module for new fail-safe and interruptible power converters

An epoxy molded package is compared with a silicone gel module with IGBTs chips in short-circuit failure modes with respect to critical energy, I²T_melting and explosion energy capabilities. Special importance was attached to “ohmic mode” assessment and ageing of the failed chips. The molded technology yields a very low and stable R_sc (<10 mΩ) as a “residual ohmic value” of the dies in low energy short-circuit failure, which is analysed through a complete reverse. Continuous thermal cycling tests over a medium time duration (>1000 h) also exhibit an acceptable drift of the R_sc property (<20%). The silicone gel module clearly exhibits an unstable R_sc value due to damage of the “free moving” wire-bonding on the chips. The authors show that the paralleled wires connections and the multiple parallel melting pits allow a sort of active redundancy and a possible on-state operation. All these results are used for the design of new and original failsafe converters. These topologies use only one paralleled safety leg that is spontaneously and directly connected in series with the failed devices, through the low R_sc value of the failed chips, without any additional complexity or extra cost.     

Characterisation and modelling of parasitic effects and failure mechanisms in AlGaN/GaN HEMTs

This work is a study of the degradations of AlGaN/GaN HEMTs induced by 2000 h of ageing tests. The methodology is based on cross-characterisation analysis.The life tests (HTO 150 °C, HTO 175 °C and HTRB 175 °C and Idq 90 °C) have mainly induced a decrease of the saturation drain current, occurring during the first 50 h, followed by a stabilisation. There is a shift of the pinch-off voltage in the range of 0.1–0.2 V while the Schottky contact is rather stable after ageing. The evolution of the electrical characteristics after ageing does not depend on the bias conditions but rather more on the channel temperature. It seems to be neither field nor current driven. Low frequency drain current noise demonstrates that there is no trap creation and the weak evolution of the 1/f noise confirms that there is no degradation in the channel. Moreover, pulsed I–V measurements show a weak evolution of gate lag and drain lag rates after ageing. The same degradation mode is demonstrated for all life tests with rather high activation energy of 1.6 eV. The weak evolution of electrical characteristics observed during the life tests cannot be obviously explained by a single physical mechanism and results from a combination of trap-related effects before stabilisation.     

Avalanche robustness of SiC Schottky diode

Reliability is one of the key issues for the application of Silicon carbide (SiC) diode in high power conversion systems. For instance, in high voltage direct current (HVDC) converters, the devices can be submitted to high voltage transients which yield to avalanche. This paper presents the experimental evaluation of SiC diodes submitted to avalanche, and shows that the energy dissipation in the device can increase quickly and will not be uniformly distributed across the surface of the device. It has been observed that failure occurs at a fairly low energy level (< 0.3 J/cm²), on the edge of the die, where the electrical field intensity is the greatest. The failure results in the collapse of the voltage across the diode (short-circuit failure mode). If a large current is maintained through the diode after its failure, then the damage site is enlarged, masking the initial failure spot, and eventually resulting in a destruction of the device and an open circuit.     

Changes of solar cell parameters during damp‐heat exposure

The electrical ageing of photovoltaic modules during extended damp‐heat tests at different stress levels is investigated for three types of crystalline silicon photovoltaic modules with different backsheets, encapsulants and cell types. Deploying different stress levels allows determination of an equivalent stress dose function, which is a first step towards a lifetime prediction of devices. The derived humidity dose is used to characterise the degradation of power as well as that of the solar cell's equivalent circuit parameters calculated from measured current–voltage characteristics. An application of this to the samples demonstrates different modes in the degradation and thus enables better understanding of the module's underlying ageing mechanisms. The analysis of changes in the solar cell equivalent circuit parameters identified the primary contributors to the power degradation and distinguished the potential ageing mechanism for each types of module investigated in this paper. © 2016 The Authors. Progress in Photovoltaics: Research and Applications published by John Wiley & Sons Ltd. © 2016 The Authors. Progress in Photovoltaics: Research and Applications published by John Wiley & Sons Ltd.     

Advanced electrical and stability characterization of untrimmed and variously trimmed thick-film and LTCC resistors

As-fired thick-film resistors have the resistance tolerance within ±20% and this tolerance is increased for smaller components. Therefore the novel trimming methods are necessary for microresistors, especially when they are embedded in LTCC substrate. This paper compares electrical (normalized temperature dependence of resistance, low frequency noise) and stability properties (relative resistance drift, changes of current noise index) of untrimmed, voltage pulse trimmed and laser trimmed unglazed thick-film resistors after step-increased long-term thermal ageing at 162 °C, 207 °C and 253 °C. Moreover the effect of long term exposure (1000 h, 125 °C) and thermal shocks (1000 shocks between −55 °C and 125 °C) is analysed for untrimmed and voltage pulse trimmed buried LTCC resistors.     

Low voltage stress induced leakage current and time to breakdown in ultra-thin (1.2–2.3 nm) oxides

Ultra-thin gate-oxide reliability is an essential factor in CMOS technologies. The low voltage gate current in ultra-thin oxide of metal–oxide–semiconductor devices is very sensitive to electrical stresses. It can be used as a reliability monitor when the oxide thickness becomes too small for traditional electrical measurements. In this paper, the low voltage stress induced leakage current (LVSILC) for various oxide thicknesses ranging from 1.2 to 2.3 nm is investigated during constant voltage stress (CVS). From the LVSILC measurements, we shown that time to breakdown can be deduced as a function of the stress voltage. We also study the effect of elevated stress temperature on the time to breakdown. We show that temperature dependence of the time to breakdown is non-Arrhenius and decreases in a drastic way with a slope of 0.036 decade/°C.     

A cascade energy band structure enhances the carrier energy in organic vertical-type triodes

Organic vertical-type triodes (OVTs) based on the cascade energy band structure as emitter layer are studied. The electric characteristics were dramatically enhanced while incorporating the cascade energy under current driving and voltage driving modes. The improvement is attributed to that injection carriers can obtain higher energy through a stepwise energy level. When the device has a layered structure of F₁₆CuPC (10 nm)/PTCDI (10 nm)/pentacene (100 nm) in emitter, it exhibits a common-base transport factor of 0.99 and a common-emitter current gain of 225 under current driving mode and exhibits a high current modulation-exceeding ?520 μA for a low collector voltage of ?5 V and a base voltage of ?5 V and the current on/off ratio of 10³ under voltage driving mode. Furthermore, we realized first organic current mirror that exhibited out/in current ratio of 0.75 and output resistance of 10⁵ Ω by using the OVTs.     

Optical and electrical characterization of thin films based on anthracene polyether polymers

Two new anthracene derivatives were characterized to improve the optoelectronic properties of π-conjugated anthracene polymers. The optical properties of the polymers were investigated by UV-visible absorption and photoluminescence (PL) spectroscopy. The energy bandgaps of anthracene-based polyether thin films were in the range 2.8–2.97 eV. Green emission (504 nm) was observed for anthracene/bisphenol A (An-BPA) and green-yellow emission (563 nm) for anthracene/fluorinated bisphenol A. (An-BPAF) Organic diodes formed by sandwiching anthracene layers between indium–tin oxide (ITO) and aluminum contacts were characterized. The dc electrical properties of ITO/anthracene derivatives/Al diodes were studied using current–voltage measurements and showed ohmic behavior at low voltage. The conduction mechanism seems to be a space-charge-limited current with exponential trap distribution at high applied bias voltage. The ac electrical transport of the anthracene derivatives was studied as a function of frequency (100 Hz–10 MHz) and applied bias in impedance spectroscopy analyses. We interpreted Cole–Cole plots in terms of the equivalent circuit model as a single parallel resistance and a capacitance network in series with a relatively small resistance. The evolution of the electrical parameters deduced from fitting of the experimental data is discussed. The conduction mechanism revealed by I–V characteristics is in agreement with the impedance spectroscopy results.     

Comparative studies of Pt and Ir schottky contacts on undoped Al0.36Ga0.64N

Schottky contacts of Pt and Ir on undoped Al_0.36Ga_0.64N have been fabricated and the ideality factor, the built-in voltage and the reverse bias current were determined using current–voltage measurements to make a comparison.The smallest ideality factors, the lowest reverse bias current and the highest built-in voltages have been obtained for Ir Schottky contacts.We have studied the effect of an annealing for Pt and Ir Schottky contacts, on the ideality factor, the built-in voltage and the reverse bias current. A decrease of the ideality factor and the reverse bias current associated to an increase of the built-in voltage have been obtained except for high annealing temperature (T > 400 °C).Reductions of 37% and 43% of the ideality factor and improvements of 24% and 41% of the built-in voltage have been obtained for Pt and Ir Schottky contacts, respectively, after an annealing performed at 350 °C during 30 min.Two different electrical stresses have also been applied on the ohmic and Schottky contacts during 164 h to study the reliability of the employed technology. In a first time, the devices have been stressed with a drain-to-source voltage V_DS of 20 V and a gate-to-source voltage V_GS of −5 V to submit the devices to an electrical field only and not to a thermal effect induced by the electrical current. In a second time, the aging stress has been applied for a V_DS of 20 V and for a V_GS of 0 V in order to study the impact of the electrical field and the thermal effect induced by the drain current on the electrical behaviours of Al_0.36Ga_0.64N/GaN transistors. This study has also shown the existence of electrical traps in the device structure and proved the good reliability of the involved technology.These comparative studies demonstrate that Ir is a better candidate than Pt for the realisation of Schottky contacts on undoped Al_0.36Ga_0.64N.     

On the short-circuit and avalanche ruggedness reliability assessment of SiC MOSFET modules

This paper provides an insight into the operational robustness of commercially available SiC MOSFET power modules, during short-circuit (SC) and unclamped inductive switching (UIS) test environments. A set of five different power modules from three vendors rated from 1.2–1.7 kV and with various current ratings have been evaluated, where the possible failure mechanisms that cause the breakdown of the modules have been addressed. The SC pulse duration of the modules was gradually increased until the failure occurred. A critical short circuit energy in the order of 4.0–8.0 J was observed at a supply voltage of 800 V and a pulse duration of 4.0 μs. At lower supply voltage of 500 V, all modules survived until 10.0 μs. One of the modules, rated at 1.7 kV, survived SC tests at voltages up to 1000 V for a pulse duration of 4 μs, but failed when the supply voltage was increased to 1100 V. Prior to failure, a gate-source voltage drop has been recorded, which is associated with a high G-S leakage current. The main failure mechanism, however, is the thermal runaway which leads the devices into avalanche breakdown mode. During the UIS tests, multiple samples from the three vendors of the power modules failed. The failure of the modules was always caused by the external diode connected in parallel with the MOSFETs. One of the modules from the same vendor which does not have external diode and another module from a different vendor with external diode survived the UIS tests under nominal test conditions.     

In-plane electrical bistability of photochromic diarylethene/Cu composite film

Electrical bistability is an essential property for memory devices. We report here the in-plane electrical bistability of photochromic diarylethene (DAE)/Cu composite film, which is prepared by Cu vapor deposition on the DAE surface with a low glass-transition temperature. The low-current level around 10⁻⁸ A was switched to a high-current level of ca. 10⁻⁴ A at a low threshold voltage (V_th) in the first voltage sweep. Once this switching occurred, the high-current level was kept in the second voltage sweep, and electrical bistability was achieved for the in-plane current. V_th was distributed in a wide range of voltages (0.5–10 V), and the colored sample obtained by the UV irradiation showed a relatively higher V_th than the colorless sample. The highest ON–OFF ratio in current was ca. 10⁶. The origin of the bistability attributed to the electrical breakdown in the insulated lines that was consisted of DAE in Cu film. The in-plane bistability of the DAE/Cu composite film has good retention time (>60 min) and readout-cycle endurance (>10⁶ cycles), indicating that it is suitable for write-once organic semiconductor memory characteristics.     

Improved Stability of Pd/Ti Contacts to <Emphasis Type="Italic">p</Emphasis>-Type SiC Under Continuous DC and Pulsed DC Current Stress

The enhanced stability of Pd/Ti contacts to p-type SiC under high-current-density continuous direct-current (DC) stressing is investigated and compared with previous work on Ti/Al contacts. Additionally, differing failure modes were observed for the Pd/Ti contacts under continuous DC and pulsed DC stress. The improved stability of the Pd/Ti contacts is demonstrated through a 29% increase in the applied continuous DC current required to cause electrical failure during a 1 h test compared with the Ti/Al contacts. The metallization scheme includes a TiW barrier and a thick electroplated Au overlayer. While severe intermixing and voiding in the ohmic contact layer caused the Pd/Ti contacts to fail under continuous DC stress, electromigration of the Au overlayer degraded the contacts under pulsed DC stress. The temperature of the surface of the contacts was reduced from over 649°C for contacts that failed under continuous DC current to between 316°C and 371°C for pulsed DC current. The difference in temperature and failure modes of the continuous and pulsed DC stressed contacts indicates different failure mechanisms.     

Study of the breakdown failure mechanisms for power AlGaN/GaN HEMTs implemented using a RF compatible process

The breakdown failure mechanisms for a family of power AlGaN/GaN HEMTs were studied. These devices were fabricated using a commercially available MMIC/RF technology with a semi-insulating SiC substrate. After a 10 min thermal annealing at 425 K, the transistors were subjected to temperature dependent electrical characteristics measurement. Breakdown degradation with a negative temperature coefficient of ?0.113 V/K for the devices without field plate was found. The breakdown voltage is also found to be a decreasing function of the gate length. Gate current increases simultaneously with the drain current during the drain-voltage stress test. This suggests that the probability of a direct leakage current path from gate to the 2-DEG region. The leakage current is attributed by a combination of native and generated traps/defects dominated gate tunneling, and hot electrons injected from the gate to channel. Devices with field plate show an improvement in breakdown voltage from ～40 V (with no field plate) to 138 V and with lower negative temperature coefficient. A temperature coefficient of ?0.065 V/K was observed for devices with a field plate length of 1.6 μm.     

Fast power cycling protocols implemented in an automated test bench dedicated to IGBT module ageing

This paper presents fast test protocols for ageing IGBT modules in power cycling conditions, and a monitoring device that tracks the on-state voltage V_CE and junction temperature T_J of IGBTs during ageing test operations. This device is implemented in an ageing test bench described in previous papers, but which has since been modified to perform fast power cycling tests.The fast test protocols described here use the thermal variations imposed on IGBT modules by a test bench operating under Pulse Width Modulation conditions. This test bench reaches the maximal values of power cycling frequencies attainable with a given module packaging in order to optimize test duration.The measurement device monitors V_CE throughout the ageing test that is needed to detect possible degradations of wire bonds and/or emitter metallization. This requires identifying small V_CE variations (a few dozen mV). In addition, the thermal swing amplitude of power cycling must be adjusted to achieve a given ageing protocol. This requires measuring junction temperature evolution on a power cycle, which is carried out by means of V_CE measurement at a low current level (100 mA).Experimental results demonstrate the flexibility of this test bench with respect to various power cycling conditions, as well as the feasibility of the proposed on-line monitoring methods.     

Influence of inhomogeneous contact in electrical properties of 4H–SiC based Schottky diode

Schottky diodes realized on 4H–SiC n-type wafers with an epitaxial layer and a metal-oxide overlap for electric field termination were studied. The oxide was grown by plasma enhanced chemical vapor deposition (PECVD) and the Schottky barriers were formed by thermal evaporation of titanium or nickel. Diodes, with voltage breakdown as high as 700 V and ideality factor as low as 1.05, were obtained and characterized after packaging in standard commercial package (TO220).The electrical properties such as ideality factor, hight barrier, the series resistance R_s were deduced by current/voltage (I–V) analysis using the least mean square (LMS) method. The temperature effect on break voltage, R_s and saturation current was studied. A model based on two parallel Schottky diodes with two barrier heights is presented for some devices having an inhomogeneous contact. It is shown that the excess current at low voltage can be explained by a lowering of the Schottky barrier in localized regions. We use the two series RC components electrical model in order to study the dynamic behaviour of the Schottky diode in low frequency and to improve the effect of barrier inhomogeneities in electrical properties.     

Effects of silicone coating degradation on GaN MQW LEDs performances using physical and chemical analyses

This work presents a physics of failure (POF) methodology coupling failure signatures with physico-chemical analyses. The aim is to work out electro-optical failure signatures located in packaged InGaN/GaN Multiple Quantum Wells Light Emitting Diodes (MQW LEDs). Electrical and optical characteristics performed after accelerated ageing tests (30 mA/85 °C/1500 h), confirm a 65% drop of optical power and an increase of one decade of leakage current spreading at the silicone oil/chip interfaces. Through measurements of silicone coating fluorescence emission spectra, we demonstrate that the polymer enlarges the LED emission spectrum and shifts central wavelength. This shift is related to silicone oil spectral instability and the central wavelength of packaged LED appears to be temperature insensitive. In this paper, we discriminate the degradation of bulk silicone oil responsible for optical losses from the polymer/chip interface inducing larger leakage current.     

Electrical characterization of solid-state heterojunctions between PEDOT:PSS and an anionic polyelectrolyte

Stable organic heterojunctions are developed by deposition of the anionic polyelectrolyte poly(4-lithium styrenesulfonic acid) (LiPSSA) on the top of poly(3,4-ethylendioxythiophene)/poly(styrenesulfonate) (PEDOT:PSS) films. The electrical response of the heterojunctions to triangular voltage pulses in the range between −5 and +5 V is characterized by hysteresis phenomena, observed for hundreds of cycles with low distortions, at scan rates between 1 and 100 mV/s. The hysteresis is ascribed to the occurrence of redox transitions, evidenced by the presence of well-defined peaks in the current–voltage characteristics. The electrical behaviour of the PEDOT:PSS/LiPSSA devices is found to be mainly capacitive, and show humidity-sensitive functionality, demonstrated by the gradual and reversible increase of the area subtended by the J−V cycles as the relative humidity increases.