倒装芯片下填充工艺的新进展（一）

为了增加在有机基板上倒装芯片安装的可靠性,在芯片安装后,通常都要进行下填充。下填充的目的是为了重新分配由于硅芯片和有机衬底间热膨胀系数失配产生的热应力。然而,仅仅依靠填充树脂毛细管流动的传统下填充工艺存在一些缺点。为了克服这些缺点,人们研究出了一些新的材料和开发出了一些新的工艺。     

基于表面能理论的倒装芯片封装下填充流动研究

为了预测倒装芯片封装中的下填充过程,通常要首先通过繁复的方法来求解平均毛细压.为了避免此问题,从能量的角度分析了倒装芯片封装工艺中的下填充流动过程.认为下填充是较低表面能的界面代替较高表面能的界面的过程,所释放的表面能用于形成流体流动的动能和克服阻力的能量损耗,期间能量守恒.在此分析的基础上建立了下填充流动的新模型.建立了可视化的下填充流动实验装置,并用下填充实验验证了所建立新模型的准确性.该模型避免了计算平均毛细压的复杂过程,并可方便地扩展到焊球排布形式不同的倒装芯片.     

国外工艺文献导读

责任编辑吕淑珍 20000301 提高倒装片工艺的成品率和可靠性一 Brian J Lewis.SMT,1999,13(11):64～68(英文) 尽管有一些成熟的工艺适用于PCB上的裸芯 片贴装,但倒装片技术是最独特的,芯片被直接倒装 在基板上.倒装片工艺的最关键问题之一是由于热 膨胀系数不同而引起的芯片与基板之间的应力,为 了消除这一应力,下填充工艺被应用于基板与芯片 之间.为了提高倒装片组装的成品率和可靠性,本 文研究了一些相关参数,并介绍了在工艺中怎样检 验每一参数的作用以及必须进行的调整. 20000302 免洗焊膏的改进-Smith Brian.SMT,     

倒装芯片放置工艺的设计分析

对倒装芯片不流动底部填充胶进行压迫流动填充,底部填料会对倒装芯片产生流体静态压力,阻碍芯片向下放置。根据牛顿流体挤压流动的静态近似分析估算出底部填料对芯片的作用力,分别计算在两种不同工艺条件下放置压力达到最大时,两种不同规格芯片与基板的间隔距离,比较与芯片凸点高度,然后计算使芯片凸点与基板键合区实现接触所需放置压力的最小保持时间,从正反两个方面讨论关键参数等对倒装芯片工艺设计影响。     

焊球正六边形排布倒装芯片的下填充毛细压研究

除了正四边形,正六边形也是倒装芯片中可行的焊球排布形式,为了预测封装倒装芯片时的下填充过程,需要精确计算毛细驱动压.在已有的焊球正四边形排布情况下平均毛细压计算方法的基础上,进一步研究了焊球正六边形排布情况下平均毛细压计算模型.通过分阶段处理,并根据质量守恒和力平衡的原则,分析了下填充过程,重点分析了填充面积和接触线跳跃量的计算,进而得到了计算平均毛细压的数学模型.通过实例验证了该模型的准确性,从而完善了倒装芯片封装工艺中的下填充流动解析模型.     

倒装芯片封装中下填充流场渗透率的数值分析

倒装芯片封装中的下填充流场可以假设为多孔介质流场,其渗透率的求解对研究下填充流动过程至关重要。根据下填充流场所具有的周期性结构,通过单胞数值模拟的方法得到了下填充流场的渗透率。通过对渗透率数据的分析,发现了渗透率和下填充流场参数之间的关系,并建立了计算渗透率的幂律模型。其中幂律模型的底是下填充流场的孔隙率,系数仅与芯片和基板的间隙有关,指数仅与芯片和基板的间隙相对于焊球直径的比值有关。通过实例分析表明,与其他模型相比,用基于幂律模型的渗透率所计算出的填充时间更符合实验结果。     

倒装片可修复底部填充材料的研究现状及发展

有机基板上的倒装芯片一般采用底部填充技术以提高其封装的可靠性.有缺陷的芯片在倒装后难以进行返工替换,使得倒装芯片技术成本提高,限制了此技术的应用.提出新型可修复底部填充材料的开发成为解决这一问题的有效途径.介绍了倒装芯片的可修复底部填充技术和可应用于可修复底部填充材料的技术要求,并综述了国内外对于可修复底部填充材料的研究现状.     

IBM芯片技术取得突破可使电流速度提高10倍

IBM公司的研究人员日前宣布,他们在芯片制造领域取得重大技术突破,可以大幅降低芯片的生产成本。传统芯片都是在坚硬的硅片上制作的,生产成本和所需的化学制造工艺都非常昂贵,因为要在一小片芯片上安装尽可能多的晶体管。一些公司已经相继采用新的制造技术,可以将薄薄的半导片体贴在软质塑料等较大的材料表面,这些表面可以象报纸排版一样安排所需线路,此类芯片可以用在计算机显示器和太阳能电池等产品之中。当前遇到的最大难题是薄芯片线路中的电流过缓,影响一些程序的应用效率。但是IBM下属的T.J. Watson研究中心报告称,他们已经开发出…     

关于底部填充在倒装芯片应用中空洞缺陷的影响因素

底部填充包封材料起初应用于提高早期氧化铝（Al2O3）基材的倒装芯片的可靠性。在芯片最外围的焊点易疲劳而导致芯片功能失效．相对较小的硅片和基材间的热膨胀差异是芯片在经受热循环时产生这种问题的根源．这样，热循环的温度范围及循环的次数就决定了芯片的使用寿命．在芯片和基板间填充可固化的包封材料，可以很好地把热膨胀差异带来的集中于焊点周围的应力分散到整个芯片所覆盖的范围。 随着引入环氧材料作为倒装芯片的基材，底部填充材料的研发大大地加快了。为了延缓焊点的应力疲劳，较大的基材和芯片硅片材料间的热膨胀差异使得底部填充剂的应用成为必然．而在底部填充材料和芯片接合界面的分层及底部填充剂中的空洞是触发许多芯片产生问题的根本原因之一。本篇将要讨论的是减少底部填充剂中的空洞的一些方法．[编者按]     

薄膜基板中填充孔工艺的研究

在微波混合电路和多芯片模块中,填充孔相比于传统电镀通孔在解决微波接地、芯片散热和微组装工艺问题等方面具有很大优势.利用填充孔工艺使微波电路的设计更加灵活;由于填充孔消除了组装时通孔溢出导电胶或焊料过多的现象,提高了组装工艺效率.对薄膜基板上填充孔的制作工艺进行了深入研究,并对其电参数、散热性能和可靠性进行了测试和评估.最后,将采用填充孔工艺的薄膜基板应用于限幅低噪放和锁相源产品中,测试结果表明产品性能和散热效果均有明显提高.     

Recent advances in flip-chip underfill: materials, process, and reliability

In order to enhance the reliability of a flip-chip on organic board package, underfill is usually used to redistribute the thermomechanical stress created by the coefficient of thermal expansion (CTE) mismatch between the silicon chip and organic substrate. However, the conventional underfill relies on the capillary flow of the underfill resin and has many disadvantages. In order to overcome these disadvantages, many variations have been invented to improve the flip-chip underfill process. This paper reviews the recent advances in the material design, process development, and reliability issues of flip-chip underfill, especially in no-flow underfill, molded underfill, and wafer-level underfill. The relationship between the materials, process, and reliability in these packages is discussed.     

Parametric reliability analysis of no-underfill flip chip package

This research proposes a parametric analysis for a flip chip package with a constraint-layer structure. Previous research has shown that flip-chip type packages with organic substrates require underfill for achieving adequate reliability life. Although underfill encapsulant is needed to improve the reliability of flip chip solder joint interconnects, it will also increase the difficulty of reworkability, increase the packaging cost and decrease the manufacturing throughput. This research is based on the fact that if the thermal mismatch between the silicon die and the organic substrate could be minimized, then the reliability of the solder joint could be accordingly enhanced. This research proposes a structure using a ceramic-like material with CTE close to silicon, mounted on the backside of the substrate to constrain the thermal expansion of the organic substrate. The ceramic-like material could reduce the thermal mismatch between silicon die and substrate, thereby enhancing the reliability life of the solder joint. Furthermore, in order to achieve better reliability design of this flip chip package, a parametric analysis using finite element analysis is performed for package design. The design parameters of the flip chip package include die size, substrate size/material, and constraint-layer size/material, etc. The results show that this constraint-layer structure could make the solder joints of the package achieve the same range of reliability as the conventional underfill material. More importantly, the flip chip package without underfill material could easily solve the reworkability problem, enhance the thermal dissipation capability and also improve the manufacturing throughput     

The effects of underfill on the reliability of flip chip solder joints

Thermal fatigue damage of flip chip solder joints is a serious reliability concern, although it usually remains tolerable with the flip chip connections (of smaller chips) to ceramic boards as practiced by IBM for over a quarter century. However, the recent trend in microelectronics packaging towards bonding large chips or ceramic modules to organic boards means a larger differential thermal expansion mismatch between the board and the chip or ceramic module. To reduce the thermal stresses and strains at solder joints, a polymer underfill is customarily added to fill the cavity between the chip or module and the organic board. This procedure has typically at least resulted in an increase of the thermal fatigue life by a factor of 10, as compared to the non-underfilled case. In this contribution, we first discuss the effects of the underfill to reduce solder joint stresses and strains, as well as underfill effects on fatigue crack propagation based on a finite element analysis. Secondly, we probe the question of the importance of the effects of underfill defects, particularly that of its delamination from the chip side, on the effectiveness of the underfill to increase thermal fatigue life. Finally, we review recent experimental evidence from thermal cycling of actual flip chip modules which appears to support the predictions of our model.     

Adhesion issues in flip-chip on organic modules

Flip chip attach on organic carriers is a novel electronic packaging assembly method which provides advantages of high input/output (I/O) counts, electrical performance and thermal dissipation. In this structure, the flip chip device is attached to organic laminate with predeposited eutectic solder. Mechanical coupling of the chip and the laminate is done via underfill encapsulant materials. As the chip size increases, the thermal mismatch between silicon and its organic carrier becomes greater. Adhesion becomes an important factor since the C4 joints fail quickly if delamination of the underfill from either chip or the solder mask interface occurs. Newly developed underfills have been studied to examine their properties, including interfacial adhesion strength, flow characteristics, void formation and cure kinetics. This paper will describe basic investigations into the properties of these underfills and also how these properties related to the overall development process. In addition, experiments were performed to determine the effects on adhesion degradation of flip chip assembly processes and materials such as IR reflow profile, flux quantity and residues. Surface treatment of both the chip and the laminate prior to encapsulation were studied to enhance underfill adhesion. Accelerated thermal cycling and highly accelerated stress testing (HAST) were conducted to compare various underfill properties and reliability responses     

Yield analysis and process modeling of low cost, high throughputflip chip assembly based on no-flow underfill materials

As a concept to achieve low-cost, high-throughput flip chip on board (FCOB) assembly, a new process has been developed implementing next generation flip chip processing based no-flow fluxing underfill materials. The low-cost, high throughput flip chip process implements large area underfill printing, integrated chip placement and underfill flow and simultaneous solder interconnect reflow and underfill cure. The goals of this study are to demonstrate feasibility of no flow underfill materials and the high throughput flip chip process over a range of flip chip configurations, identify the critical process variables affecting yield, analyze the yield of the high throughput flip chip process, and determine the impact of no-flow underfill materials on key process elements. Reported in this work is the assembly of a series of test vehicles to assess process yield and process defects. The test vehicles are assembled by depositing a controlled mass of underfill material on the chip site, aligning chip to the substrate pads, and placing the chip inducing a compression type underfill flow. The assemblies are reflowed in a commercial reflow furnace in an air atmosphere to simultaneously form the solder interconnects and cure the underfill. A series of designed experiments identify the critical process variables including underfill mass, reflow profile, placement velocity, placement force, and underfill material system. Of particular interest is the fact that the no-flow underfill materials studied exhibit an affinity for unique reflow profiles to minimize process defects     

倒装焊后清洗工艺及其对底部填充的影响

倒装焊封装是通过将整个芯片有源面进行管脚阵列排布并预制焊料凸点,通过倒装焊工艺进行互连,与传统引线键合技术相比具有更高的组装密度及信号传输速率,是实现电子产品小型化、轻量化、多功能化的关键技术之一.对于小尺寸微节距的倒装焊芯片来说,焊后清洗的难度相对更大,因此清洗技术也是影响倒装焊工艺的重要因素.针对不同清洗方式及参数...     

Do chip size limits exist for DCA?

Solder joints, the most widely used flip chip on board (FCOB) interconnects, have a relatively low structural compliance due to the large thermal expansion mismatch between silicon die and the organic substrate. The coefficient of thermal expansion (CTE) of the printed wiring board (PWB) is almost an order of magnitude greater than that of the integrated circuit (IC). Under operating and testing conditions, this mismatch subjects the solder joints to large creep strains and leads to early failure of the solder connections. The reliability of such flip chip structures can be enhanced by applying an epoxy-based underfill between the chip and the substrate, encapsulating the solder joints. This material, once cured, mechanically couples the IC and substrate together to locally constrain the CTE mismatch. However, the effects of CTE mismatch are assumed to become more severe with increasing chip size. Even with the addition of an underfill material, it has been supposed that there are limits on the chip size used in flip chip applications     

Solder wetting in a wafer-level flip chip assembly

Wafer-level flip chips provide an innovative solution in establishing flip chip as a standard surface mount process. In this paper, the wetting of solder bumps within confining underfill during the reflow of a wafer-level flip chip assembly is addressed. For real time monitoring of an assembly during the reflow process, a system using a high-speed camera is utilized. The collapse of solder bumps on the chip in the vertical direction is found to be a prerequisite of solder wetting. Underfill voids and outgassing are found to cause chip drift and tilt during the reflow process. In addition, symmetry of the underfill flow and fillet formation is identified as a critical factor in maintaining chip to substrate alignment. During solder wetting of the metallization pads on the substrate, the underfill needs to maintain a low viscosity. With the selection of a thermally stable underfill and corresponding process development, wafer-level flip chip assemblies with good solder interconnects are demonstrated     

倒装芯片底部填充工艺

从热疲劳故障的角度论述了倒装芯片底部填充的必要性，介绍了倒装芯片底部填充的参数控制。通过正确的底部填充，可提高倒装芯片组装的成品率和可靠性。