A study on the characteristics of a wafer-polishing process according to machining conditions

The polishing process for silicon wafers plays a key role in the fabrication of semiconductors, since a globally planar, mirrorlike wafer surface is achieved in the process. The surface roughness of the wafer depends on the surface properties of the carrier head unit, together with other machining conditions, such as working speed, type of polishing pad, temperature, and down force. In this paper, the results of several experiments are used to study silicon wafer surfaces. The experiments were designed to observe the down force and temperature when a wafer carrier head unit with wafer was pressed down onto a polishing pad. A load cell was employed to detect the applied pressure against the polishing pad, and the working temperature was measured with an infrared sensor. Wafer surface roughness was investigated according to several parameters and experimental data.     

A study on the characteristic of parameters by the response surface method in final wafer polishing

As the level of Si-wafer surface directly affects device line-width capability, process latitude, yield, and throughput in fabrication of microchips, it needs to have ultra precision surface and flatness. Polishing is one of the important processing having influence on the surface roughness in manufacturing of Si-wafers. The surface roughness in final wafer polishing is mainly affected by the many process parameters. For decreasing the surface, the control of polishing parameters is very important. In this paper, the optimum condition selection of ultra precision wafer polishing and the effect of polishing parameters on the surface roughness were evaluated by using central composite designs such as the Box-Behnken method. Moreover, in accordance with variation of process variables, there is a temperature change on pad surface. And so, this paper also researches that this temperature variation affects surface roughness of Si-wafer.     

硅片边缘化学机械抛光的微小去除量测量

针对硅片化学机械抛光工艺的材料去除量非常微小并难以测量的问题,本文介绍一种采用表面粗糙度测量仪,对硅片边缘化学机械抛光的材料去除量进行一种简易、快速的测量方法,且该方法同时还可准确地测量硅片边缘抛光表面粗糙度值。检测结果表明,本方法较好地解决了硅片边缘化学机械抛光表面检测问题。     

A state-of-the-art review of ductile cutting of silicon wafers for semiconductor and microelectronics industries

Silicon is a typical functional material for semiconductor and optical industry. Many hi-tech products like lenses in thermal imaging, solar cells, and some key products of semiconductor industry are made of single crystal silicon. Silicon wafers are used as substrate to build vast majority of semiconductor and microelectronic devices. To meet high surge in demand for microelectronics based products in recent years, the development of rapid and cost efficient processes is inevitable to produce silicon wafers with high-quality surface finish. The current industry uses a sequence of processes such as slicing, edge grinding, finishing, lapping, polishing, back thinning, and dicing. Most of these processes use grinding grains or abrasives for material removal. The mechanism of material removal in these processes is fracture based which imparts subsurface damage when abrasive particles penetrate into the substrate surface. Most of these traditional processes are extremely slow and inefficient for machining wafers in bulk quantity. Moreover, the depth of subsurface damage caused by these processes can be up to few microns and it is too costly and time consuming to remove this damage by heavy chemical–mechanical polishing process. Therefore, semiconductor industry requires some alternative process that is rapid and cost effective for machining silicon wafers. Ductile cutting of silicon wafer has the potential to replace the tradition wafer machining processes efficiently. If implemented effectively in industry, ductile cutting of silicon wafers should reduce the time and cost of wafer machining and consequently improve the productivity of the process. This paper reviews and discusses machining characteristics associated with ductile cutting of silicon wafers. The limitations of traditional wafer fabrication, the driving factors for switching to ductile cutting technology, basic mechanism of ductile cutting, cutting mechanics, cutting forces, surface topography, thermal aspects, and important factors affecting these machining characteristics have been discussed to give a systematic insight into the technology.     

硅晶片抛光加工工艺的实验研究

双面抛光已成为硅晶片的主要后续加方法,但由于需要严格的加工条件,很难获得理想的超光滑表面.设计了硅片双面抛光加工工艺新路线,并在新研制的双面抛光机上对硅晶片进行抛光加工,实验研究了不同加工参数对桂晶片表面粗糙度和材料去除率的影响.采用扫描探针显微镜和激光数字波面干涉仪分别对加工后的硅晶片进行测量,实验结果表明:在优化实验条件下硅晶片可以获得表面粗糙度0.533nm的超光滑表面.     

超声椭圆振动-化学机械复合抛光工具及实验研究

针对硅片的传统化学机械抛光,特别是随着硅片直径不断增大,硅片抛光表面质量和抛光效率成为一个亟待解决的问题。介绍一种超声椭圆振动-化学机械复合抛光新技术,并对抛光机理,抛光工具设计,性能及检测进行了详细论述和说明。在上述研究工作基础上,建立了超声椭圆振动辅助抛光实验系统,并进行了实验研究。实验结果显示,在抛光加工中引入超声椭圆运动后,工件抛光表面粗糙度值由传统抛光法的Ra0.077μm降低到Ra0.032μm,材料去除率最多可提高24%,且工件表面形貌有明显改善。     

Viscoelastic behavior of polishing pad: Effects on edge roll-off during silicon wafer polishing

In semiconductor device fabrication, surface flatness of silicon wafers has a significant impact on the chip yield. Hence, there is a strong demand to prevent the deterioration in surface flatness near the wafer edge due to edge roll-off during polishing. In the present study, we investigate the viscoelastic behavior of polishing pads and its effects on the uniformity of material removal distribution near the wafer edge. On the basis of the findings, we propose polishing conditions required to improve surface flatness near the wafer edge. The double-sided polishing experiments performed using silicon wafers reveal that the proposed polishing conditions effectively reduce edge roll-off.     

高浓度硼扩散硅片CMP工艺研究

"叉指式微加速度计"的研制,需要使用高浓度硼扩散硅片,而硅片经过高浓度硼扩散后,硅片双面生长了一层硼硅玻璃,很难将其去除,不能在高浓度硼扩散层上制作更好的"叉指式微加速度计"结构.针对上述问题,在CMP研磨抛光工艺中,针对上述问题,在CMP研磨抛光工艺中,选择合适的研磨料和抛光料以及研磨盘和抛光盘,通过对浆料浓度、流量大小、抛光温度进行改进,优化研磨抛光工艺流程及工艺参数,以完成高浓度硼扩散硅片的表面平坦化.     

Study on the effect of various machining speeds on the wafer polishing process

Silicon wafer polishing has an important role in semiconductor manufacturing; the general purpose of the polishing process is to produce a mirror-like surface. The wafer surface roughness is affected by many variables such as the carrier head unit characteristics, operation, platen and chuck speeds, pad and slurry ratios, and temperature. The optimum process conditions for the experimental temperature, down-force, slurry ratio, and processing time were determined in previous studies and used as fixed factors in this experiment. The main purpose of the present study was to determine how the different platen and chuck machining speeds influence the wafer surface roughness via the polishing process to obtain the optimum machining speed. In the results, the machining temperature appeared to differ at different machining speeds, which is a vital element with regard to wafer polishing.     

化学机械抛光过程中护环对硅片表面接触压强分布和宏观轮廓的影响

为了获得单晶硅片化学机械抛光过程中护环对接触压强分布的影响规律,根据有护环化学机械抛光实际出发,建立了抛光过程的接触力学模型和边界条件,利用有限元的方法对有护环抛光接触状态接触压强分布进行了计算和分析,并利用抛光实验对计算获得结果进行了验证;获得了硅片与抛光垫间的接触表面压强分布形态,以及护环几何参数对压强分布的影响规律;结果表明护环抛光接触压强的分布也存在不均匀性,而且在硅片外径邻域内接触压强最大,这些也能导致被加工硅片产生平面度误差和塌边,选择合理地护环几何参量和负载比,可以改善接触压强场分布的均匀性。     

Pad surface and coefficient of friction correlation analysis during friction between felt pad and single-crystal silicon

In wafer polishing pad surface plays a crucial role in the polishing process. With the increase of friction time between pad and wafer, the pad becomes flattened or glazed with particles clogging the pores of the pad and forming a layer of slurry residue and wafer particles, leading to changes of COF, material removal rates and higher defects on the wafer surface. Thus, this study aims to determine the correlation between pad surface deformation, slurry adhesive rate and Coefficient of friction (COF) during friction between felt pad and single -crystal silicon, to analyze the relationship between pad condition and COF. The real-time COF between felt pad and single-crystal silicon wafer are tested which are sorted in groups depending on various loads and oscillation frequencies and surfaces of felt pads measuring by Scanning electron microscope (SEM) are compared. The correlation between pad surface deformation and abrasive adhesion and COF is evaluated through analyzing the experiment results.

     

碳纤维增强热塑性复合材料超声波焊接研究进展

碳纤维增强热塑性复合材料（Carbon fiber reinforced thermoplastic composite,CFRTP）由于其优越的力学性能、较低的加工成本及可回收性,逐渐成为继铝合金、高强钢之后的新一代轻量化材料。国内外科研机构和材料企业都投入巨资和人力竞相开展相关研究,部分高校、企业已开始探索将CFRTP应用于机身与车身的制造与装配。超声波焊接是最适合焊接热塑性材料的方法之一,也是实现大规模装配CFRTP零部件的关键使能技术之一。从CFRTP超声波焊接基本过程、接头形式、数值模拟、质量监控和异种材料连接五个方面进行分析,系统讨论CFRTP超声波焊接最新研究成果,展望CFRTP超声波焊接中有待解决的共性问题,以期为CFRTP零部件的大规模装配应用提供参考。     

A novel polishing method for single-crystal silicon using the cavitation rotary abrasive flow

Traditional low-pressure abrasive flow polishing can produce highly smooth surfaces, but the efficiency of this method is too low for polishing of hard-brittle materials parts. This paper proposes a novel cavitation rotary abrasive flow polishing (CRAFP) method. The energy generated from the cavitation bubble collapse is used to increase the kinetic energy of the abrasive particles in the low-pressure abrasive flow and the motion randomness of the abrasive particles near the wall; thereby, the efficiency and quality of low-pressure abrasive flow polishing are improved. The CRAFP mechanism was first introduced, and then the characteristics of the CRAFP process were investigated using computational fluid dynamics (CFD)-based abrasive flow simulation. Subsequently, a single-crystal silicon wafer polishing test was carried outperformed to verify the validity of the CRAFP method. The polishing results were compared with those of the traditional low-pressure abrasive flow polishing method. After 8 h of polishing using the CRAFP method and the traditional low-pressure abrasive flow polishing method, the surface roughness of the workpiece decreased to7.87 nm and 10.53 nm, respectively. Furthermore, by starting at similar initial roughness values, the polishing time required to reduce the roughness to 12 nm was 3.5 h and 6 h, respectively. The experimental results demonstrated that CRAFP can satisfy the surface requirements of single-crystal silicon (R_a < 12 nm) and exhibit high polishing efficiency and good quality.     

Innovative chemical mechanical polish design and experiments

An innovative design for intelligent chemical mechanical polishing (CMP) control system is proposed and verified by experiments. Online measurement and real-time feedback are integrated to eliminate the shortcomings of traditional approaches, e.g., the batch-to-batch discrepancy of required polishing time, over consumption of chemical slurry, and non-uniformity across the wafer. The major advantage of the proposed method is that the finish of local surface roughness can be consistent, no matter where the inner-ring region or outer-ring region is concerned. Secondly, it is able to eliminate the edge effect: the interfacial-induced stress near the wafer edge is generally much higher than that near the wafer center. At last, by using the proposed intelligent chemical mechanical polishing strategy, the quality of the finished goods certainly upgraded.     

Effect of wafer size on material removal rate and its distribution in chemical mechanical polishing of silicon dioxide film

Chemical mechanical polishing (CMP) is a semiconductor fabrication process. In this process, wafer surfaces are smoothed and planarized using a hybrid removal mechanism, which consists of a chemical reaction and mechanical removal. In this study, the effects of wafer size on the material removal rate (MRR) and its uniformity in the CMP process were investigated using experiments and a mathematical model proposed in our previous research; this model was used to understand the MRR and its uniformity with respect to wafer size. Under constant process conditions, the MRR of a silicon dioxide (SiO₂) film increased slightly along with an increase in wafer size. The increase in MRR may be attributed to the acceleration of the chemical reaction due to a rise in process temperature. Based on the results obtained, the k and α values in the mathematical model are useful parameters for understanding the effect of wafer size on the MRR and its distribution under a uniform, relative velocity. These parameters can facilitate the prediction of CMP results and the effective design of a CMP machine.     

用表面粗糙度测量仪测量材料微小去除量

抛光加工工艺的材料去除量非常微小,因此难以对该材料去除量进行精确测量。本文采用常用表面粗糙度测量仪对反映硅片抛光材料去除量的抛光深度进行了简易、快速和实用的测量,较好地解决了微小去除量的测量问题,并通过实例证明该方法可行。     

Design and development of PCD micro straight edge end mills for micro/nano machining of hard and brittle materials

One of the biggest challenges for mechanical micro/nano milling is the design and fabrication of high precision and high efficiency micro milling tools. Commercially available micro milling tools are either too expensive (around several hundred US dollars) or simply made from downsizing of macro milling tools, which is sometimes not appropriate for the specific micro/nano milling requirements. So the design and fabrication of custom micro milling tools are necessary. In this paper, a micro straight edge endmill (SEE) is designed. Static and dynamic FEM analyses have been done for the SEEs with different rake angles trying to identify their stiffness and natural frequencies. By wire electrical discharge machining (WEDM), the SEEs made of polycrystalline diamond (PCD) with three different rake angles have been fabricated. The evaluation milling on tungsten carbide (WC) and silicon wafer have processed on a nano milling center. Experimental results show the SEEs have a good ability to simultaneously micro/nano milling of both the side and bottom surfaces with submicron surface roughness, and the SEE has high accuracy for large aspect ratio thin wall machining. The milling experiments on silicon wafer have successfully demonstrated that ductile mode machining was achieved and the coolant played an important role in silicon wafer milling.     

Efficient automatic polishing process with a new compliant abrasive tool

In this paper, an efficient polishing process is proposed for precision polishing tasks using a new compliant abrasive tool. The polishing process is conducted by a force-controllable five-axes robot. The polishing process comprises many steps using different abrasive grain sizes. For each process step, an optimal set of polishing parameters that can efficiently reduce surface roughness is determined by the Taguchi method. The relation between the surface roughness and the polishing efficiency for each set of optimal parameters can be fitted as an R–E curve. The efficiency of a polishing step decreases with the number of polishing cycles and the surface roughness reduces to an asymptote value. The automatic polishing scheduling is fulfilled by switching to a more efficient choice among these R–E curves until the desired surface roughness is reached.     

典型碳化硅光学材料的超光滑抛光试验研究

研究了三种典型的碳化硅光学材料CVD SiC、HP SiC以及RB SiC的材料去除机理与可抛光性,并对其进行了超光滑抛光试验。在分析各种材料制备方法与材料特性的基础上,通过选择合理的抛光工艺参数,均获得了表面粗糙度优于Rq=2nm（采样面积为0.71mm×0.53mm）的超光滑表面。试验结果表明：研磨过程中,三种碳化硅光学材料均以脆性断裂的方式去除材料,加工表面存在着裂纹以及材料脱落留下的缺陷;抛光过程中,CVD SiC主要以塑性划痕的方式去除材料,决定表面粗糙度的主要因素为表面微观划痕的深度;HP SiC同时以塑性划痕与晶粒脱落的形式去除材料,决定表面粗糙度的主要因素为碳化硅颗粒大小以及颗粒之间微孔的尺寸;RB SiC为多组分材料,决定其表面粗糙度的主要因素为RB SiC三种组分之间的去除率差异导致的高差。
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Polishing pad for reducing edge roll-off while maintaining good global flatness of silicon wafer

In the double-sided polishing process of silicon wafers, there is a strong demand to reduce amount of edge roll-off (ERO) while improving global flatness of a wafer. In the present study, we clarified the negative effects of uneven wear of the polishing pads on the global flatness of a wafer can be suppressed when the deformation of the polishing pads is large. As for the ERO, we found small deformation of the polishing pad near the top surface was effective in reducing the amount of ERO. In addition, we revealed small distance from the surface of the polishing pad at the area under the wafer to that at the area around the wafer was also effective in reducing the amount of ERO. On the basis of the findings, we developed a three-layered polishing pad which was expected to reduce the amount of ERO while achieving the good global flatness.