Virtual test reduces semiconductor product development time

In the semiconductor industry's evolutionary life cycle, the speed at which products are introduced to the market-place is key to the competitive success of individual companies. The semiconductor industry is classed as a fast-changing industry in which product technology, manufacturing process technology and industry organisation need to be continuously updated in relatively short cycle times. This paper looks at the test engineering aspect of the IC (integrated circuit) product development process and describes how an emerging `virtual test' methodology can be effectively applied to reduce the overall product development time for semiconductor devices     

Quick-turnaround-time improvement for product development andtransfer to mass production

We describe equipment and facility operational methods in a production fab which are designed to achieve quick-turnaround-time (QTAT) manufacturing and ease product transfer from development to mass production. An advanced CIM system with precise lot management is introduced to keep the optimum balance of manufacturing TAT and throughput. Substantial end-user computing reduces the engineering holding time for handling development lots. In situ monitoring technologies are applied for the utilization enhancement of plasma-assisted equipment. A 9% manufacturing TAT reduction and a 14% throughput increase are estimated using a manufacturing simulator. The number of wafers in QTAT lots is reduced for processing time reduction. As a result, manufacturing TAT of QTAT lots with reduction from 24 wafers to three is reduced to 56% compared with that of normal lots in the production fab. This new production fab realizes QTAT development and agile product transfer from development to mass production with full process compatibility     

Online multiobjective Pareto optimal dynamic scheduling of semiconductor back-end using conjunctive simulated scheduling

A discrete event simulation based "online near-real-time" dynamic multiobjective scheduling system has been conceptualized, designed, and developed to achieve Pareto optimal solutions in a complex manufacturing environment of semiconductor back-end. Our approach includes the use of linear weighted aggregation optimization approach for multiple objectives and auto simulation model generation for online simulation. Developed concepts are implemented at a semiconductor back-end site and are in use. The impact of the system includes a better customer delivery achievement, consistent cycle time with narrower distribution, improved machine utilization, reduction in the time that planners and manufacturing personnel spend on scheduling, and more predictable and repeatable manufacturing performance. In addition, it enables managers and senior planners to carry out "what now" analysis to make effective current decisions and "what if" analysis to plan for the future.     

Factory cycle-time prediction with a data-mining approach

An estimate of cycle time for a product in a factory is critical to semiconductor manufacturers (and in other industries) to assess customer due dates, schedule resources and actions for anticipated job completions, and to monitor the operation. Historical data can be used to learn a predictive model for cycle time based on measured and calculated process metrics (such as work-in-progress at specific operations, lot priority, product type, and so forth). Such a method is relatively easy to develop and maintain. Modern data mining algorithms are used to develop nonlinear predictors applicable to the majority of process lots, and three methods are compared here. They are compared with respect to performance in actual manufacturing data (to predict times for both final and intermediate steps) and for the feasibility to maintain and rebuild the model.     

Applications of single-wafer rapid-thermal processing to the manufacture of advanced flash memory

The application of single-wafer processing in semiconductor manufacturing has long been touted as the most effective way in reducing cycle time in a production environment as well as shortening the learning cycle for process development. However, one of the bottle neck areas is in the diffusion module in which conventional furnace processes are difficult to replace due to their superior film quality and high throughput. Recently, significant progress has been made in the areas of rapid thermal oxidation (RTO) and low-pressure chemical vapor deposition (LPCVD) such that high quality films of oxide, nitride, and polysilicon were achieved with great improvement in manufacturing cycle time. In this paper, nonvolatile memory devices such as flash EPROM will be used as examples to illustrate the effective applications of RTO and single-wafer LPCVD processes.     

Compound semiconductor equipment manufacturers perform well in VLSI survey

Compound semiconductor equipment manufacturers are well represented in this year’s VLSI customer satisfaction survey. Conducted annually, the survey looks at equipment performance and customer service, and asks semiconductor manufacturing equipment users to rank suppliers on a 10 point scale. Equipment performance is measured in terms of: build quality, cost of ownership, uptime, software, usable throughput, quality of results, and product performance. For customer service, the measures are: process support, field engineering support, spares support, support after sales, technical leadership in the supplier’s field and the supplier’s overall commitment to supporting its customers’ needs.This is a short news story only. Visit www.three-fives.com for the latest advanced semiconductor industry news.     

半导体封装测试厂库存控制系统的研究

在制品库存控制是生产制造系统的一项重要活动,它直接关系到工厂的产出、生产周期和物料投放。当前很多半导体封装测试厂还没有形成一个系统化的库存管理模式,导致库存过高或不均, 直接影响产出和生产成本。文章将阐述半导体封装测试厂如何选用并有效实施CONWIP系统,以及它在生产控制、降低库存和缩短生产周期上发挥的积极作用。     

Systematic defect improvement integration of dual damascene processes development on nano semiconductor fabrication

Process defects of semiconductor wafer nanotechnology manufacturing process can often impact product yields, depending on the type, size, and location of the defect, as well as the design and yield sensitivity of the respective semiconductor product devices. Manufacturing process-induced defects prevention should begin with an assessment of the critical risks associated with the wafer fabrications. Systematic identification and classification approaches have been introduced to improve the process yield by defects sampling and images reviewing. This study presents comprehensive investigation of a process defects monitor and integration on semiconductor copper manufacturing process and technology, and module process integration of the problem of defects reduction on semiconductor manufacturing processes. Experiments on electrical devices were performed to identify the defect source and determine the mechanism of defect formation, and integrated manufacturing processes implemented to eliminate defect issues are also investigated.     

Statistical Approach for Cycle Time Estimation in Semiconductor Packaging Factories

In the semiconductor industry, to enhance customer satisfactions and ability of quick responses, the development of cycle time estimation model is very important. Cycle time estimation is an essential planning basis, which has many applications, especially on the analyses of performance indexes, capacity planning, and the assignments of due dates. In this paper, we provide a statistical approach for cycle time estimation in semiconductor plastic ball grid array (PBGA) packaging factories. Due to today's fierce competitive environments in the semiconductor industry, planners involved in PBGA packaging factories need an approach to obtain estimated cycle times with different confidence to ensure the due date assignments more accurately. Therefore, upper confidence bounds of estimated cycle times at various confidence coefficients are also presented in this paper. We demonstrate the applicability of the proposed cycle time estimation model incorporating the upper confidence bounds by presenting a real-world example taken from a PBGA packaging shop floor in a semiconductor packaging factory located in the Science-Based Industrial Park in Hsinchu, Taiwan.      

仿真技术在半导体和集成电路生产流程优化中的应用

半导体和集成电路制造是一个流程高度复杂,资金高度密集的加工过程。集成电路制造的特殊性表现在产品工序的繁多,对设备的高利用率要求,和“再进入”(Re-entry)的流程特点。这种特殊的工艺流程特点决定了半导体集成电路工序中的排队优化选择策略比其他制造行业更为复杂,对生产效率和制造周期有更直接的影响。本文通过EXTEND仿真软件对英特尔的一个微型晶圆试验台进行初步研究,来说明计算机仿真手段在半导体集成电路生产流程优化中的作用。     

Efficient scheduling policies to reduce mean and variance ofcycle-time in semiconductor manufacturing plants

The problem of reducing the mean and variance of cycle time in semiconductor manufacturing plants is addressed. Such plants feature a characteristic reentrant process flow, where lots repeatedly return at different stages of their production to the same service stations for further processing, consequently creating much competition for machines. We introduce a new class of scheduling policies, called Fluctuation Smoothing policies. Unanimously, our policies achieved the best mean cycle time and Standard Deviation of Cycle Time, in all the configurations of plant models and release policies tested. As an example, under the recommended Workload Regulation Release policy, for a heavily loaded Research and Development Fabrication Line model, our Fluctuation Smoothing policies achieved a reduction of 22.4% in the Mean Queueing Time, and a reduction of 52.0% in the Standard Deviation of Cycle Time, over the baseline FIFO policy. These conclusions are based on extensive simulations conducted on two models of semiconductor manufacturing plants. The first is a model of a Research and Development Fabrication Line. The second is an aggregate model intended to approximate a full scale production line. Statistical tests are used to corroborate our conclusions     

半导体生产线建模方法与调度策略研究进展

半导体生产线是典型多重入复杂的制造系统，具有可重入性、复杂性、不确定性、多目标和多约束等特点，其优化调度问题是近年来控制领域的一个重要研究方向．本文根据近些年来这一研究方向上的主要研究成果，系统评述了国内外半导体生产线调度的建模方法和调度策略的研究进展，分析和讨论它们各自的主要优缺点和适用范围，简要介绍了重调度判定依据及所采用的方法，并指出半导体制造领域中值得进一步研究的一些问题和可能发展的方向．     

The impact of single-wafer processing on semiconductor manufacturing

In this paper, we have described the importance of single-wafer processing (SWP) in semiconductor manufacturing. As compared to batch processing, reduced cycle time, better control of surface and interface properties, and reduced defect densities are some of the attractive features of SWP. We have provided the example of new SWP tools that have the answers to address virtually all process integration issues in dealing with new materials as well as conventional materials in ultra small dimensions. Driven by reduced I/O pitches, and emergence of system-on-chip, system-in-package or system-on-package as the driver of semiconductor growth, SWP tools have started to play an important role in the surface cleaning in IC assembly and packaging. Global acceptance of SWP in manufacturing can address the supply chain problem of the semiconductor industry.     

Participative management: an empirical study of the semiconductormanufacturing industry

In order to stay competitive, semiconductor fabrication plants (fabs) must increase throughput and lower costs. At the same time, processes are becoming more complex with shorter life cycles. In this environment, some fabs are turning to their workforce for the added capacity, flexibility, and speed. This paper examines the effect of participative management techniques on manufacturing performance. Analyzing an international sample of 15 fabrication plants, the authors show that participative management has a statistically significant and positive correlation with manufacturing quality and a positive, but not statistically significant, correlation with quantity. The analysis also shows that the fabs in their sample tend to drive the individual components of participative management-power, information, rewards and knowledge-to the lowest level of the organization in a congruent fashion. This suggests that those fabs that utilize participative techniques do so efficiently     

Quantifying the environmental footprint of semiconductor equipment using the environmental value systems analysis (EnV-S)

Many environmental and health impacts from semiconductor processing are tied to the design of the manufacturing equipment. Evaluating solutions to properly treat effluents from semiconductor tools has become an increasingly important part of supply chain management and equipment procurement decisions. Accordingly, understanding the environmental footprint associated with equipment sets is essential for both equipment manufacturers and semiconductor manufacturers seeking to improve their products' environmental and financial performance. Equipment environmental performance must be evaluated within the context of the factory infrastructure and auxiliary equipment sets, with appropriate allocations of impacts from additional steps, both upstream and downstream of the wafer processing tools (chemical precursor delivery as well as byproduct treatment). Several challenges to environmental assessments arise from the nature of semiconductor manufacturing itself, due to short process life cycles, complexity of processes, and the need to track diverse inter-related impacts. Environmental value systems analysis (EnV-S) is an analytical tool to evaluate the environmental performance of semiconductor processing. EnV-S develops environmental assessments through a "bottom-up" analysis approach, assembling equipment environmental models to describe a system. This paper presents the use of EnV-S as a tool to quantify the environmental impact of a product or process by creating an operational signature along multiple dimensions of cost and environmental and health factors. The use of EnV-S is illustrated through a case study comparing systems that abate emissions from dielectric chemical vapor deposition processes.     

A Performance Driven Lot Merging Method with Closed Loop Optimization for Semiconductor Wafer Fabrication

This paper deals with lot merging problem in semiconductor wafer fabrication system.There is the possibility to merge two or more partial lots into single lot if their subsequent process routes are the same,an improved lot merging method is presented by grouping lots belonging to different orders.Based on job information extracted from the buffers,several bin packing and knapsack solving algorithms are used to determine which lots should be merged.An iterative improvement procedure is introduced for optimizing merging strategy through a heuristic algorithm with resetting the ready time of critical lots.The closed loop structure with global revision factor is built for minimizing the impact of uncertain events while balancing the different orders processing progress.Applied to a simulation semiconductor manufacturing fab,the proposed algorithm can reduce cycle time and tardiness compared with other methods currently.     

Modeling, analysis, simulation, scheduling, and control ofsemiconductor manufacturing systems: A Petri net approach

This paper presents a Petri net approach to modeling, analysis, simulation, scheduling, and control of semiconductor manufacturing systems. These systems can be characterized as discrete event systems that exhibit sequential, concurrent, and conflicting relations among the events and operations. Their evolution is dynamic over time. The system complexity is tremendous owing to the complex semiconductor manufacturing processes and test procedures. A formal approach such as Petri nets enables one to describe such complex discrete event systems precisely and thus allows one to perform both qualitative and quantitative analysis, scheduling and discrete-event control of them. This paper also serves as a tutorial paper. It briefly reviews applications of Petri nets in semiconductor manufacturing automation. It then introduces definitions and concepts of Petri nets. It proceeds with a discussion of basic Petri net modules in system modeling, a modeling method and a practical system's modeling example. Next, the paper presents their properties and their implications in manufacturing systems, as well as their analysis methods. Timed Petri nets are introduced for system simulation, performance evaluation, and scheduling purposes. An application-oriented case study is presented. Finally, the paper concludes with the active research areas in applying Petri nets to design of semiconductor manufacturing systems     

Empirical results on the relationship between die yield and cycletime in semiconductor wafer fabrication

A negative correlation between die yield and cycle time is frequently hypothesized for semiconductor wafer fabrication. Methods that aggregate die yield and cycle time statistics over time are shown to exaggerate correlation coefficients. A lot-by-lot analysis of die yield and cycle time data from four volume manufacturing facilities is performed. The results indicate that the correlation coefficient is often statistically insignificant. Where the correlation coefficient is significant, outlying data points are checked for assignable causes and removed pending proper explanation. In addition, statistical models regressing die yield on cycle time are poor, and thus should not be used as the basis of decision-making in production control     

Understanding a semiconductor process using a full-scale model

A full-scale semiconductor manufacturing plant model was developed from a SEMATECH dataset using the computer software package EXTEND. The model was generated to study the complex interactions and characteristics of a semiconductor fabrication process. Equipment downtimes, process flow routes, and machine processing times were used to validate the model. Pilot runs of the model were used to determine simulation run times and data collection rates for the initial inventory and product cycle time measurements. The product cycle time results from the model at 95% capacity were within 63 hours (or 7%) of the SEMATECH cycle time measurements. These results demonstrate the accuracy of the simulation model built from the SEMATECH dataset. The full-scale model was set up to run special scenarios showing the effects of eliminating maintenance and changing product types. The full-scale model was compared to a small-scale model based on the same dataset to demonstrate the inadequacy of the validated small-scale model. A full-scale model is also useful for analyzing scheduling routines, detecting bottlenecks, and understanding machine relations in the semiconductor industry     

A 300-mm Semiconductor Manufacturing Foreign Material Reduction Initiative

It is well established that foreign material (FM) in a semiconductor manufacturing process can result in significant unplanned tool down time, reduced product yields, and potential reliability performance issues. This paper will present an overview of the strategy and subsequent results of a multifaceted effort to reduce FM impact during the ramp up of the IBM 300-mm semiconductor manufacturing facility in Hopewell Junction, NY.