Characterizing wearout, breakdown and trap generation in thin silicon oxide

A model describing how wearout leads to breakdown in thin silicon oxides has been developed. During wearout defects or traps are generated inside the oxide and at the oxide interfaces. The signature of the trap generation is the permanent change in the transient current, in response to a voltage pulse, from an exponential decay to a 1/time decay. In oxides thinner than approximately 20 nm the dominant trap generation mechanism appears to be determined by the high fields across the oxides and not electron flow through the oxides. Locally higher current densities, flowing through the traps generated during wearout, lead to local breakdown. This model is critically dependent on the measurement of the properties of the traps generated inside the oxides during the wearout phase. The techniques for measurement of these traps and some of their properties have been described. The ability of this model to describe oxide charging, low-level leakages, transient currents, the role of asperities, polarity dependences, and the fluence, time, thickness, voltage and temperature dependences of oxide breakdown distributions has been discussed.     

Trap generation and breakdown processes in very thin gate oxides

Neutral electron traps are generated in gate oxide during electrical stress, leading to degradation in the form of stress-induced leakage current (SILC) and eventually resulting in breakdown. SILC is the result of inelastic, trap-assisted tunneling of electrons that originate in the conduction band of the cathode. Deuterium annealing experiments call into question the interfacial hydrogen release model of the trap generation mechanism. A framework for modeling time-to-breakdown is presented.     

Gate oxide breakdown statistics in wearout tests of metal-oxide-semiconductor structures

Experimental breakdown data of different MOS structures under different wearout tests support the validity of a new physical approach to the breakdown statistics. This model is based on the idea that the dielectric breakdown is intimately related to the previous degradation of the SiO₂ network, and particularly, to the generation of neutral electron trapping sites. The main properties of the widely used extreme-value statistical distributions are preserved, and the parameters involved have a natural physical interpretation. Only two parameters have been used to build up the model and to fit the experimental: data the minimum area that has to be degraded for the breakdown to be effective, and the critical number of traps that has to be locally generated to trigger the breakdown. Although the analytical calculations have provided excellent results, the Monte Carlo method has been shown to be powerful technique to introduce second-order effects in the sudy of the breakdown statistics.     

An operational definition for breakdown of thin thermal oxides of silicon

As MOS devices with thinner gate oxides are put into production, the high-field oxide breakdown definition used for process monitoring must be revised to account for noncatastrophic electrical conduction. This conduction is due to electron injection by Fowler-Nordheim tunneling into the oxide conduction band, and it can be as large as 0.1 A/cm²without causing irreversible breakdown of thin oxides. We propose that breakdown should be defined as the passage of a large current at a low value of applied electric field, after stressing of the oxide at a high field. We show that this definition represents a truly irreversible catastrophic breakdown, that it can be adapted easily for automated testing, and that it yields reliable results for breakdown of thin (less than 500 Å) gate oxides.     

High-field breakdown in thin oxides grown in N2O ambient

A detailed study of time-dependent dielectric breakdown (TDDB) in N₂O-grown thin (47-120 Å) silicon oxides is reported. A significant degradation in breakdown properties was observed with increasing oxide growth temperatures. A physical model based on undulations at the Si/SiO₂ interface is proposed to account for the degradation. Accelerated breakdown for higher operating temperatures and higher oxide fields as well as thickness dependence of TDDB are studied under both polarities of injection. Breakdown under unipolar and bipolar stress in N₂O oxides is compared with DC breakdown. An asymmetric improvement in time-to-breakdown under positive versus negative gate unipolar stress is observed and attributed to charge detrapping behavior in N₂O oxides. A large reduction in time-to-breakdown is observed under bipolar stress when the thickness is scaled below 60 Å. A physical model is suggested to explain this behavior. Overall, N₂O oxides show improved breakdown properties compared with pure SiO₂     

Soft breakdown and hard breakdown in ultra-thin oxides

Soft breakdown (SBD) and hard breakdown (HBD) events are characterised separate of each other for a 3.4 nm gate oxide. It is shown that both breakdown events can have significantly different voltage and temperature acceleration behaviour. Further it is demonstrated by photoemission microscopy (PEM) for a 2.2 nm oxide that different types of breakdown paths exist. HBD-like and SBD-like breakdowns are found on the same gate area during constant voltage stress. PEM also points out that a structural change of a breakdown path can occur, usually referred to as thermal breakdown of SiO₂. It is concluded that a separate characterisation of SBD and HBD events is correct, if the stress conditions do not cause this structural change for the first SBD event.     

Stress voltage polarity dependence of thermally grown thin gateoxide wearout

Gate oxide wearout for thermally grown 57-190-A SiO₂ films in a polycrystalline silicon-SiO₂-Si structure prepared on n-type and p-type wafers was studied by examining time-dependent dielectric breakdown (TDDB) under 1-mA/cm² constant current with positive and negative voltages at 250°C. TDDB lifetimes for positive voltage stress are more than one order longer than those for negative voltage stress. TDDB lifetimes depend on oxide thickness, that is, they increase for positive voltage stress and decreases for negative voltage stress with decreasing oxide thickness. They also depend on whether the oxide films are prepared on n-type or p-type wafers. After the positive voltage TDDB stress, negative charges are predominantly produced in the oxide layer, and the electric field at the cathode in the oxide film slightly decreases. On the contrary, after the negative voltage TDDB stress, positive charges are predominantly produced at the cathode in the oxide layer and the electric field at the cathode is built up, resulting in an increase in Fowler-Nordheim tunnel current flowing though the oxide film     

Statistics of soft and hard breakdown in thin SiO2 gate oxides

Assuming that there are circuit applications which can tolerate one or several soft breakdown events before failure, we study the implications of soft/hard breakdown prevalence ratios on the device failure statistics. Our results demonstrate that these two breakdown modes are triggered by the same type of defect-related path, showing identical statistics if considered as independent breakdown mechanisms. An energy dissipation model for the breakdown current runaway transient is presented as a possible way to model soft and hard breakdown prevalence ratios as a function of stress conditions and sample characteristics.     

Stress polarity dependence of the activation energy intime-dependent dielectric breakdown of thin gate oxides

Stress polarity dependence of the activation energies in the two time dependent dielectric breakdown measurements, the constant-current injection (Q_bd testing) and the constant-voltage stressing (t _bd testing) are investigated for gate oxides with the thickness ranging from 10 to 4 nm. A remarkable polarity dependence of the activation energies appears in the t_bd testing when the oxide thickness decreases. This phenomenon is found to be due to a characteristic temperature dependence of the gate current density during the whole t_bd testing period for thinner oxides, which is considered as a result from the temperature dependence of the electron trapping process during the stressing     

Time dependent dielectric wearout (TDDW) technique for reliabilityof ultrathin gate oxides

The degradation of ultrathin oxides is measured and characterized by the dual voltage time dependent dielectric wearout (TDDW) technique. Compared to the conventional time-dependent dielectric breakdown (TDDB) technique, a distinct breakdown can be determined at the operating voltage I-t curve. A noisy, soft prebreakdown effect occurs for 1.8-2.7 nm ultrathin oxides at earlier stress times. The different stages of wearout of 1.8-2.7 nm oxides are discussed. The wearout of oxide is defined when the gate current reaches a critical current density at the circuit operating voltage. Devices still function after the soft breakdowns occur, but are not functional after the sharp breakdown. However, application of the E model to project the dielectric lifetime shows that this is more than 20 y for thermal oxides in the ultrathin regime down to 1.8 nm     

Micro breakdown in small-area ultrathin gate oxides

The purpose of this work was to study the gate oxide leakage current in small area MOSFETs. We stressed about 300 nMOSFETs with an oxide thickness t/sub OX/=3.2 nm by using a staircase gate voltage. We detected the oxide breakdown at an early stress stage, by measuring the leakage current at low fields during the stress. The gate leakage of stressed devices is broadly distributed, but two well-defined current regimes appear, corresponding to currents larger than 1 mA or smaller than 100 pA, respectively. We focused our attention on the small current regime, which shows all the electrical characteristics typical of the soft breakdown, with the noticeable exception of the current intensity that is much smaller than usually reported in literature, being the average leakage around 40 pA at V/sub G/=+2 V. For this reason, we introduce the oxide micro breakdown. The leakage kinetics during stress, the gate-voltage characteristics of stressed devices and the breakdown statistical distributions are in agreement with the formation of a single conductive path across the oxide formed by few oxide defects. Just two positively charged traps can give rise to a gate leakage comparable to those experimentally found, as evaluated by using a new original model of double trap-assisted tunneling (D-TAT) developed ad hoc.     

Cell-based analytic statistical model with correlated parametersfor intrinsic breakdown of ultrathin oxides

The cell-based analytic statistical model, with the cell area A _O and the critical trap number per cell n_BD both as parameters, is one of the widely cited literature models in calculating the critical density of neutral electron traps that trigger the intrinsic breakdown of ultrathin oxides. This letter reports a new correlation between A_O and n_BD, which can effectively reduce the cell-based model to one with the only fitting parameter n_BD. Reproduction of charge-to-breakdown data has shown that (1) n_BD decreases for reduced oxide thicknesses and (2) the range of intrinsic breakdown is relatively narrowed for increasing areas. The work also addresses the ultimate thickness limit for breakdown, as set critically at n_BD=1     

Analysis of errors in estimating wearout characteristics of time-dependent dielectric breakdown using system-level accelerated life test

Reliability issues exacerbated by small feature sizes in modern VLSI circuits challenge an accurate reliability assessment using the conventional approach of employing device-level accelerated life test. Since such device-level reliability assessment ignores tolerance of a circuit or a system to device wearout failures, to accurately estimate circuit/system reliability, we need to directly test a circuit or a system for extraction of wearout parameters in operating environments. In this paper, we propose a system-level accelerated life test to compliment device-level accelerated life test. We also investigate errors in estimating wearout parameters from time-dependent dielectric breakdown (TDDB) from experimental results from system-level accelerated life test and note differences from device-level reliability assessment.     

Statistics of successive breakdown events in gate oxides

The basic statistics for devices/circuits that can tolerate several breakdown (BD) events without failure are derived. All the presented results are analytical and do not rely on the validity of any model relating breakdown to defect generation. The single requirement is the uniform and uncorrelated generation of breakdown paths. Significant lifetime improvement is anticipated for low failure percentiles and Weibull slopes close to unity, as those found in oxides with the thickness required for sub-100-nm CMOS technologies. The presented results are validated using grouping experiments.     

Charge to breakdown mechanism of thin ONO films

Effects of charge trapping in the thin ONO (oxide silicon nitride oxide) film caused by the voltage stress on the time-dependent dielectric breakdown (TDDB) mechanism are studied. The purpose is to report the TDDB data of the films after various treatments of charge injection and thermal annealing together with analysis of the experimental data to enhance the understanding of the dielectric breakdown mechanisms of the ONO film. It is observed that the trapped charges injected from one electrode have very little effect on the TDDB mechanism during stress to the other electrode. This suggests that the position of trapped charges may be quite different for the two injecting electrodes and that breakdown mechanisms may be initiated from the different charge positions and sources     

Accelerated dielectric breakdown and wear out standard testing methods and structures for reliability evaluation of thin oxides

This paper describes the various methods used for the assessment of the breakdown and wear out properties of thin oxides currently employed in CMOS and EEPROM technologies. Standard procedures for breakdown and wear out testing are given in conjunction with the associated test structures required for their accomplishment.     

A characterization model for ramp-voltage-stressed I-V characteristics of thin thermal oxides grown on silicon substrate

A theoretical model considering the effects of Fowler-Nordheim tunneling, image-force lowering, first-order trapping kinetics and impact ionization has been developed to characterize the ramp-voltage stressed current-voltage characteristics of thin oxides grown on silicon substrate. Based on the developed model, physical parameters of thin oxides such as effective total trapping density, trap capture cross section, recombination capture cross section and dielectric breakdown field can be extracted from the measurements. In general, the dielectric field strength of the oxide can be enhanced by increasing the amount of traps, which is especially important when the effective total trapping density is above 10¹³ cm⁻². Besides, smaller leakage current across thin oxide can be obtained with larger effective total trapping density and trap capture cross section. The recombination capture cross section is found to be in the order of 10⁻¹⁵–10⁻¹⁴ cm² for thin SiO₂ ranging from 92 to 196 Å. The dielectric field strength is enhanced and the leakage current is reduced as the trapped electron centroid shifts toward the cathode electrode, however, this is less prominent when the effective total trapping density is ⩽10¹² cm⁻².     

Electric breakdowns and breakdown mechanisms in ultra-thin silicon oxides

It was found that the breakdown times measured using time-dependent-dielectric-breakdown (TDDB) distributions could be shifted to shorter times when the amount of energy available during the breakdown event was increased. The TDDB distributions were non-unique and breakdown models must account for both electrical breakdowns and dielectric breakdown. A novel approach for obtaining breakdown distributions will be presented. This approach uses a small number of oxides to obtain a time-dependent-electric-breakdown (TDEB) distribution, which will be shown to provide complementary information to that obtained from (TDDB) distributions. While the observation of dielectric breakdown in ultra-thin dielectrics may be difficult using standard test conditions, it will be shown that electric breakdowns are relatively easy to observe.