A low-voltage 5.1-5.8-GHz image-reject downconverter RF IC

This paper describes a single-chip implementation of a low-voltage image-reject downconverter for a 5.1-5.8-GHz radio receiver. It consists of a low-noise preamplifier (LNA) that is simultaneously noise and power matched to the RF source, and dual doubly balanced mixers coupled to the LNA by a monolithic trifilar transformer. The image-reject architecture eliminates an RF filter, thereby simplifying packaging requirements. The downconverter realizes over 36 dB of image rejection while dissipating 24 mW from a 0.9 V supply, or 18.5 mW at 1.8 V. Conversion gain is 14 dB, IIP3=-5.5 dBm, and noise figure is 6.8 dB (single sideband 50 Ω) when operating from a 0.9 V supply     

A superheterodyne receiver front-end with on-chip automatically Q-tuned notch filters

A superheterodyne receiver front-end with on-chip automatically Q-tuned notch filters is proposed. The front-end includes a differential LNA and a Gilbert down-converter, where each block is coupled with an on-chip image-rejection notch filter to get high image-rejection ratio. Each notch filter is formed by one on-chip LC network and one negative-resistance cross-coupled pair to compensate for the loss of the LC network. The current through the cross-coupled pairs is automatically adjusted by an automatic Q tuning circuit so that the loss of the notch filter is perfectly compensated to achieve a deepest notch. The automatic Q tuning circuit is an analog?Cdigital mixed signal circuit, and successive approximation register algorithm is used to search for the optimum current value. The superheterodyne receiver front-end has been implemented in 0.18???m CMOS. Experimental results show that the circuit could achieve an image rejection ratio of 75?dB with 105?MHz IF Frequency. The LNA draws 5.86?mA current, and the down-converter draws 1.27?mA current while two image-rejection filters and the master VCO totally draw 363???A current, all from a 1.8?V power supply.     

一种接收前端三级低噪声放大器的设计

针对单片雷达接收机中对低噪声放大器（LNA）的要求,采用CMOS0．18,um工艺设计了一个三级级联的镜像抑制低噪声放大器。通过在低噪声放大器中接入限波滤波器,实现对镜像信号的衰减,从而减小了后端混频器电路的设计难度。在ADS中对设计的放大器仿真,其结果为：最大供电电压为5V情况下,信号频段为3．0～3．2GHz,中频输出为225MHz,功率增益≥31dB,噪声系数（FN）≤O．5dB,1dB点的输入／输出功率分别为-19．5dBm和11．5dBm,对镜像信号的抑制度达22dB。     

A 1.9-GHz silicon receiver with monolithic image filtering

A 1.9-GHz fully monolithic silicon superheterodyne receiver front-end is presented; it consists of a low noise amplifier (LNA), a tunable image reject filter, and a Gilbert cell mixer integrated in one die. The receiver was designed to operate with a 1.9-GHz RF and a 2.2-GHz local oscillator (LO) for a 300-MHz IF. Two chip versions were fabricated on two different fabrication runs using a 0.5-μm bipolar technology with 25 GHz transit frequency (f_T). Measured performance for the receiver front-end version 1, packaged and without input matching, was: conversion gain 33.5 dB, noise figure 4.9 dB, input IP3 -28 dBm, image rejection 53 dB (tuned to reject a 2.5-GHz image frequency), and 15.9 mA current consumption at +3 V. The image rejection was tunable from 2.4-2.63 GHz by means of an on-chip varactor. Version 2 had increased mixer degeneration for improved linearity. Its measured performance for the packaged receiver with its input matched to 50 Ω was: conversion gain 24 dB, noise figure 4.8 dB, input IP3 -19 dBm, and 65 dB image rejection for a 2.5-GHz image with an image tuning range from 2.34-2.55 GHz     

5-GHz SiGe HBT monolithic radio transceiver with tunable filtering

A wide-band CDMA-compliant fully integrated 5-GHz radio transceiver was realized in SiGe heterojunction-bipolar-transistor technology with on-chip tunable voltage controlled oscillator (VCO) tracking filters. It allows for wide-band modulation schemes with bandwidth up to 20 MHz. The receiver has a single-ended single-sideband noise figure of 5.9 dB, more than 40 dB on-chip image rejection, an input compression point of -22 dBm, and larger than 70 dB local-oscillator-RF isolation. The phase noise of the on-chip VCO is -100 and -128 dBc/Hz at 100 kHz and 5 MHz offset from the carrier, respectively. The transmitter output compression point is +10 dBm. An image rejection better than 40 dB throughout the VCO tracking range has been demonstrated in the transmitter with all spurious signals 40 dB below the carrier. The differential transceiver draws 125 mA in transmit mode and 45 mA in receive mode from a 3.5-V supply     

A crystal-tolerant fully integrated CMOS low-IF dual-band GPS receiver

This paper presents the design of a dual-band L1/L2 GPS receiver, that can be easily integrated in portable devices (mainly GSM mobile phones). For the ease of integration with GSM wireless systems the receiver can tolerate most of the common GSM crystals, besides the GPS crystals, this will eliminate the need to use another crystal on board. A new frequency plan is presented to satisfy this requirement. A low-IF receiver architecture is used for dual-band operation with analog on-chip image rejection. The receiver is composed of a narrow-band LNA for each band, dual down-conversion mixers, a variable-gain channel filter, a 2-bit analog-to-digital converter, and a fully integrated frequency synthesizer including an on-chip VCO and loop filter. The complex filter can accept IF frequency variation of 10% around 4.092 MHz which allows the use of the commonly used 10/13/26 MHz GSM crystals and all the GPS crystals. The synthesizer generates the LO signals for both L1/L2 bands with an average phase noise of −95 dBc/Hz. The receiver exhibits maximum gain of 112 and 115 dB, noise figures of 4 and 3.6 dB, and input compression points of −76 and −79 dBm for L1 and L2, respectively. An on-chip variable-gain channel filter provides IF image rejection greater than 25 dB and gain control range over 80 dB. The receiver is designed in 0.13 μm CMOS technology and consumes 18 mW from a 1.2-V supply.     

A 5-GHz CMOS wireless LAN receiver front end

This paper presents a 12.4-mW front end for a 5-GHz wireless LAN receiver fabricated in a 0.24-μm CMOS technology. It consists of a low-noise amplifier (LNA), mixers, and an automatically tuned third-order filter controlled by a low-power phase-locked loop. The filter attenuates the image signal by an additional 12 dB beyond what can be achieved by an image-reject architecture. The filter also reduces the noise contribution of the cascode devices in the LNA core. The LNA/filter combination has a noise figure of 4.8 dB, and the overall noise figure of the signal path is 5.2 dB. The overall IIP3 is -2 dBm     

0.18 /spl mu/m CMOS dual-band UWB LNA with interference rejection

A CMOS dual-band ultra-wideband low noise amplifier (LNA) with interference rejection is presented. The proposed LNA employs a current reuse structure to reduce power consumption and an active notch filter to produce in-band rejection in the 5 GHz WLAN frequency band. The load tank of the current reuse stage is optimised to provide an additional out-band attenuation in the 2.4 GHz WLAN band. Measurement shows a peak gain of 19.7 dB in the low band (3-5 GHz) and 20.3 dB in the high band (6-10 GHz), while the in-band and out-band maximum rejections are 19.6 and 12.8 dB, respectively.     

A Low-Noise Amplifier With Tunable Interference Rejection for 3.1- to 10.6-GHz UWB Systems

An ultrawideband common-gate low noise amplifier with tunable interference rejection is presented. The proposed LNA embeds a tunable active notch filter to eliminate interferer at 5-GHz WLAN and employs a common-gate input stage and dual-resonant loads for wideband implementation. This LNA has been fabricated in a 0.18-$mu$m CMOS process. The measured maximum power gain is 13.2 dB and noise figure is 4.5–6.2 dB with bandwidth of 3.1–10.6 GHz. The interferer rejection is 8.2 dB compared to the maximum gain and 7.6 dB noise figure at 5.2 GHz , respectively. The measured input P1dB is ${-} $11 dBm at 10.3 GHz. It consumes 12.8 mA from 1.8-V supply voltage.      

Design of a full-band CMOS UWB receiver and fast-hopping carrier generator for 3.1–10.6 GHz

This paper presents an interference rejection full-band UWB receiver and fast hopping carrier generator for 3.1–10.6 GHz. This receiver enables 11 bands of operation by embedding a tunable notch filter to eliminate interferers in a 5 GHz wireless local area network. The carrier generator can cover 3.1–10.6 GHz within less than 9.5 ns. The receiver, based on the proposed multi-band OFDM standard, consists of a zero-IF receive chain and required system noise figure, the receiver linearity specifications of which are discussed in this paper. It consists of a single-ended low-noise amplifier (LNA), a down-conversion mixer, a low-pass filter (LPF), and a programmable gain amplifier with an IO buffer. The LNA employs a common-gate topology of the 1st stage with dual-resonant loads, a cascade amplifier of the 2nd stage for mid-band resonance, and a tunable notch filter. The down-conversion mixer adopts a single-balanced architecture with LO cancellation. The LPF is implemented based on an active RC topology, and implements a four-stage programmable gain amplifier. The receiver dissipates 49.3 mA from a 1.8 V power supply. The average voltage conversion gain of the receiver IC is 73.5 dB, and the system noise figure is 8.4 dB. Input P1dB increases from ?36.8 dBm at 4 GHz to ?30.5 dBm at 10.3 GHz. The attenuation is 8.5 dB, which is achieved in the interference rejection band at 5.2 GHz. It occupies an area of 0.98 × 3.3 mm² including the bond pads.     

Design of low-voltage cmos low-noise amplifier with image-rejection function

A new design is presented that combines a low-noise amplifier (LNA) with an on-chip filter instead of external filter to eliminate image signal based on TSMC 0.18 mum CMOS technology. The fully integrated 5.9 GHz LNA exhibits 15.2 dB gain, 3.2 dB noise figure, better than -15 dB input and output return loss, and -27 dB image rejection. The circuit operates at a supply voltage of 1 V and consumes only 6.1 mW power.     

具有带外抑制特性的Ka波段低功耗低噪声放大器

基于0.15μm GaAs赝配高电子迁移率晶体管(PHEMT)工艺,成功研制了一款30~34 GHz频带内具有带外抑制特性的低功耗低噪声放大器(LNA)微波单片集成电路(MMIC)。该MMIC集成了滤波器和LNA,其中滤波器采用陷波器结构,可实现较低的插入损耗和较好的带外抑制特性;LNA采用单电源和电流复用结构,实现较高的增益和较低的功耗。测试结果表明,该MMIC芯片在30~34 GHz频带内,增益大于28 dB,噪声系数小于2.8 dB,功耗小于60 mW,在17~19 GHz频带内带外抑制比小于-35 dBc。芯片尺寸为2.40 mm×1.00 mm。该LNA MMIC可应用于毫米波T/R系统中。     

A single-chip GaAs MMIC image-rejection front-end for digitalEuropean cordless telecommunications

An active image-rejection filter is presented in this paper, which applies actively coupled passive resonators. The filter has very low noise and high insertion gain, which may eliminate the use of a low-noise amplifier (LNA) in front-end applications. The GaAs monolithic-microwave integrated-circuit (MMIC) chip area is 3.3 mm² . The filter has 12-dB insertion gain, 45-dB image rejection, 6.2-dB noise figure, and dissipates 4.3 mA from a 3-V supply. An MMIC mixer is also presented. The mixer applies two single-gate MESFETs on a 2.2-mm² GaAs substrate. The mixer has 2.5-dB conversion gain and better than 8-dB single-sideband (SSB) noise figure with a current dissipation of 3.5 mA applying a single 5-V supply. The mixer exhibits very good local oscillator (LO)/RF and LO/IF isolation of better than 30 and 17 dB, respectively, Finally, the entire front-end, including the LNA, image rejection filter, and mixer functions is realized on a 5.7-mm ² GaAs substrate. The front-end has a conversion gain of 15 dB and an image rejection of more than 53 dB with 0-dBm LO power. The SSB noise figure is better than 6.4 dB, The total power dissipation of the front-end is 33 mW. The MMIC's are applicable as a single-block LNA and image-rejection filter, mixer, and single-block front-end in digital European cordless telecommunications. With minor modifications, the MMIC's can be applied in other wireless communication systems working around 2 GHz, e.g., GSM-1800 and GSM-1900     

Single-Stage Low-Power Quadrature RF Receiver Front-End: The LMV Cell

This paper presents the first quadrature RF receiver front-end where, in a single stage, low-noise amplifier (LNA), mixer and voltage-controlled oscillator (VCO) share the same bias current. The new structure exploits the intrinsic mixing functionality of a classical LC tank oscillator providing a compact and low-power solution compatible with low-voltage technologies. A 0.13-mum CMOS prototype tailored to the GPS application is presented. The experimental results exhibit a noise figure of 4.8 dB, a gain of 36 dB, an IIP3 of -19 dBm with a total power consumption of only 5.4 mW from a voltage supply of 1.2 V     

基于RC-CR多相网络的镜频抑制接收机MMIC

基于RC-CR多相网络技术研制了一款S波段镜频抑制接收机单片微波集成电路(MMIC),在MMIC芯片上集成S波段低噪声放大器(LNA)、差分IQ混频器、本振(LO)驱动放大器、RC-CR多相网络滤波器等电路单元,实现了S波段单片镜频抑制接收机,解决了镜频接收机小型化的问题.电路、电磁场软件仿真以及采用GaAs赝配高电子迁移率晶体管(PHEMT)工艺流片后的结果表明,在S波段实现了噪声系数小于1.8 dB,增益大于12 dB,中频(150±5) MHz带内镜频抑制大于35 dBc的技术指标.MMIC的芯片尺寸为4.8 mn×2.5 mm×0.07 mm.此镜频抑制接收机MMIC具有指标优异、体积小、集成度高的特点,可广泛用于各种需小型化的相控阵雷达和通信系统中.     

Post-linearization with image rejection for high IIP3 and image-rejection ratio of a 17 GHz CMOS low noise amplifier

This study develops a post-linearization technique to simultaneously improve the input third-order intercept point (IIP3) and image-rejection ratio (IRR) of a 17 GHz low noise amplifier (LNA) in a 0.18 μm standard CMOS process. A third-order intermodulation distortion (IMD3) compensator constructed by a second-order notch filter was proposed to achieve both high linearity and image reject (IR) of the cascode LNA. The correlation between the post-linearization and IR techniques is analyzed and discussed. The measured LNA achieved a gain of 16.5 dB, a noise figure (NF) of 4.58 dB, an IIP3 of 0 dBm, and an IRR from 68 to 78 dB. The improvements of IIP3 and IRR are 11.7 and 46 dB, respectively, better than that of the LNA without the notch filter. The proposed IR LNA with total current dissipation of 4.8 mA under 1.8 V supply voltage and notch filter only dissipate a DC power of 2 mW.     

A low-noise mixer with an image-reject notch filter for 2.4 GHz applications

This paper presents a low noise first down-conversion mixer with a notch filter for the heterodyne receiver. The notch filter connected to the output node of the mixer driver stage plays a role of image rejection at an image frequency, thereby suppressing the sideband image noise and improving the mixer noise performance. Targeted for 2.4 GHz industrial-scientific-medical band applications, a simple source-degenerated down-conversion single balanced mixer with the filter is implemented. The measurement results of the proposed down-conversion mixer shows about 3.0 dB improvement of single-side band noise figure, about 2.9 dB power conversion gain improvement, and 25 dB image suppression compared to those without the filter dissipating 4 mA from a 2.5 V supply voltage.     

A Fully Integrated Direct-Conversion Receiver for CDMA and GPS Applications

This paper describes a fully integrated zero-IF receiver for cellular CDMA and GPS applications. The single-chip zero-IF receiver integrates the entire signal path for CDMA and GPS bands, including a low-noise amplifier (LNA), I/Q down-converters, baseband channel selection filters (CSFs), a voltage-controlled oscillator (VCO), and a local oscillator (LO) distribution circuit for each band. The cellular-band LNA achieves a noise figure (NF) of 1.2 dB, input third-order intercept point (IIP3) of 11 dBm, and gain of 15.5 dB. Cellular I/Q down-converter and baseband circuitries show 9-dB composite NF, 9 dBm IIP3 and 60-dBm input second-order intercept point (IIP2) without IIP2 calibration. The measured LO leakage is less than -110 dBm at LNA input. The phase noise of the cellular VCO is -134 dBc/Hz at 900-kHz offset with 1.76-GHz carrier frequency. Total GPS signal path achieves NF of 1.7 dB and gain of 74 dB with 42-mA current. The receiver is fabricated in a 0.35-mum SiGe BiCMOS process and packaged in a 6 mm times 6 mm 40-pin micro-lead-frame. Handset measurements report that the receiver meets or exceeds all of the CDMA-2000 requirements     

2.4 GHz ISM-Band Receiver Design in a 0.18 μm Mixed Signal CMOS Process

This letter presents the design and measurement results of a fully integrated CMOS receiver front-end and voltage controlled oscillator (VCO) for 2.4 GHz industrial, scientific and medical (ISM)-band application. For low cost design, this receiver has been fabricated with a 0.18 mum thin metal CMOS process with a top metal thickness of only 0.84 mum. The receiver integrates radio frequency (RF) front-end (a single-ended low-noise amplifier (LNA) with on-chip spiral inductors and a double balanced down conversion mixer), VCO and local oscillation buffers on a single chip together with an internal output buffer. To obtain the high-quality factor inductor in LNA, VCO and down conversion mixer design, patterned-ground shields (PGS) are placed under the inductor to reduce the effect from image current of resistive Si substrate. Moreover, in VCO and mixer design, due to the incapability of using thick top metal layer of which the thickness is over 2 mum, as used in many RF CMOS process, the structure of dual-metal layer in which we make electrically short circuit between the top metal and the next metal below it by a great number of via arrays along the metal traces is adopted to compensate the Q -factor degradation. In this letter, the receiver achieves a conversion gain of 23 dB, noise figure of 8.1 dB and P1 dB of -20 dBm at 39 MHz with 21 mW power dissipation from a 1.8 V power supply. It occupies a whole circuit area of 2 mm².     

High Performance Millimeter‐Wave Image Reject Low‐Noise Amplifier Using Inter‐stage Tunable Resonators

A Q‐band pHEMT image‐rejection low‐noise amplifier (IR‐LNA) is presented using inter‐stage tunable resonators. The inter‐stage L‐C resonators can maximize an image rejection by functioning as inter‐stage matching circuits at an operating frequency (F_OP) and short circuits at an image frequency (F_IM). In addition, it also brings more wideband image rejection than conventional notch filters. Moreover, tunable varactors in L‐C resonators not only compensate for the mismatch of an image frequency induced by the process variation or model error but can also change the image frequency according to a required RF frequency. The implemented pHEMT IR‐LNA shows 54.3 dB maximum image rejection ratio (IRR). By changing the varactor bias, the image frequency shifts from 27 GHz to 37 GHz with over 40 dB IRR, a 19.1 dB to 17.6 dB peak gain, and 3.2 dB to 4.3 dB noise figure. To the best of the authors' knowledge, it shows the highest IRR and F_IM/F_OP of the reported millimeter/quasi‐millimeter wave IR‐LNAs.