Design of a Negative-Impedance Converter and Its Application for a TV Deflection Circuit

Most horizontal deflection circuits used in TV cameras or TV receivers are deflection circuits operated by the switching function of transistors. This type of circuit is well known as an efficient deflection system having less power consumption, however, because there is a resistance existing in the deflection coil or within the circuit, it has a defect in that distortion is liable to occur in the deflection current. In order to improve the linearity of this deflection current, various methods were offered in the past, however, nothing definite has been found to solve this problem.     

Resistive Bridging Defect Detection in Bulk,FDSOI and FinFET Technologies

Fully Depleted Silicon on Insulator (FDSOI) and Fin Field Effect Transistor (FinFET) are likely alternatives to traditional planar Bulk transistors for future technologies due to their respective promising ways of tackling the scalability issues with better short channel characteristics. Both these technologies are aiming in particular at regaining a better electrostatic control by the gate over the channel of the transistor. However, FDSOI is a planar MOS technology and as a result it is much more in continuity with planar Bulk as compared to the vertical FinFET transistors. The competition between these two technologies is fierce and many studies have been reported in the literature to compare these technologies in terms of speed performance, power consumption, cost, etc. However, these studies have not yet focused on their testability properties while the impact of defects on circuits implemented in FDSOI and FinFET technologies might be significantly different from the impact of similar defects in planar MOS circuit. It is therefore the objective of the paper to address this aspect. More specifically, we analyze the electrical behavior of logic gates in presence of a resistive bridging defect for these three different technologies. A particular care has been taken to design transistors and elementary gates in such a way that the comparative analysis in different technologies is meaningful. After implementing similar design in each technology, we compare the electrical behavior of the circuit with the same resistive bridging defect and we analyze both the static and dynamic impact of this defect.     

Novel pseudo-exponential circuits

In this paper, two voltage-mode circuits that implement the pseudo-exponential function using controllable gain blocks are presented. The gain block of the proposed circuits each utilize a current conveyor and an operational amplifier in a novel manner. They offer the advantages that they are precise, easily implemented in integrated circuit (IC) form and can employ a bank of switched resistors, MOS transistors in triode or transconductors to change their gain according to a control parameter /spl chi/ that is determined by a ratio of resistances. Experimental results using discrete IC components confirm the theory and show the circuits having an output range of approximately 22 dB, with an error of less than 1 dB for x greater than -0.55 and less than 0.63.     

Classification of Defective Analog Integrated Circuits Using Artificial Neural Networks

This paper presents a new approach for detecting defects in analog integrated circuits using the feed-forward neural network trained by the resilient error back-propagation method. A feed-forward neural network has been used for detecting catastrophic faults randomly injected in a simple analog CMOS circuit by classification the differences observed in supply current responses of good and faulty circuit. The experimental classification was performed for time and frequency domain, followed by a comparison of results achieved in both domains. It was shown that neural networks might be very efficient and versatile approach for test of analog circuits since an arbitrary fault class or circuit's parameter can be analyzed. Considered defect types and their successful detection by the neural network; and a possible off-chip hardware implementation of the proposed technique are discussed as well. Moreover, optimized hardware architecture of the selected neural network type was designed using VHDL for FPGA realization.     

Behavior of a radiation-immune CMOS logic family under resistiveshorts

Previous researchers had developed a special family of CMOS logic circuits which uses additional feedback transistors to provide immunity to radiation-induced errors for space-borne electronics. It was originally speculated that these transistors, representing a form of redundancy, might provide additional benefits, such as greater tolerance of manufacturing defects. Instead, the authors work shows that the redundant transistors, because of the way in which they are used, increase the sensitivity of the circuitry to manufacturing defects which manifest themselves as resistive transistor shorts, such faults cause: (1) logic errors at the affected gate output; and (2) an increase in the signal transition delay. Furthermore, these transistors lead to higher levels of quiescent supply current, making the circuits more difficult to test using quiescent current (I_DDQ) testing     

High-speed 8:1 multiplexer and 1:8 demultiplexer implemented withAlGaAs/GaAs HBTs

An 8:1 multiplexer (MUX) and 1:8 demultiplexer (DMUX) implemented with AlGaAs/GaAs heterojunction bipolar transistors are described. The circuits were designed for lightwave communications, and were demonstrated to operate at data rates above 6 Gb/s. These are among the fastest 8-b MUX-DMUX circuits ever reported. Each contains about 600 transistors and consumes about 1.5 W. The pair provides features such as resettable timing, data framing, and clock recovery circuitry, and a built-in decision circuit on the DMUX. Emitter-coupled logic (ECL) compatible input/output (1/O) signals are available. The circuits were implemented with bi-level current mode logic (CML) and require a -5.2-V power supply and a +1-V bias for ECL compatibility     

A Method of Transformation from Symbolic Transfer Function to Active-RC Circuit by Admittance Matrix Expansion

Active-RC circuits containing 2-terminal linear passive elements and ideal transistors or operational amplifiers are derived from symbolic voltage or current transfer functions by admittance matrix transformations without any prior assumption concerning circuit architecture or topology. Since the method is a reversal of symbolic circuit analysis by Gaussian elimination applied to a circuit nodal admittance matrix, it can generate all circuits using the specified elements that possess a given symbolic transfer function. The method is useful for synthesis of low-order circuits, such as those used for cascade implementation, for deriving alternative circuits with the same transfer function as an existing circuit or for realizing unusual transfer functions, as may arise, for example, where a transfer function is required that contains specific tuning parameters     

Piecewise Nonlinear Approach to the Implementation of Nonlinear Current Transfer Functions

A piecewise nonlinear approach to the nonlinear circuit design has been proposed in this paper. It is to approximate a target nonlinear transfer function by a particular combination of selected nonlinear pieces. The pieces can be produced by one or more analog blocks involving nonlinear devices. This approach can be applied to design nonlinear circuits to implement various current transfer functions. By controlling the operation modes of the transistor pair in a simple current mirror, one can modulate the current transfer function in a radical or fine-tuning manner. It is thus possible for the same current mirror to generate very different nonlinear pieces in different sections of its input range. In order that the control is done automatically by the input current, or in other words, the operation of the transistors is made to be input-current-dependent in a controlled manner, a series structure of two transistors has been proposed to be incorporated in the current mirror. The dependency can be made different by placing the structure in different places of the current mirror and/or by making the two transistors complementary or not, which makes the variations of the nonlinear function. Several current mirrors have been designed. Each of them consists of a very small number of transistors and performs a defined nonlinear current transfer function. The circuits have been simulated with HSPICE to validate the functions. The successful results have been obtained and are presented in the paper.     

A Practical Tantalum Thin-Film Single-Sideband Demodulator Using RC Time-Varying and Active Networks

The thin-film circuit described in this paper is equivalent to a demodulator circuit containing an extremely selective filter ("sideband" filter). Such a filter would, in conventional form, require very high Q inductors or, as the Q requirement increases, the use of crystal or mechanical filters. At the frequency of operation of this circuit (1 MHz), demodulation with conventional filters would have to be accomplished in two or more stages so that the selectivity requirement can be decreased for each filter. Thin-film techniques restrict us to circuits using only resistors (R), capacitors (C), and added semiconductor devices (thin-film inductors are not considered here since their inductance values are too small). The current trend is to realize frequency selective networks (conventionally in LC form) as active RC networks. However, although the circuit described here incorporates such a network, the main selectivity requirement cannot be met by present-day active network techniques. The solution is found in the use of time-varying RC networks, i.e., by combining passive RC thin-film phase-shift networks with miniature transistors, used as electronic switches, in the form of so-called quadrature modulation circuits. The phase-shift networks, which in principle can be passive thin-film RC circuits, are in practice more easily realized as combinations of much simpler RC circuits with buffer amplifiers.     

Impact of anomalous short-channel MOS transistors on VLSI circuit reliability

In VLSI and ULSI circuits, a major reliability concern is that completed, fully functional, in-specification integrated circuits may contain one or more anomalous transistors with substantially closer source-to-drain spacing than the minimum-design-rule devices, and that such transistors will be more susceptible to degradation or failure due to hot-carrier effects, total-dose-radiation effects or other instabilities. A further concern is that such vulnerable transistors will not be detected during conventional electrical testing or during typical high-reliability integrated circuit burn-in procedures such as static or dynamic burn-in at 125°C, since hot carrier effects tend to anneal out at elevated temperatures, as well as having a negative temperature acceleration factor.Experimental studies have shown that fully functional nMOS transistors with shorter-than-normal channel lengths can have many orders of magnitude greater susceptibility to hot-electron-induced threshold voltage shifts, compared to transistors with minimum-design-rule dimensions of 1.2μm. Total-dose radiation tests showed that anomalous n-channel MOS transistors can have orders-of magnitude higher post-total-dose radiation leakage than nominal devices made by the same process.Several possible types of screening techniques that can be considered for detecting integrated circuits containing anomalous transistors are discussed, including a low-dissipation dynamic stress test at room temperature or at −55°C, with parts electrically characterized before and after the stress test. A large change (delta) of certain critical parameters would be used to predict future failure. Quiescent CMOS supply-current testing could also be used to detect the presence of anomalous transistors in some types of integrated circuits.     

Yield modeling based on in-line scanner defect sizing and acircuit's critical area

Wafers containing a large number of defects on any layer should be discarded in order to avoid the cost associated with processing wafers that are unlikely to yield. Normally decisions about scrapping wafers are based on defect counts. However, including the size of defects can improve the accuracy of such dispositions. If the size of defects is taken into account, critical area provides an estimate of the kill ratio associated with defects of a given size, where the critical area of a layer of a circuit is computed from a circuit's layout. In this paper, the accuracy of the sizing of defects by in-line scanners is analyzed. Then, the impact of defect sizing inaccuracy on estimates of layer yield is discussed, and a methodology to more accurately compute layer yield and kill ratios is presented, which calibrates for inaccuracy in defect sizing by in-line scanners     

Dynamic-type CMOS four-valued logic circuits

We first briefly introduce the various kinds of basic CMOS four-valued logic circuit that can be suitably employed for circuits with clock pulses. Using these, the design of multiple-valued MAX and MIN circuits with many inputs, each of which has two quaternary figures, are developed. It is shown that the number of MOS transistors required for these circuits can be reduced in comparison to binary circuits having equivalent functions. Successful simulation results using SPICE-2 for the circuit operations are given.     

Design of a novel fault-tolerant voter circuit for TMR implementation to improve reliability in digital circuits

Due to the shrinking of feature size and significant reduction in noise margins, nanoscale circuits have become more susceptible to manufacturing defects, interference from radiation and noise-related transient faults. Many of these faults are not permanent in nature but their occurrence can result in malfunctioning of circuits, either due to complexity of digital circuits or due to interaction with software. A fault-tolerant scheme such as triple-modular redundancy (TMR) is being implemented increasingly in digital systems. One of the drawbacks of this scheme is that the reliability of the voter circuit is assumed to be very high, which may not be true. Most of the implementation of digital circuits is in the form of integrated circuit; so all the circuit elements are fabricated with same technology and hence reliability of all the components is usually same. In this paper we are presenting a novel fault-tolerant voter circuit which itself can tolerate a fault and give error free output by improving the overall system’s reliability.     

An Analog Programmable Multidimensional Radial Basis Function Based Classifier

A compact analog programmable multidimensional radial basis function (RBF)-based classifier is demonstrated. The probability distribution of each feature in the templates is modeled by a Gaussian function that is approximately realized by the bell-shaped transfer characteristics of a proposed floating-gate circuit, which we term a floating-gate bump circuit. The maximum likelihood, the mean, and the variance of the distribution are stored in floating-gate transistors and are independently programmable. By cascading these floating-gate bump circuits, the overall transfer characteristics approximate a multivariate Gaussian function with a diagonal covariance matrix. An array of these circuits constitute a compact multidimensional RBF-based classifier that can easily implement a Gaussian mixture model. When followed by a winner-take-all circuit, the RBF-based classifier forms an analog vector quantizer. We use receiver operating characteristic curves and equal error rate to evaluate the performance of our RBF-based classifier as well as a resultant analog vector quantizer. We show that the classifier performance is comparable to that of digital counterparts. The proposed approach can be at least two orders of magnitude more power efficient than the digital microprocessors at the same task.     

Cyclostationary noise analysis of large RF circuits with multitoneexcitations

This paper introduces a new, efficient technique for analyzing noise in large RF circuits subjected to true multitone excitations. Noise statistics in such circuits are time-varying, hence cyclostationary stochastic processes, characterized by harmonic power spectral densities (HPSDs), are used to describe noise. HPSDs are used to devise a harmonic-balance-based noise algorithm with the property that required computational resources grow almost linearly with circuit size and nonlinearity. Device noises with arbitrary spectra (including thermal, shot, and flicker noises) are handled, and input and output correlations, as well as individual device contributions, can be calculated. HPSD-based analysis is also used to establish the nonintuitive result that bandpass filtering of cyclostationary noise can result in stationary noise. Results from the new method are validated against Monte Carlo simulations. A large RF integrated circuit (>300 nodes) driven by a local oscillator (LO) tone and a strong RF signal is analyzed in less than two hours. The analysis predicts correctly that the presence of the RF tone leads to noise folding, affecting the circuit's noise performance significantly     

Integrating Multiple Resistive Memory Devices on a Single Carbon Nanotube

Nano‐objects would be of great interest for the development of new types of electronic circuits if one could combine their nanometer scale with original functionalities beyond the conventional transistor action. However, the associated circuit architectures will have to handle the increasing variability and defect rate intrinsic to the nanoscale. In this context, there is a very fast growing interest for memory devices, and in particular resistive memory devices, used as building blocks in reconfigurable circuits tolerant to defects and variability. It was recently shown that optically gated carbon nanotube field effect transistors (OG‐CNTFETs) based on large assemblies of nanotubes covered by an organic photoconductive thin film can be operated as programmable resistors and thus used as artificial synapses in circuits with function‐learning capabilities. Here, the potential of such approach is evaluated in terms of scalability by integrating and addressing several individually programmable resistances on a single carbon nanotube. In addition, the charge storage mechanism can be controlled at a length scale smaller than the device length allowing to also program the direction in which the current flows. It thus demonstrates that a single nanotube section can combine all‐in‐one the properties of an analog resistive memory and of a rectifying diode with tunable polarity.     

Capacitance of semiconductor p-n junction space-charge layers: anoverview

The modeling of capacitance of p-n junction space-charge layers in semiconductor devices is discussed. First, previously developed models and methods are reviewed. Capacitance models developed recently by the authors that include mobile-carrier, nonquasi static, and multidimensional effects are then considered. These models yield more accurate device and circuit simulations for semiconductor integrated circuits. The emphasis is on diodes and bipolar transistors, but many concepts used apply as well to p-n junctions of metal-oxide-semiconductor field effect transistors. The review includes conventional homojunction devices (devices fabricated with a single semiconductor such as silicon) and the increasingly important heterojunction devices (devices fabricated with two or more semiconductors or a semiconductor having a spatially varying chemical composition such as gallium-aluminum-arsenide)     

Modeling the Random Parameters Effects in a Non-Split Model of Gate Oxide Short

This paper presents a new model for gate-to-channel GOS defects. The transistors used in digital cell library are usually designed with a minimum-size. This new model permits to handle minimal-length transistors allowing the simulation of GOS defects in realistic digital circuits. Based on the electrical analysis of the defect behavior, a comprehensive method for the model construction is detailed. It is shown that the behavior of the proposed model matches in a satisfactory way the behavior of a defective transistor including the random parameters of the defect.     

Statistical fault sampling

Computational requirements often discourage, or even prohibit, complete fault simulation of circuit designs having greater than 20000 single stuck-at faults. To circumvent this problem, statistical sampling methods have been proposed that provide fault coverage values within a small, predictable error range by simulating only a fraction of the circuit's total faults and using the result fault coverage value as an estimate of the fault coverage for the total circuit. As an introduction to the application of sampling methods to fault simulation of integrated circuits, the statistical theory behind these sampling methods and proposed augmentations of these methods for improving the precision of the sample fault coverage are presented. Various proposed sampling schemes are applied to example circuit designs, and the results are analyzed     

Performance of heterostructure FET's in LSI

This paper reports a comparative evaluation of circuits based on heterostructure field-effect transistors (HFET's) for delay, noise-margin and power dissipation in unloaded and loaded configurations. n-channel enhancement/depletion (E/D) circuits operating at 300 and 77 K and complementary circuits operating at 77 K are compared with respect to each other. The paper also shows that a modified short-channel MOSFET model gives good agreement with experimental behavior of the devices and is adequate for evaluation. Fan-in (FI) sensitivities of delay are much smaller than fan-out (FO) sensitivities of delay for E/D circuits because of capacitive effects. E/D circuit delays are more fan-out sensitive at 300 K than at 77 K because of lower current capability. The fan-in sensitivity of the delay of complementary circuits is larger and is comparable to that circuit's fan-out sensitivity. Under loaded conditions (FI is 3, FO is 3, capacitance is 0.1 pF) at 77 K, 0.5-µm gate length E/D structures show gate delays near 50 ps and 1.0-µm gate length show gate delays near 75 ps. The circuits at 300K exhibit a doubling of the gate delay. The complementary circuits offer, at 77 K, a performance of 70 ps at 0.5-µm gate length and 140 ps at 1.0-µm gate length. The significant performance improvements of complementary circuits with reduction of gate lengths to submicrometer dimensions occurs primarily due to reduction in the device capacitances and secondarily due to improvement of current characteristics. They demonstrate noise margins that are more than 50 percent better than their E/D counterpart along with lower power dissipations. The larger noise margin may be a significant advantage because the small logic swings require stringent parasitic resistance and threshold voltage control.