Bit-Error-Rate Performance Enhancement of All-Optical Clock Recovery at 42.66 Gb/s Using Passive Prefiltering

In this letter, we demonstrate the bit-error-rate (BER) performance enhancement of an all-optical clock recovery device at 42.66 Gb/s using a prefiltering operation in front of a self-pulsating semiconductor laser. The prefilter is composed of a simple passive fiber-Bragg-grating-based Fabry–PÉrot bandpass filter. The assessment is obtained thanks to BER measurement using a data remodulation technique.      

Flexible and Reconfigurable Time-Domain Demultiplexing of Optical Signals at 160 Gb/s

We present experimental results showing reconfigurable switching of four 40-Gb/s tributary channels in a 160-Gb/s data signal using Fourier-domain temporal pulse shaping and all-optical processing. Arbitrary combinations of multiple tributary channels are switched out of a high-speed data-modulated signal. The performance is characterized using a fast optical sampling oscilloscope and bit-error-rate measurements.     

6.25 Gb/s快速锁定时钟数据恢复电路

基于65 nm CMOS工艺,设计了一种6.25 Gb/s时钟数据恢复电路(CDR)。该CDR采用基于相位插值的双环结构和带有快速锁定算法的2阶积分环路实现,支持半速、全速、倍速3种工作模式。其抖动传输带宽在2~7 MHz范围内可调,相位插值精度为2.8°,DNL为1.1°,INL为5.6°。在频差为1.0×10-3时,其锁定速度较传统CDR提高了1倍以上,可应用于满足PCI-E、RAPIDIO协议、短期爆发性传输数据的高速串行接口领域。     

Detailed Theoretical and Experimental Characterization of 10 Gb/s Clock Recovery Using a Q-Switched Self-Pulsating Laser

A detailed characterization of the clock recovery properties of a self-pulsating, three-section distributed feedback laser is presented by directly comparing simulation and experimental results for the dependence of the RMS timing jitter of the recovered clock signal on important properties of the input signal. These properties include the duty cycle, peak power, extinction ratio, state-of-polarization, optical signal-to-noise ratio (OSNR), and waveform distortion due to residual group velocity dispersion and polarization mode dispersion. The permissible range for each of these is identified in terms of the RMS timing jitter of the recovered clock signal being less than 2 ps. In particular, the self-pulsating laser is effective for input signals degraded by amplified spontaneous emission noise as it provides this level of jitter performance for input OSNRs larger than 8.8 dB (0.1 nm noise bandwidth).     

10Gb/s CMOS时钟和数据恢复电路的设计

介绍了利用0.18μmCMOS工艺实现了应用于光纤传输系统SDHSTM-64级别的时钟和数据恢复电路。采用了电荷泵锁相环(CPPLL)结构,CPPLL中的鉴相器能够鉴测相位产生超前滞后逻辑,采样数据具有1∶2分接的功能。振荡器采用全集成LC压控振荡器,鉴相器采用半速率的结构。对应于10Gb/s的PRBS数据(231-1),恢复出的5GHz时钟的相位噪声为-112dBc/Hz@1MHz,同时10Gb/s的PRBS数据分接出两路5Gb/s数据。芯片面积仅为1.00mm×0.8mm,电源电压1.8V时功耗为158mW。     

2.5Gb/s0.35μm CMOS时钟恢复芯片

介绍了基于0．35μm CMOS工艺的2．5Gb／s时钟恢复电路设计。根据工艺特点，电路采用倍频器加全模拟镇相环蛄构。模拟表明，电路能工作在2．5Gb／s速率上，镇定范围达到100MHz，5V电压供电下功耗小于330mW。     

10 Gb/s 0.18 μm CMOS时钟恢复芯片

介绍了基于0．18μmCMOS工艺的10Gb／s时钟恢复电路的设计。核心电路采用预处理加简单锁相环的结构。模拟结果表明，该电路能工作在10GHz频率上，输入信号峰值0．4V时，同步范围可以达到270MHz，总功耗210mW。     

3.125Gb/s基于PS/PI型的时钟与数据恢复电路设计

基于标准0.18μmCMOS工艺,设计了一种全速率PS/PI型时钟与数据恢复(CDR)电路。该电路主要由bang-bang型鉴相器、数字控制模块、分接器、相位选择器以及相位插值器等模块构成。根据本CDR的特点,提出了一种在分接器后对超前、滞后信息进行统计比较得到一组低速信号来解决高速模拟电路和低速数字电路之间的接口问题。     

2.5Gb/s Ga As MESFET定时判决电路

设计了 2 .5 Gb/ s光纤通信用耗尽型 Ga As MESFET定时判决电路 .通过 SPICE模拟表明恢复的时钟频率达2 .5 GHz,判决电路传输速率达 2 .5 Gb/ s.实验证明经时钟信号抽样后判决电路可产生正确的数字信号 ,传输速率达 2 .5 Gb/ s     

2.5Gb/s GaAs MESFET定时判决电路

设计了2.5Gb/s光纤通信用耗尽型GaAs MESFET定时判决电路.通过SPICE模拟表明恢复的时钟频率达2.5GHz,判决电路传输速率达2.5Gb/s.实验证明经时钟信号抽样后判决电路可产生正确的数字信号,传输速率达2.5Gb/s.     

160 Gb/s-Based Field Transmission Experiments Using Polarizer-Based PMD Compensator With Optical Power Monitor

Higher bit-rate transmission is attractive for improving network resource efficiency and reducing the complexity of network management in future transmission systems. However, chromatic dispersion and polarization mode dispersion (PMD) are one of the most serious impairments. In particular, PMD should be compensated for dynamically because it changes rapidly according to environmental variations such as temperature change and mechanical vibration. Therefore, an adaptive PMD compensator is indispensable for higher bit-rate transmission systems. In this paper, we employed a simple and bit-rate independent PMD compensator based on a polarizer with an optical power monitoring scheme in 160 Gb/s-based field experiments. By using the PMD compensator, the single channel transmission of a 160 Gb/s return-to-zero differential phase-shift-keying modulation signal over an installed fiber link with buried and aerial cable routes was successfully achieved. Approximately 1 dB of Q-factor was improved by using the PMD compensator when PMD impairment was maximized. Through these experiments, the effectiveness of the PMD compensator in the higher bit-rate transmission systems was confirmed in the field environment. Furthermore, single-polarization 8times160 Gb/s wavelength division multiplexing transmission over the installed 200 km standard single mode fiber without polarization demultiplexing was successfully achieved by using the simple PMD compensator.     

超100Gb/秒的光OFDM在光长度系统的传输

100 G Ethernet is considered to become the next generation Ethernet standard for IP networks. Typical 100 Gb/s transmission systems and their performance are presented. Comparision and analysis for 100 Gb/s transmission systems have been discussed. It is demonstrated that optical OFDM can be used in future 100 Gb/s/ch and long-haul system.     

2.5 Gb/s PS/PI型半速率时钟数据恢复电路设计

采用标准0.18 μm CMOS工艺,设计了一种相位选择(PS)/相位插值(PI)型半速率时钟数据恢复电路。该电路主要由半速率Bang-Bang鉴相器、改进型PS/PI电路、数字滤波器和数字控制器等模块构成。改进型PS/PI电路通过两个相位选择器和两个相位插值器实现正交时钟的产生,相较于传统结构,减少了两个相位选择器,降低了复杂度和功耗。数字滤波器和数字控制器通过Verilog代码自动综合生成,降低了设计难度。Cadence仿真结果表明,输入2.5 Gb/s伪随机数据时,电路在1.8 μs时锁定,锁定后恢复出的时钟和数据峰峰值抖动分别为17.71 ps和17.89 ps,可以满足短距离I/O接口通信的需求。     

CMOS2.5 Gb/s时钟恢复电路设计

设计采用0.35μm CMOS工艺来实现一款CMOS2.5 Gb/s时钟恢复电路。由于0.35μm CMOS工艺的限制,采用了预处理电路加锁相环的电路结构。这种电路结构有利于单片集成且工作速度高。预处理器主要有延迟单元、乘法器和窄带滤波电路构成,可以从NRZ数据中得到时钟信号。锁相环采用二阶的模拟锁相环结构,鉴相器采用Gilbert乘法器,环路滤波器采用无源滤波器,VCO采用3级环形振荡器。     

一种5 Gb/s双信道并行时钟数据恢复电路

基于0.18 μm CMOS工艺,设计了一种双信道并行时钟数据恢复(CDR)电路,它由1个锁相环(PLL)型CDR和1个相位选择/相位插值(PS/PI)型CDR结合实现。与传统的并行CDR相比,该CDR电路不需要本地参考时钟。PLL型CDR中环形压控振荡器的延迟单元采用电感峰化技术,拓展了带宽,实现了较高的振荡频率;电荷泵采用自举基准和运放,改善了充放电电流匹配。PS/PI型CDR中Bang-Bang型鉴相器结构简单,具有较好的鉴相功能;PS/PI电路比传统结构少2个相位选择器。仿真结果表明,当输入并行数据速率为5 Gb/s时,恢复出的2组时钟与数据的峰峰抖动值分别为6.1 ps,8.1 ps和8.7 ps,11.2 ps。电路核心模块的功耗为172.4 mW,整体电路版图面积为(1.7×1.585) mm²。     

2.5Gb/s 0.18μm CMOS时钟数据恢复电路

采用TSMC公司标准的0．18μm CMOS工艺，设计并实现了一个全集成的2．5Gb／s时钟数据恢复电路．时钟恢复由一个锁相环实现．通过使用一个动态的鉴频鉴相器，优化了相位噪声性能．恢复出2．5GHz时钟信号的均方抖动为2．4ps，单边带相位噪声在10kHz频偏处为-111dBc／Hz．恢复出2．5Gb／s数据的均方抖动为3．3ps．芯片的功耗仅为120mW．     

2.5Gb/s 0.18μm CMOS时钟数据恢复电路

采用TSMC公司标准的0.18μm CMOS工艺,设计并实现了一个全集成的2.5Gb/s时钟数据恢复电路.时钟恢复由一个锁相环实现.通过使用一个动态的鉴频鉴相器,优化了相位噪声性能.恢复出2.5GHz时钟信号的均方抖动为2.4ps,单边带相位噪声在10kHz频偏处为-111dBc/Hz.恢复出2.5Gb/s数据的均方抖动为3.3ps.芯片的功耗仅为120mW.     

2.5Gb/s Monolithic IC of Clock Recovery,Data Decision，and 1∶4 Demultiplexer

A high integrated monolithic IC，with functions of clock recovery,data decision,and 1∶4 demultiplexer，is implemented in 0.25μm CMOS process for 2.5Gb/s fiberoptic communications.The recovered and frequency divided 625MHz clock has a phase noise of －106.26dBc/Hz at 100kHz offset in response to a 2.5Gb/s PRBS input data (2~31-1).The 2.5Gb/s PRBS data are demultiplexed to four 625Mb/s data.The 0.97mm×0.97mm IC consumes 550mW under a single 3.3V power supply (not including output buffers).     

A 40 Gb/s CMOS Serial-Link Receiver With Adaptive Equalization and Clock/Data Recovery

This paper presents a 40 Gb/s serial-link receiver including an adaptive equalizer and a CDR circuit. A parallel-path equalizing filter is used to compensate the high-frequency loss in copper cables. The adaptation is performed by only varying the gain in the high-pass path, which allows a single loop for proper control and completely removes the RC filters used for separately extracting the high- and low-frequency contents of the signal. A full-rate bang-bang phase detector with only five latches is proposed in the following CDR circuit. Minimizing the number of latches saves the power consumption and the area occupied by inductors. The performance is also improved by avoiding complicated routing of high-frequency signals. The receiver is able to recover 40 Gb/s data passing through a 4 m cable with 10 dB loss at 20 GHz. For an input PRBS of 2 $^{7}-$1, the recovered clock jitter is 0.3 ps$_{rm rms}$ and 4.3 ps$_{rm pp}$. The retimed data exhibits 500 mV $_{rm pp}$ output swing and 9.6 ps$_{rm pp}$ jitter with ${hbox{BER}}≪ 10^{-12}$ . Fabricated in 90 nm CMOS technology, the receiver consumes 115 mW , of which 58 mW is dissipated in the equalizer and 57 mW in the CDR.      

2.5Gb/s单片时钟恢复数据判决与1:4分接集成电路的设计

用0.25μm CMOS工艺实现一个复杂的高集成度的2.5Gb/s单片时钟数据恢复与1:4分接集成电路.对应于2.5Gb/s的PRBS数据(231-1),恢复并分频后的625MHz时钟的相位噪声为-106.26dBc/Hz@100kHz,同时2.5Gb/s的PRBS数据分接出4路625Mb/s数据.芯片面积仅为0.97mm×0.97mm,电源电压3.3V时核心功耗为550mW.