CMOS Quadrature VCO Implemented With Two First-Harmonic Injection-Locked Oscillators

This letter presents a new quadrature voltage-controlled oscillator (QVCO). The LC-tank QVCO consists of two first-harmonic injection-locked oscillators (ILOs). The outputs of one ILO are injected to the gates of the tail transistors on the other ILO and vice versa so as to force the two ILOs operate in quadrature. The proposed CMOS QVCO has been implemented with the TSMC 0.18 mum CMOS technology and the die area is 0.582 times 0.972 mm². At the supply voltage of 1.0 V, the total power consumption is 8.0 mW. The free-running frequency of the QVCO is tunable from 5.31 GHz to 5.75 GHz as the tuning voltage is varied from 0.0 V to 1.0 V. The measured phase noise at 1 MHz offset is -120.01 dBc/Hz at the oscillation frequency of 5.31 GHz and the figure of merit (FOM) of the proposed QVCO is about -185.48 dBc/Hz.     

新型CMOS正交压控振荡器设计

通过对两个相同的LC振荡器进行交差耦合,用耦合系数来控制输出频率,设计了一种新型精准正交正弦波压控振荡器.由于其频率调节方式不再依赖于变容管,大大增加了输出频率的调节范围.基于TSMC18rf工艺库,采用Cadence的Spectre工具对电路进行仿真.在VDD=1.8V下,频率覆盖了1.78GHz到4.03GHz,可调控范围约为77%,1MHz处相位噪声约为-104dB/Hz.     

A 5 GHz Differential Colpitts CMOS VCO Using the Bottom PMOS Cross-Coupled Current Source

A low phase noise differential Colpitts voltage- controlled oscillator (VCO) with the bottom series PMOS cross-coupled current source is presented. The core Colpitts VCO adopts a pair of PMOS as the biased current source at the bottom, instead of a conventional NMOS topology, to achieve a better phase noise performance as the PMOS has lower flicker and white noise than those of NMOS and the output power spectral density of PMOS operated in bottom-biased type is further less than that in top-biased one in the same power consumption. The fabricated VCO operates from 4.9 to 5.46 GHz with 10.6% tuning range when the power consumption is below 6.4 mW with a supply voltage of 1.8 V. The measured phase noise at 100 kHz offset is $-$100.3 dBc/Hz at 5.46 GHz and achieves a good FOM performance of $-$187 dBc/Hz.      

5-GHz Low-Phase Noise CMOS Quadrature VCO

A 5-GHz low-phase noise CMOS quadrature voltage controlled oscillator (QVCO) is described. Two differential pairs (one for negative gm generation and the other one for the coupling input) of each resonator have separate biasing transistors which are switched on and off by the coupling input of each resonator. The proposed QVCO implemented in a 0.13-mum CMOS technology shows 17-dB phase noise improvement from a conventional QVCO with constant tail current sources while the two QVCOs consume the same power of 5.28mW. The phase noise of the proposed QVCO is measured to be -102dBc/Hz and -117dBc/Hz at 100KHz and 1-MHz offset, respectively     

A 1-V 17-GHz 5-mW CMOS Quadrature VCO Based on Transformer Coupling

A 1-V 17-GHz 5-mW quadrature voltage-controlled oscillator (QVCO) based on transformer coupling is presented. Transformer coupling between two LC tank oscillators is proposed to achieve quadrature outputs with improved performance in terms of high frequency, wide tuning range, low phase noise, and low power as compared to existing active-coupling QVCOs. Implemented in a 0.18-mum CMOS process, the proposed QVCO measures a frequency tuning range of 16.5% at 17 GHz and phase noise of -110 dBc/Hz at 1 MHz offset while consuming 5 mA from a 1-V power supply and occupying a core area of 0.37 mm².     

An Amplitude-Balanced Current-Reused CMOS VCO Using Spontaneous Transconductance Match Technique

A 3.5 GHz, 0.18 $mu{rm m}$ CMOS current-reused voltage-controlled oscillator (VCO) with very high amplitude balance is presented. While the current-reused VCO can dramatically save dc power consumption, it has the drawback of output amplitude imbalance resulting from the asymmetric circuit structure. A spontaneous transconductance match (STM) technique is proposed to balance the transconductance of nMOS and pMOS transistors by the imbalance-induced voltage at the center-tapped point of the tank inductor. This transconductance match takes place spontaneously with the occurrence of signal imbalance such that imbalances can be instantly eliminated. The measured amplitude imbalance ratio is less than 0.7% over the entire tuning range of 2.93 to 3.62 GHz, significantly reduced from 3% of the VCO without STM. The power consumption is as low as 1.65 mW from a 1.5 V supply. The phase noise is $-$ 122 dBc/Hz at 1 MHz offset. A very high FOM of $-$195.7 dBc/Hz is achieved.      

A 0.22 V Quadrature VCO in 90 nm CMOS Process

This letter presents an ultra-low voltage quadrature voltage-controlled oscillator (QVCO). The LC-tank QVCO consists of two low-voltage voltage-controlled oscillators (VCOs) with the body dc biased at the drain bias through a resistor. The superharmonic and back-gate coupling techniques are used to couple two differential VCOs to run in quadrature. The proposed CMOS QVCO has been implemented with the UMC 90 nm CMOS technology and the die area is 0.827 $, times ,$0.913 mm $^{2}$. At the supply voltage of 0.22 V, the total power consumption is 0.33 mW. The free-running frequency of the QVCO is tunable from 3.42 to 3.60 GHz as the tuning voltage is varied from 0.0 to 0.3 V. The measured phase noise at 1 MHz offset is ${-}112.97$ dBc/Hz at the oscillation frequency of 3.55 GHz and the figure of merit (FOM) of the proposed QVCO is about ${-}188.79$ dBc/Hz.      

A Low-Voltage Quadrature CMOS VCO Based on Voltage-Voltage Feedback Topology

A novel low-voltage quadrature voltage-controlled oscillator (QVCO) with voltage feedback to the input gate of a switching amplifier is proposed and implemented using the standard TSMC 0.18-mum CMOS 1P6M process. The proposed circuit topology is made up of two low-voltage LC-tank VCOs, where the coupled QVCO is obtained using the transformer coupling technique. At the 0.7-V supply voltage, the output phase noise of the VCO is -124.9 dBc/Hz at 1-MHz offset frequency from the carrier frequency of 2.4GHz, and the figure of merit is -185.35dBc/Hz. Total power consumption is 5.18 mW. Tuning range is about 135 MHz while the control voltage was tuned from 0 to 0.7V     

A novel complementary Colpitts differential CMOS VCO with low phase noise performance

A low phase noise Ka-band CMOS voltage-controlled oscillator is proposed in this paper. A new complementary Colpitts structure was adopted in a 0.18-μm CMOS process to achieve differential-ended outputs, low phase-noise performance, and low-power consumption. The designed VCO oscillates from 29.8 to 30 GHz with 200 MHz tuning range. The measured phase noise at 1-MHz offset is −109 dBc/Hz at 30 GHz and −105.5 dBc/Hz at 29.8 GHz. The power consumption of VCO is only 27 mW. In addition, compared with the published papers, the proposed CMOS VCO achieves the best figure of merit (FOM) of −185 dB at 29.95-GHz band.     

A 1 V 2.2 mW 7 GHz CMOS Quadrature VCO Using Current-Reuse and Cross-Coupled Transformer-Feedback Technology

A current-reused quadrature voltage-controlled oscillator (CR-QVCO) is proposed with the cross-coupled transformer-feedback technology for the quadrature signal generation. This CR-QVCO has the advantages of low-voltage/low-power operation with an adequate phase noise performance. A compact differential three-port transformer, in which two half-circle secondary coils are carefully designed to optimize the effective turn ratio and the coupling factor, is newly constructed to satisfy the need of signal coupling and to save the area consumption simultaneously. The quadrature oscillator providing a center frequency of 7.128 GHz for the ultrawideband (UWB) frequency synthesizer use is demonstrated in a 0.18 mum RF CMOS technology. The oscillator core dissipates 2.2 mW from a 1 V supply and occupies an area of 0.48 mm². A tuning range of 330 MHz (with a maximum control voltage of 1.8 V) can be achieved to stand the frequency shift caused by the process variation. The measured phase noise is -111.2 dBc/Hz at 1 MHz offset from the center frequency. The IQ phase error shown is less than 2deg. The calculated figure-of-merit (FOM) is 184.8 dB.     

CMOS VCO and LNA Using Tuned-Input Tuned-Output Circuits

A tuned-input tuned-output (TITO) VCO utilizes two resonant-tanks to achieve a low measured phase noise of 130.5 dBc/Hz @ 1 MHz offset from 2.5 GHz center frequency. Improvement in phase noise is achieved with comparable power consumption and tuning range compared to a cross-coupled VCO topology. A TITO cell similar to that in the VCO is used as a common-source amplifier in a current-reuse configuration cascaded with a -boosted common-gate amplifier to realize a high gain (20 dB), low power (2.7 mW) LNA. A technique to improve the linearity of the current-reuse LNA is also presented.     

Analysis and Design of a CMOS Phase-Tunable Injection-Coupled LC Quadrature VCO (PTIC-QVCO)

This paper presents the design, analysis, and characterization of a low-power, low-phase-noise, phase-tunable injection-coupled LC quadrature oscillator (PTIC-QVCO). Two LC VCOs are superharmonically coupled in quadrature phase via a frequency doubler that injects a synchronizing signal at the common source node of the negative transconductor stage. Conceptual and analytical models of the circuit are introduced to derive the conditions for quadrature operation and examine the circuit parameters affecting the phase imbalance due to mismatched VCOs. Additionally, a tunable tail filter (TTF) is incorporated to calibrate the residual quadrature imbalance in presence of a 3-$sigma $ variation in the device parameters and drive the oscillator to its optimum phase noise performance. To validate the proposed approach, measurements have been carried out on a 9 GHz prototype implemented in a 0.18 $muhbox{m}$ RF CMOS process. With core current consumption of 5 mA at 1.8 V supply voltage, the circuit achieves a measured phase noise figure-of-merit ranging from 177.3 to 182.6 dBc/Hz at 3 MHz offset along the 9.0 to 9.6 GHz frequency tuning range. Quadrature phase correction of $pm 11 ^{0}$ at 9 GHz is demonstrated.      

A Low Phase Noise LC VCO in 65 nm CMOS Process Using Rectangular Switching Technique

A low phase noise and low power LC voltage-controlled oscillator (VCO) has been designed using a 65-nm CMOS process. The phase noise is minimized by switching the differential core using a rectangular shaped voltage waveform, which is formed by a harmonic tuned LC tank assisted by a g_m3 boosting circuit. The g_m3 boosting circuit effectively maximizes the slope at the zero crossing point and reduces the transition time in which the switching transistor is operated at the triode region. The rectangular switching technique has improved the phase noise of the oscillator by 10 dB. The 450 mum times 540 mum chip consumes 4.34 mW. The proposed VCO has phase noises of -83.3, -110.7, and -131.8 dBc/Hz at 10 KHz, 100 KHz, and 1 MHz offset frequencies, respectively, from the 1.6-GHz carrier frequency.     

A 56–65 GHz Injection-Locked Frequency Tripler With Quadrature Outputs in 90-nm CMOS

A sub-harmonic injection-locked tripler multiplies a 20-GHz differential input to 60-GHz quadrature (I/Q) output signals. The tripler consists of a two-stage ring oscillator driven by a single-stage polyphase input filter and 50-$Omega$ I and Q-signal output buffers. Each gain stage incorporates a hard limiter to triple the input frequency for injection locking and a negative resistance cell with two positive feedback loops to increase gain. Regenerative peaking is also used to optimize the gain/bandwidth performance of the 50-$Omega$ output buffers. Fabricated in 90-nm CMOS, the tripler has a free-running frequency of 60.6 GHz. From a 0-dBm RF source, the measured output lock range is 56.5–64.5 GHz, and the measured phase noise penalty is 9.2 $ pm 1~$dB with respect to a 20.2-GHz input. The $0.3times 0.3~ hbox{mm}^{2}$ tripler (including passives) consumes 9.6 mW, while the output buffers consume 14.2 mW, all from a 1-V supply.      

A K-Band CMOS Quadrature Frequency Tripler Using Sub-Harmonic Mixer

A low-power frequency tripler is designed by using the sub-harmonic mixer configuration for K-band applications. The proposed circuit features quadrature signal generation, applicable to LO signal synthesis in millimeter-wave wireless transceivers. It achieves conversion gain of $-$5.7 dB at the output frequency of 21 GHz. Implemented in a 0.18 $mu{rm m}$ CMOS technology, the circuit consumes power of 7.5 mW with 1.5 V supply voltage. The entire die occupies an area of $1000times 1050 mu{rm m}^{2}$.      

Low Phase Noise Self-Switched Biasing CMOS LC Quadrature VCO

A self-switched biasing quadrature voltage-controlled oscillator (VCO) is presented. It is implemented by directly injecting the oscillation signal of one VCO core into the other VCO core through the divided tail current sources without additional active devices for coupling. The proposed coupling structure automatically switches the NMOS field-effect transistors used in VCO cores and current sources from strong inversion to accumulation. Since the deep switching of MOSFETs was reported to physically reduce flicker noise, the proposed quadrature VCO (QVCO) is expected to improve the phase noise performance, which is confirmed experimentally. The designed QVCO using 0.18- $mu{hbox{m}}$ CMOS technology operates from 1.86 to 2.2 GHz with a 17% frequency tuning range. The measured phase noise is from $-$ 129.1 to $-$ 134.5 dBc/Hz at a 1-MHz offset, which is really close to ideal simulation results with the NMOS model disabling the flicker noise components. The average measured phase noise is 7.2 dB below the simulated one with a flicker noise model, which verifies the physical reduction of flicker noise by deep switching of the MOSFET. The phase noise figure-of-merit ranges from 179 to 185 over the entire tuning range. The QVCO dissipates 20 mA from a 1.8-V supply.      

A Millimeter-Wave CMOS LC-Tank VCO With an Admittance-Transforming Technique

A novel circuit topology suitable for millimeter-wave voltage-controlled oscillators (VCOs) is presented. With the admittance-transforming technique, the proposed VCO can operate at a frequency close to the f_max of the transistors while maintaining remarkable circuit performance in terms of phase noise, tuning range, and output power. Using a standard micrometer CMOS process, a U-band VCO is implemented for demonstration. The fabricated circuit exhibits a frequency tuning range of 1.1 GHz in the vicinity of 50 GHz. The measured output power and phase noise at 1-MHz offset are -11 dBm and -101 dBc/Hz, respectively. Operated at a supply voltage of 1.8 V, the VCO core consumes a DC power of 45 mW.     

Extraction Technique of Differential Second Harmonic Output in CMOS LC VCO

A technique to extract differential second harmonic output signals in a CMOS LC voltage-controlled oscillator (VCO) is introduced. In a cross-coupled n-type field effect transistor (NFET) and p-channel field effect transistor (PFET) VCO topology, the upper and lower common source nodes of the FET pairs can provide well-balanced differential second harmonic output by resonating the impedances at the common source nodes and operating the VCO in the voltage-limited regime. The idea is verified experimentally by implementing a 5.6-GHz CMOS VCO having a tunable impedance element at the common source node. The error signal power between the differential signals is measured to be -70dBm when properly tuned, which indicates almost perfect differentiality of the second harmonic output signals     

基于电流折叠技术的CMOS全差分VCO设计

针对目前通信系统应用上对压控振荡器的片上集成、宽调谐、调幅、启动特性和功耗等提出的综合性要求,分析和设计了一种压控调频调幅振荡器,其延迟单元采用全差分结构,以消除共模噪声和增加延迟控制的灵活性;并利用交叉耦合的差分负阻和电流折叠的正反馈技术进行频率调谐,使之在宽频范围内具有常数振荡幅度.采用0.5 μm CMOS工艺进行spice仿真,结果表明振荡器具有34～197 MHz的宽调谐范围,并能保持常数振荡幅度,功耗仅10mw,启动时间仅52 ns.系统还能在0.5～2.0 V范围内进行良好的线性调幅.