A 46-ns 1-Mbit CMOS SRAM

A 1-Mb (128 K×8-bit) CMOS static RAM (SRAM) with high-resistivity load cell has been developed with 0.8-μm CMOS process technology. Standby power is 25 μW, active power 80 mW at 1-MHz WRITE operation, and access time 46 ns. The SRAM uses a PMOS bit-line DC load to reduce power dissipation in the WRITE cycle, and has a four-block access mode to reduce the testing time. A small 4.8×8.5-μm² cell has been realized by triple-polysilicon layers. The grounded second polysilicon layer increases cell capacitance and suppresses α-particle-induced soft errors. The chip size is 7.6×12.4 mm²     

An experimental 295 MHz CMOS 4K×256 SRAM using bidirectionalread/write shared sense amps and self-timed pulsed word-linedrivers

An experimental 4 K word by 256 b CMOS synchronous SRAM employing read/write shared sense amplifiers and self-timed pulsed word-lines is described. The read/write shared sense amplifier allows the RAM to have 256 I/Os and the self-timed pulsed word-line scheme reduces power consumption. Fully differential I/O buses, laid out in fourth metal over the memory cell arrays, use a 0.3 V differential swing. The SRAM is fabricated in a 0.35 μm four-layer metal CMOS process employing a 6-T SRAM cell measuring 5.2 μm×6.6 μm. The die measures 13.22 mm×4.80 mm. The SRAM operates at 295 MHz with a 3.3 V supply, achieving a bandwidth of 9.44 Gbyte/s     

A 3.8-ns 16 K BiCMOS SRAM

A 2 K×8-b, ECL 100 K compatible BiCMOS SRAM with 3.8-ns (-4.5 V, 60°) address access time is described. The precisely controlled bit-line voltage swing (60 mV), a current sensing method, and optimized ECL decoding circuits permit a reliable and fast readout operation. The SRAM features an on-chip write pulse generator, latches for input and output bits, and a full six-transistor CMOS cell array. Power dissipation is approximately 2 W, and the chip size is 3.9×5.9 mm². The SRAM was based on 1.2-μm BiCMOS, using double-metal, triple-polysilicon, and self-aligned bipolar transistors     

A 6-ns 4-Mb CMOS SRAM with offset-voltage-insensitive current senseamplifiers

A 4-Mb CMOS SRAM with 3.84 μm² TFT load cells is fabricated using 0.25-μm CMOS technology and achieves an address access time of 6 ns at a supply voltage of 2.7 V. The use of a current sense amplifier that is insensitive to its offset voltage enables the fast access time. A boosted cell array architecture allows low voltage operation of fast SRAM's using TFT load cells     

GaAs Schmitt trigger memory cell design

A novel GaAs five-transistor static memory cell derived from a Schmitt trigger is proposed. The memory cell overcomes MESFET subthreshold leakage loss by using a self ground-shifting technique which limits the leakage current flow to the cell. Compared with conventional GaAs SRAM cells, it offers small area and as well as fast read/write cycles. A 1 Kb prototype implemented in 1 μm nonself-aligned GaAs MESFET technology exhibited read and write access times of the order of 2.0 ns     

An 8 ns 4 Mb serial access memory

A new architecture for serial access memory is described that enables a static random access memory (SRAM) to operate in a serial access mode. The design target is to access all memory address serially from any starting address with an access time of less than 10 ns. This can be done by all initializing procedure and three new circuit techniques. The initializing procedure is introduced to start the serial operation at an arbitrary memory address. Three circuit techniques eliminate extra delay time caused by an internal addressing of column lines, sense amplifiers, word lines, and memory cell blocks. This architecture was successfully implemented in a 4-Mb CMOS SRAM using a 0.6 μm CMOS process technology. The measured serial access time was 8 ns at a single power supply voltage of 3.3 V     

A 250-MHz skewed-clock pipelined data buffer

A synchronous dual-port memory employing a three-transistor (3T) dynamic cell has been designed for use as a high throughput embedded data buffer in digital switching and signal processing applications. Skewed-clock pipelining is used to achieve operation at frequencies as high as 250 MHz with a low register element count. The 3T cell provides separate read and write access ports while occupying less than half the area of a conventional dual-port SRAM cell. On-chip Hamming error correction coding (ECC) is used to enhance the fault tolerance of the memory, A 25-kb experimental prototype has been integrated in a 0.8-μm CMOS technology; it occupies a die area of 3800 μm×1600 μm and dissipates 420 mW while operating at 250 MHz     

An Experimental 0.8 V 256‐kbit SRAM Macro with Boosted Cell Array Scheme

This work presents a low‐voltage static random access memory (SRAM) technique based on a dual‐boosted cell array. For each read/write cycle, the wordline and cell power node of selected SRAM cells are boosted into two different voltage levels. This technique enhances the read static noise margin to a sufficient level without an increase in cell size. It also improves the SRAM circuit speed due to an increase in the cell read‐out current. A 0.18 µm CMOS 256‐kbit SRAM macro is fabricated with the proposed technique, which demonstrates 0.8 V operation with 50 MHz while consuming 65 µW/MHz. It also demonstrates an 87% bit error rate reduction while operating with a 43% higher clock frequency compared with that of conventional SRAM.     

Fast-access BiCMOS SRAM architecture with a VSSgenerator

A high-speed BiCMOS ECL (emitter coupled logic) interface SRAM (static RAM) architecture is described. To obtain high-speed operation for scaled-down devices, such as MOSFETs with a feature size of 0.8 μm or less and with a small MOS level, a new SRAM architecture featuring all-bipolar peripheral circuits and CMOS memory cells with V_SS generator has been developed. Two key circuits, a V_SS generator and a current switch level converter, are described in detail. These circuits reduce the external supply voltage to the internal MOS level, thus permitting high-speed SRAM operation. To demonstrate the effectiveness of the concept, a 256 kb SRAM with an address access time of 5 ns is described     

Low-power embedded SRAM with the current-mode write technique

In the traditional current-mode SRAMs, only the read operation is performed in the current mode. In this paper, we propose to use the current-mode technique in both the read and write operations. Due to the current mode operation, voltage swings at bit lines and data lines are kept very small during both read and write. Then, the ac power dissipation of bit lines and data lines, which is proportional to the voltage swing, can be significantly saved. A new current-mode 128×8 SRAM has been designed based on a 0.6 μm CMOS technology, and the new SRAM consumes only 30% of the power of an SRAM with current-mode read but voltage mode write operations. Besides a test chip for the new SRAM, it has also been embedded in an 8-bit 1.1-controller. Experimental results show good agreement with the simulation results and prove the feasibility of the new technique     

A 12-ns ECL I/O 256 K×1-bit SRAM using a 1-μm BiCMOStechnology

An ECL (emitter-coupled-logic) I/O 256K×1-bit SRAM (static random-access memory) has been developed using a 1-μm BiCMOS technology. The double-level-poly, double-level-metal process produces 0.8-μm CMOS effective gate lengths and polysilicon emitter bipolar transistors. A zero-DC-power ECL-to-CMOS translation scheme has been implemented to interface the ECL periphery circuits to the CMOS decode and NMOS matrix. Low-impedance bit-line loads were used to minimize read access time. Minimization of bit-line recovery time after a write cycle is achieved through the use of a bipolar/CMOS write recovery method. Full-die simulations were performed using HSPICE on a CRAY-1     

An Ultra-Low-Power 9T SRAM Cell Based on Threshold Voltage Techniques

This paper presents a new nine-transistor (9T) SRAM cell operating in the subthreshold region. In the proposed 9T SRAM cell, a suitable read operation is provided by suppressing the drain-induced barrier lowering effect and controlling the body–source voltage dynamically. Proper usage of low-threshold voltage (L-\(V_{\mathrm{t}}\)) transistors in the proposed design helps to reduce the read access time and enhance the reliability in the subthreshold region. In the proposed cell, a common bit-line is used in the read and write operations. This design leads to a larger write margin without using extra circuits. The simulation results at 90 nm CMOS technology demonstrate a qualified performance of the proposed SRAM cell in terms of power dissipation, power–delay product, write margin, read access time and sensitivity to process, voltage and temperature variations as compared to the other most efficient low-voltage SRAM cells previously presented in the literature.     

A sub-40-ns chain FRAM architecture with 7-ns cell-plate-line drive

A nonvolatile chain FRAM adopting a new cell-plate-line drive technique was demonstrated. Two key circuit techniques, a two-way metal cell-plate line and a cell-plate line shared with 16 cells, reduce cell-plate-line delay to 7 ns and reduce plate drive area to 1/5. The total cell-plate-line delay, including cell transistor delay due to eight cells in series, is reduced to 15 μs, in contrast to 30-100-ns delay of the conventional FRAM. The die size is reduced to 86% that of the conventional FRAM by reduction of the plate driver area and sense amplifier area, assuming the same memory cell size. A prototype 16-kb chain FRAM chip was fabricated using 0.5 μm rule one-polycide and two-metal CMOS process. The memory cell size was 13.26 μm² using a 3.24-μm² capacitor. Thanks to the fast cell-plate-line drive, the chain FRAM test chip has achieved the fastest random access time, 37 ns, and read/write cycle time, 80 ns, at 3.3 V so far reported. The chain FRAM has also realized V_{dd min} of 2.3 V and 10¹⁰ read/write cycles     

A 16-Mb CMOS SRAM with a 2.3-μm2 single-bit-linememory cell

A novel architecture that enables fast write/read in poly-PMOS load or high-resistance polyload single-bit-line cells is developed. The architecture for write uses alternate twin word activation (ATWA) with bit-line pulsing. A dummy cell is used to obtain a reference voltage for reading. An excellent balance between a normal cell signal line and a dummy cell signal line is attained using balanced common data-line architecture. A newly developed self-bias-control (SBC) sense amplifier provides excellent stability and fast sensing performance for input voltages close to V_CC at a low power supply of 2.5 V. The single-bit-line architecture is incorporated in a 16-Mb SRAM, which was fabricated using 0.25-μm CMOS technology. The proposed single-bit-line architecture reduces the cell area to 2.3-μm² , which is two-thirds of a conventional two-bit-line cell with the same processes. The 16-Mb SRAM, a test chip for a 64-Mb SRAM, shows a 15-ns address access time and a 20-ns cycle time     

A 5-ns 1-Mb ECL BiCMOS SRAM

A 1-Mword×1-b ECL (emitter coupled logic) 10 K I/O (input/output) compatible SRAM (static random-access memory) with 5-ns typical address access time has been developed using double-level poly-Si, double-level metal, 0.8-μm BiCMOS technology. To achieve 5-ns address access time, high-speed X-address decoding circuits with wired-OR predecoders and ECL-to-CMOS voltage-level converters with partial address decoding function and sensing circuits with small differential signal voltage swing were developed. The die and memory cell sizes are 16.8 mm×6.7 mm and 8.5 μm×5.3 μm, respectively. The active power is 1 W at 100-MHz operation     

A 7.5-ns 32 K×8 CMOS SRAM

A 256 K (32 K×8) CMOS static RAM (SRAM) which achieves an access time of 7.5 ns and 50-mA active current at 50-MHz operation is described. A 32-block architecture is used to achieve high-speed access and low power dissipation. To achieve faster access time, a double-activated-pulse circuit which generates the word-line-enable pulse and the sense-amplifier-enable pulse has been developed. The data-output reset circuit reduces the transition time and the noise generated by the output buffer. A self-aligned contact technology reduces the diffused region capacitance. This RAM has been fabricated in a twin-tub CMOS 0.8-μm technology with double-level polysilicon (the first level is polycide) and double-level metal. The memory cell size is 6.0×11.0 μm² and the chip size is 4.38×9.47 mm ²     

A 1.5-ns access time, 78-μm2 memory-cell size, 64-kbECL-CMOS SRAM

A 1.5-ns access time, 78-μm² memory-cell size, 64-kb ECL-CMOS SRAM has been developed. This high-performance device is achieved by using a novel ECL-CMOS SRAM circuit technique: a combination of CMOS cell arrays and ECL word drivers and write circuits. These ECL word drivers and write circuits drive the CMOS cell arrays directly without any intermediate MOS level converter. In addition to the ultrahigh-speed access time and relatively small memory-cell size, a very short write-pulse width of 0.8 ns and sufficient soft-error immunity are obtained. This ECL-CMOS SRAM circuit technique is especially useful for realizing ultrahigh-speed high-density SRAMs, which have been used as cache and control storages of mainframe computers     

A 180 MHz 0.8 μm BiCMOS modular memory family of DRAM andmultiport SRAM

A family of modular memories with a built-in self-test interface designed using a synchronous self-timed architecture is described. This approach is ideally suited to modular memories embedded within synchronous systems due to its simple boundary specification, excellent speed/power performance, and ease of modelling. The basic port design is self-contained and extensible to any number of ports sharing access to a common-core cell array. The same design has been used to implement modular one-, two-, and four-part SRAMs and a one-port DRAM based on a four-transistor (4-T) cell. The latter provides a 45% core cell density improvement over the one-port SRAM. Nominal access and cycle times of 5.5 ns for 64 kb blocks have been shown for a 0.8 μm BiCMOS process with no memory process enhancements. System operation at 100 MHz has been demonstrated on a broadband time-switch chip containing 96 kb of two-port SRAM     

A bitline leakage compensation scheme for low-voltage SRAMs

A bitline leakage current of an SRAM, induced by leakage current of the transmission transistors in the cells that are associated with the bitline, increases as the threshold voltage (V_TH) of the transistors is reduced for high performance at low power-supply voltage (V_DD). The increased bitline leakage causes slow or incorrect read/write operation of an SRAM because the leakage current acts as noise current for a sense amplifier. In this paper, the problem has been solved from a circuitry point of view, and the scheme which detects the bitline leakage current in a precharge cycle and compensates for it during a read/write cycle is proposed. Employing this scheme, the SRAM with 360-μA bitline leakage current can perform a read/write operation at the same speed as one that has no bitline leakage current. This enables a 0.1-V reduction in V_TH, and keeps the V_TH and delay scalability of a high-performance SRAM in technology progress. An experimental 8-Kb SRAM with 256 rows is fabricated in a 0.25-μm CMOS technology, which demonstrates the effectiveness of the scheme     

A C-switch cell for low-voltage and high-density SRAMs

We propose a novel static random access memory (SRAM) cell named complementary-switch (C-switch) cell. The proposed SRAM cell features: (1) C-switch in which an n-channel bulk transistor and a p-channel TFT are combined in parallel; (2) single-bit-line architecture; (3) gate-all-around TFT (GAT) with large ON-current of μA order. With these three features, the proposed cell enjoys stability at 1.5 V and is 16% smaller in size than conventional cells. The C-switch cell is built with only a triple poly-Si and one metal process using 0.3 μm design rules