Design of a low-power 3.5-GHz broad-band CMOS transimpedance amplifier for optical transceivers

This paper describes a novel low-power low-noise CMOS voltage-current feedback transimpedance amplifier design using a low-cost Agilent 0.5-/spl mu/m 3M1P CMOS process technology. Theoretical foundations for this transimpedance amplifier by way of gain, bandwidth and noise analysis are developed. The bandwidth of the amplifier was extended using the inductive peaking technique, and, simulation results indicated a -3-dB bandwidth of 3.5 GHz with a transimpedance gain of /spl ap/60 dBohms. The dynamic range of the amplifier was wide enough to enable an output peak-to-peak voltage swing of around 400 mV for a test input current swing of 100 /spl mu/A. The output noise voltage spectral density was 12 nV//spl radic/Hz (with a peak of /spl ap/25 nV//spl radic/Hz), while the input-referred noise current spectral density was below 20 pA//spl radic/Hz within the amplifier frequency band. The amplifier consumes only around 5 mA from a 3.3-V power supply. A test chip implementing the transimpedance amplifier was also fabricated using the low-cost CMOS process.     

A 1.2-V RF front-end with on-chip VCO for PCS 1900 direct conversion receiver in 0.13-/spl mu/m CMOS

In this paper, a 1.2-V RF front-end realized for the personal communications services (PCS) direct conversion receiver is presented. The RF front-end comprises a low-noise amplifier (LNA), quadrature mixers, and active RC low-pass filters with gain control. Quadrature local oscillator (LO) signals are generated on chip by a double-frequency voltage-controlled oscillator (VCO) and frequency divider. A current-mode interface between the downconversion mixer output and analog baseband input together with a dynamic matching technique simultaneously improves the mixer linearity, allows the reduction of flicker noise due to the mixer switches, and minimizes the noise contribution of the analog baseband. The dynamic matching technique is employed to suppress the flicker noise of the common-mode feedback (CMFB) circuit utilized at the mixer output, which otherwise would dominate the low-frequency noise of the mixer. Various low-voltage circuit techniques are employed to enhance both the mixer second- and third-order linearity, and to lower the flicker noise. The RF front-end is fabricated in a 0.13-/spl mu/m CMOS process utilizing only standard process options. The RF front-end achieves a voltage gain of 50 dB, noise figure of 3.9 dB when integrated from 100 Hz to 135 kHz, IIP3 of -9 dBm, and at least IIP2 of +30dBm without calibration. The 4-GHz VCO meets the PCS 1900 phase noise specifications and has a phase noise of -132dBc/Hz at 3-MHz offset.     

A 35-mW 3.6-mm/sup 2/ fully integrated 0.18-/spl mu/m CMOS GPS radio

A single-chip CMOS Global Positioning System (GPS) radio has been integrated using only a couple of external passive components for the input matching network and one external reference for the synthesizer. The receiver downconverts the GPS L1 signal at 1575.42 MHz to an IF of 9.45 MHz. The complete front-end and frequency synthesizer section have been integrated: low noise amplifier, image rejection mixer, IF active filter, and the full phase-locked loop synthesizer, including voltage-controlled oscillator and loop filter. The front-end measured performances are 81-dB maximum gain, 5.3-dB noise figure, and >30-dB image rejection. The synthesizer features a phase noise of -95 dBc/Hz at 1-MHz offset and a total integrated phase noise of less than 7/spl deg/ rms in the 500-Hz-1.5-MHz band. The front-end and the synthesizer draw, respectively, 11 and 9 mA from a 1.8-V supply. The architecture of the front-end and synthesizer has been geared to high level of integration and reduction of silicon area at the lowest possible power consumption. Consequently, the one reported here is the smallest and most integrated CMOS GPS receiver reported so far.     

A 1.9 GHz low-voltage silicon bipolar receiver front-end forwireless personal communications systems

A 1.9 GHz wireless receiver front-end (low-noise preamplifier and mixer) is described that incorporates monolithic microstrip transformers for significant improvements in performance compared to silicon broadband designs. Reactive feedback and coupling elements are used in place of resistors to lower the front-end noise figure through the reduction of resistor thermal noise, and this also allows both circuits to operate at supply voltages below 2 V. These circuits have been fabricated in a production 0.8 μm BiCMOS process that has a peak npn transistor transit frequency (f_T) of 11 GHz. At a supply voltage of 1.9 V, the measured mixer input third-order intercept point is +2.3 dBm with a 10.9 dB single-sideband noise figure. Power dissipated by the mixer is less than 5 mW. The low-noise amplifier input intercept is -3 dBm with a 2.8 dB noise figure and 9.5 dB gain. Power dissipation of the preamplifier is less than 4 mW, again from a 1.9 V supply     

Optical receiver IC for CD/DVD/blue-laser application

In this paper, an optoelectronic receiver IC for CD, DVD, and Blue-Laser optical data storage applications is presented. The IC was developed in a 0.5-/spl mu/m BiCMOS technology with integrated PIN photodiodes. It includes a new architecture of high-speed and low-noise variable gain transimpedance amplifiers witch current preamplifier input. The amplifier transimpedance gain is programmable over a gain range of 130 /spl Omega/ to 270 k/spl Omega/ by a serial interface. The amplifier small-signal bandwidth is 260 MHz for the highest gain, which gives a gain-bandwidth product of 70 THz/spl Omega/ and a sensitivity improvement by a factor of 2 compared to published OEICs. The amplifiers support a special write/clip mode which realizes a nonlinear gain reduction for high input signals. The output voltage buffers are 130-/spl Omega/ impedance matched for optimized data transmission over a flex cable. The impedance is generated by active-impedance synthesis to increase the output dynamic range.     

2.5Gb/Scmos光接收机跨阻前置放大器

给出了一种利用0.35μm CMOS工艺实现的2.5Gb/s跨阻前置放大器。此跨阻放大器的增益为59 dB*Ω,3dB带宽为2GHz,2GHz处的等效输入电流噪声为0.8×10-22 A2/Hz。在标准的5V电源电压下,功耗为250mW。PCML单端输出信号电压摆幅为200mVp-p。整个芯片面积为1.0mm×1.1mm。     

Fiber-optic multigigabit GaAs MIC front-end circuit with inductorpeaking

The design and performance of a multigigabit optical front-end circuit are discussed. Inductor peaking is applied to the GaAs MIC preamplifiers and a 3-dB down bandwidth of 6.5 GHz, 15.5-pA/√Hz averaged input equivalent noise current density from 10 MHz to 6.5 GHz, and transimpedance gain of 57 dB are achieved. A 3-dB down bandwidth of 6.1 GHz is achieved in an optical front-end circuit with a InGaAs p-i-n photodiode. This performance indicates that the optical front-end circuit with inductor peaking is promising for multigigabit optical receivers     

High-gain differential CMOS transimpedance amplifier with on-chip buried double junction photodiode

An integrated fully differential CMOS transimpedance amplifier (TIA) with buried double junction photodiode input is described. The TIA features a variable high transimpedance gain (250 k/spl Omega/ to 2.5 M/spl Omega/), large DC photocurrent rejection capability (>55 dB) and low input referred noise density at 100 kHz (2pA//spl radic/Hz).     

Low-Power 2.4-GHz Transceiver With Passive RX Front-End and 400-mV Supply

An ultra low power 2.4-GHz transceiver targeting wireless sensor network applications is presented. The receiver front-end is fully passive, utilizing an integrated resonant matching network to achieve voltage gain and interface directly to a passive mixer. The receiver achieves a 7-dB noise figure and -7.5-dBm IIP3 while consuming 330 muW from a 400-mV supply. The binary FSK transmitter delivers 300 muW to a balanced 50-Omega load with 30% overall efficiency and 45% power amplifier (PA) efficiency. Performance of the receiver topology is analyzed and simple expressions for the gain and noise figure of both the passive mixer and matching network are derived. An analysis of passive mixer input impedance reveals the potential to reject interferers at the mixer input with characteristics similar to an extremely high-Q parallel LC filter centered at the switching frequency     

1-Gb/s 80-dB/spl Omega/ fully differential CMOS transimpedance amplifier in multichip on oxide technology for optical interconnects

A 1-Gb/s differential transimpedance amplifier (TIA) is realized in a 0.25-/spl mu/m standard CMOS technology, incorporating the regulated cascode input configuration. The TIA chip is then integrated with a p-i-n photodiode on an oxidized phosphorous-silicon (OPS) substrate by employing the multichip-on-oxide (MCO) technology. The MCO TIA demonstrates 80-dB/spl Omega/ transimpedance gain, 670-MHz bandwidth for 1-pF photodiode capacitance, 0.54-/spl mu/A average input noise current, -17-dBm sensitivity for 10/sup -12/ bit-error rate (BER), and 27-mW power dissipation from a single 2.5-V supply. It also shows negligible switching noise effect from an embedded VCO on the OPS substrate. Furthermore, a four-channel MCO TIA array is implemented for optical interconnects, resulting in less than -40-dB crosstalk between adjacent channels.     

A variable transimpedance preamplifier for use in wide dynamic range optical receivers

A preamplifier with an automatic gain control (AGC) function based on a new circuit configuration suitable for monolithic integration is proposed as an approach for realizing optical receivers with wide dynamic ranges. This new preamplifier, intended for transmission systems operating above 100 Mb/s, is designed for fabrication using 3-/spl mu/m Si-bipolar IC technology. The fabricated IC exhibits a bandwidth of more than 220 MHz and an equivalent input noise current of about 3 pA//spl radic/Hz at a maximum transimpedance of 18 k/spl Omega/. To examine the AGC capability of the new preamplifier IC, a 140-Mb/s transmission experiment was carried out using a laser diode (LD) transmitter and a p-i-n receiver with its gain controlled by the new preamplifier. An optical dynamic range of 21.5 dB was achieved and thus it should be possible to realize optical receivers with wide dynamic ranges using this preamplifier.     

A 455-Mb/s MR preamplifier design in a 0.8-μm CMOS process

In this paper, we present a CMOS preamplifier for use with magnetoresistive (MR) read elements in disk drives. The performance of the CMOS design is competitive with the more expensive current generation of BiCMOS MR preamplifiers. The measured gain for the preamplifier is 43 dB and the measured 3-dB bandwidth is greater than 273 MHz corresponding to a 455-Mb/s data rate. Likewise, the measured input-referred voltage noise is less than 0.57 nV/√Hz, and measured input-referred current noise is less than 10.54 pA/√Hz at an MR bias current of 10 mA, The preamplifier has been implemented in a 0.8-μm 5 V CMOS process and occupies a die area of 1.78×1.78 mm ² In this paper, we introduce a new scheme to reduce current noise below that contributed by a single MOS device, This technique has the potential for even more impact for future submicron processes. We also showed that voltage amplifiers offer lower noise than transimpedance amplifiers for similar gain and bandwidth constraints     

A K-band down-conversion mixer with 1.4-GHz bandwidth in 0.13-/spl mu/m CMOS technology

A low power and low voltage down conversion mixer working at K-band is designed and fabricated in a 0.13/spl mu/m CMOS logic process. The mixer down converts RF signals from 19GHz to 2.7GHz intermediate frequency. The mixer achieves a conversion gain of 1dB, a very low single side band noise figure of 9dB and third order intermodulation point of -2dBm, while consuming 6.9mW power from a 1.2V supply. The 3-dB conversion gain bandwidth is 1.4GHz, which is almost 50% of the IF. This mixer with small frequency re-tuning can be used for ultra-wide band radars operating in the 22-29GHz band.     

Low-voltage CMOS current-mode preamplifier: analysis and design

This paper presents the analysis and design of a new low-voltage fully balanced differential CMOS current-mode preamplifier for multi-Gbps series data communications. The minimum supply voltage of the proposed preamplifier is V/sub T/+V/sub sat/. The preamplifier employs a balanced configuration to achieve large bandwidth and to minimize the effect of bias-dependent mismatches. Two new bandwidth enhancement techniques, namely inductive series peaking and current feedback that are specific to low-voltage CMOS current-mode circuits, are introduced. The inductive series peaking technique utilizes the resonant characteristics of LC networks to achieve both a flat frequency response and maximum bandwidth. Current feedback extends bandwidth, lowers input impedance, and improves dynamic range. The employment of both techniques further increases the bandwidth, reduces the value of the series peaking inductor, and improves noise performance of the pre-amplifier at high frequencies. The preamplifier has been designed using a 0.18-/spl mu/m 6-metal 1-poly 1.8-V CMOS technology. Simulation results from Spectre with BSIM3.3 device models that account for device parasitics demonstrate that the preamplifier has a flat frequency response with 25.3 dB dc current gain or equivalently 60 dB/spl Omega/ transimpedance gain with a 50-/spl Omega/ load and bandwidth of 2.15 GHz.     

CMOS wideband amplifiers using multiple inductive-series peaking technique

This work presents the technique of multiple inductive-series peaking to mitigate the deteriorated parasitic capacitance in CMOS technology. Employing multiple inductive-series peaking technique, a 10-Gb/s optical transimpedance amplifier (TIA) has been implemented in a 0.18-/spl mu/m CMOS process. The 10-Gb/s optical CMOS TIA, which accommodates a PD capacitor of 250 fF, achieves the gain of 61 dB/spl Omega/ and 3-dB frequency of 7.2 GHz. The noise measurement shows the average noise current of 8.2 pA//spl radic/Hz with power consumption of 70 mW.     

A wide-band RF front-end for multiband multistandard high-linearity low-IF wireless receivers

A wide-band radio-frequency (RF) front-end is designed with a balanced combined low-noise amplifier and a switching mixer (a low-noise converter) in an RF Si-bipolar process with an f/sub T/ of 25 GHz. The circuit achieves 20-dB conversion gain, higher than -4.5-dBm RF-to-IF IIP/sub 3/ (+15.5-dBm OIP/sub 3/) and less than 3.8-dB double-side-band noise figure in 900-MHz (e.g., GSM) and 1.9-GHz (e.g., WCDMA) frequency bands. The -1-dB compression point is -20 dBm at 13-mA DC current consumption from a single 5-V supply. The local-oscillator leakage to the input is less than -56 dBm in the 900-MHz band and less than -63 dBm in the 1.9-GHz band. The -3-dB bandwidth of the amplifier is larger than 3 GHz and a wide-band matching at the input with -10 to -41-dB S/sub 11/ is achieved in the frequency bands of interest by applying a dual-loop wide-band active feedback. The die area is 0.69 /spl times/ 0.9 mm/sup 2/. The circuit is suitable for area-efficient multiband multistandard low-IF receivers.     

6-k/spl Omega/ 43-Gb/s differential transimpedance-limiting amplifier with auto-zero feedback and high dynamic range

A high-gain, 43-Gb/s InP HBT transimpedance-limiting amplifier (TIALA) with 100-/spl mu/A/sub pp/ sensitivity and 6 mA/sub pp/ input overload current is presented. The circuit also operates as a limiting amplifier with 40-dB differential gain, better than 15-dB input return loss, and a record-breaking sensitivity of 8 mV/sub pp/ at 43 Gb/s. It features a differential TIA stage with inductive noise suppression in the feedback network and consumes less than 450mW from a single 3.3-V supply. The TIALA has 6-k/spl Omega/ (76dB/spl Omega/) differential transimpedance gain and 35-GHz bandwidth and comprises the transimpedance and limiting gain functions, an auto-zero dc feedback circuit, signal level monitor, and slicing level adjust functions. Other important features include 45-dB isolation and 800-mV/sub pp/ differential output.     

1.25-Gb/s regulated cascode CMOS transimpedance amplifier for Gigabit Ethernet applications

A transimpedance amplifier (TIA) has been realized in a 0.6-/spl mu/m digital CMOS technology for Gigabit Ethernet applications. The amplifier exploits the regulated cascode (RGC) configuration as the input stage, thus achieving as large effective input transconductance as that of Si Bipolar or GaAs MESFET. The RGC input configuration isolates the input parasitic capacitance including photodiode capacitance from the bandwidth determination better than common-gate TIA. Test chips were electrically measured on a FR-4 PC board, demonstrating transimpedance gain of 58 dB/spl Omega/ and -3-dB bandwidth of 950 MHz for 0.5-pF photodiode capacitance. Even with 1-pF photodiode capacitance, the measured bandwidth exhibits only 90-MHz difference, confirming the mechanism of the RGC configuration. In addition, the noise measurements show average noise current spectral density of 6.3 pA//spl radic/(Hz) and sensitivity of -20-dBm for a bit-error rate of 10/sup -12/. The chip core dissipates 85 mW from a single 5-V supply.     

一种高性能宽带直接变频射频前端设计

提出一种宽带(250 MHz~4.7 GHz)无电感BiCMOS射频前端结构,包含低噪声跨导放大器(LNTA)、带电阻无源混频器和跨阻级。低噪声跨导放大器使用了噪声和线性度消除技术,例如输入交叉耦合结构、互补输入和电流复用技术。带电阻无源混频器采用退化电阻来提高线性度。仿真结果表明, 当电源电压为3.3 V时,总电流为9.38 mA, 噪声系数为9.8 dB(SSB),电压转换增益为20 dB,输入3阶交调为+11.8 dBm。     

An energy-efficient analog front-end circuit for a sub-1-V digital hearing aid chip

A low-power energy-efficient adaptive analog front-end circuit is proposed and implemented for digital hearing-aid applications. It adopts the combined-gain-control (CGC) technique for accurate preamplification and the adaptive-SNR (ASNR) technique to improve dynamic range with low power consumption. The CGC technique combines an automatic gain control and an exponential gain control together to reduce power dissipation and to control both gain and threshold knee voltage. The ASNR technique changes the value of the signal-to-noise ratio (SNR) in accordance with input amplitude in order to minimize power consumption and to optimize the SNR by sensing an input signal. The proposed analog front-end circuit achieves 86-dB peak SNR in the case of third-order /spl Sigma//spl Delta/ modulator with 3.8-/spl mu/Vrms of input-referred noise voltage. It dissipates a minimum and maximum power of 59.4 and 74.7 /spl mu/W, respectively, at a single 0.9-V supply. The core area is 0.5 mm/sup 2/ in a 0.25-/spl mu/m standard CMOS technology.