Facile polymer gate dielectric surface-modification for organic thin-film transistors using self-assembled surfactant layer

We demonstrate facile polymer gate dielectric surface-modification method for organic thin-film transistors (OTFTs). We simply introduce self-assembled surfactant layer onto the top surface of poly(4-vinylphenol) (PVP) dielectric by spin coating PVP solution mixed with sodium dodecyl sulfate and tridecafluorohexane-1-sulfonic acid potassium salt as additive agents. The surfactant-modified PVP layer acquires various merits compared to pristine PVP layer in terms of surface smoothness and hydrophobicity, as confirmed by contact angle measurement, atomic force microscopy analyses, grazing incident X-ray diffraction and near-edge X-ray absorption fine structure spectroscopy. The resulting OTFTs with the conventional semiconducting poly(2,5-bis(3-hexadecylthiophen-2-yl)thieno[3,2-b]thiophene) as the active layer and surfactant-modified PVP as the dielectric layer reveal overall ascendency over the OTFT with pristine PVP, especially in terms of operating hysteresis and reliability. The effects of hydrophobicity of surfactants on the surface properties of PVP as well as the OTFT performances are fully discussed in conjunction with various characterization tools.     

Low-power organic field-effect transistors and complementary inverter based on low-temperature processed Al2O3 dielectric

Organic-based complementary inverter could be a key component in future flexible and portable electronic products, which require low-power operation, high operating stability and flexible compatibility at the same time. A simple method for making excellent Al₂O₃ gate dielectric is developed toward the target, and it is a low-cost solution process with a low annealing temperature compatible with plastic substrates. Utilizing the Al₂O₃ dielectric, both p-type and n-type low-voltage organic field-effect transistors (OFETs) are realized. The device operating voltage is down to ±3 V, and the On/Off ratio is up to 10⁶. The hole and electron field-effect mobilities are 2.7 cm²/V and 0.2 cm²/V, respectively, and the subthreshold swing is as small as about 110 mV/decade. The high quality of the Al₂O₃ dielectric results in high operating stability of the devices. The p-type and n-type OFETs are integrated to achieve a low-power complementary inverter with a large gain, which can be successfully fabricated on a flexible substrate.     

Below-one-volt organic thin-film transistors with large on/off current ratios

In many of the applications envisioned for organic thin-film transistors (TFTs), the electrical power will be supplied by small batteries or energy harvesters, which implies that it will be beneficial if the TFTs can be operated with voltages of 1 V or even below 1 V. At the same time, the TFTs should have large on/off current ratios, especially for applications in digital circuits and active matrices. Here we demonstrate p-channel and n-channel organic TFTs fabricated on a flexible plastic substrate that have a turn-on voltage of exactly 0 V, a subthreshold slope of 100 mV/decade, and an on/off current ratio of 2 × 10⁵ when operated with gate-source voltages between 0 and 0.7 V. Complementary inverters fabricated using these TFTs have a small-signal gain of 90 and a minimum noise margin of 79% at a supply voltage of 0.7 V. Complementary ring oscillators can be operated with supply voltages as small as 0.4 V.     

High-performance pentacene thin-film transistor with ZrLaO gate dielectric passivated by fluorine incorporation

Pentacene thin-film transistor with high-κ ZrLaO gate dielectric has been fabricated for the first time. After treating the dielectric in a fluorine plasma, the carrier mobility of the transistor can be greatly improved to 0.717 cm²/V s, which is more than 40 times that of one without plasma treatment. The major reasons should be larger pentacene grains and fewer traps in the device with gate dielectric passivated by the fluorine plasma. AFM confirms that relatively large and high pentacene islands form on the plasma-treated dielectrics in the initial growth stage, and the growth pattern obviously follows the Vollmer–Weber growth model. Furthermore, the surfaces of the dielectrics with different plasma treatment times are investigated by AFM, XPS and contact-angle measurement to reveal the mechanism/effects of the fluorine incorporation. Lastly, after exposure to atmosphere without encapsulation for 6 months, all the devices still display good transistor characteristics.     

Solution processable bilayered gate dielectric towards flexible organic thin film transistors

In this study, we have successfully explored the potential of a new bilayer gate dielectric material, composed of Polystyrene (PS), Pluronic P123 Block Copolymer Surfactant (P123) composite thin film and Polyacrylonitrile (PAN) through fabrication of metal insulator metal (MIM) capacitor devices and organic thin film transistors (OTFTs). The conditions for fabrication of PAN and PS-P123 as a bilayer dielectric material are optimized before employing it further as a gate dielectric in OTFTs. Simple solution processable techniques are applied to deposit PAN and PS-P123 as a bilayer dielectric layer on Polyimide (PI) substrates. Contact angle study is further performed to explore the surface property of this bilayer polymer gate dielectric material. This new bilayer dielectric having a k value of 3.7 intermediate to that of PS-P123 composite thin film dielectric (k ∼ 2.8) and PAN dielectric (k ∼ 5.5) has successfully acted as a buffer layer by preventing the direct contact between the organic semiconducting layer and high k PAN dielectric. The OTFT devices based on α,ω-dihexylquaterthiophene (DH4T) incorporated with this bilayer dielectric, has demonstrated a hole mobility of 1.37 × 10⁻² and on/off current ratio of 10³ which is one of the good values as reported before. Several bending conditions are applied, to explore the charge carrier hopping mechanism involved in deterioration of electrical properties of these OTFTs. Additionally, the electrical performance of OTFTs, which are exposed to open atmosphere for five days, can be interestingly recovered by means of re-baking them respectively at 90 °C.     

Triacetate cellulose gate dielectric organic thin-film transistors

Here, we report on the performance and the characterization of all solution-processable top-contact organic thin-film transistors (OTFTs) consisting of a natural-resourced triacetate cellulose gate dielectric and a representative hole-transport poly[2,5-bis(3-dodecylthiophen-2-yl)thieno[3,2-b]thiophene] (pBTTT) semiconductor layer on rigid or flexible substrates. The bio-based triacetate cellulose layer has an important role in the OTFT fabrication because it provides the pBTTT semiconducting polymer with highly suitable gate dielectric properties including a low surface roughness, hydrophobic surface, appropriate dielectric constant, and low leakage current. The triacetate cellulose gate dielectric-based pBTTT OTFTs exhibit an average filed-effect mobility of 0.031 cm²/Vs similar to that obtained from a SiO₂ gate dielectric-based OTFT device in ambient conditions. Even after a bending stimulation of 100 times and in an outward bending state, the flexible triacetate cellulose gate pBTTT OTFT device still showed excellent electrical device performance without any hysteresis.     

Cardanol-based polymeric gate dielectric for solution-processed organic field-effect transistors on flexible substrates

A cardanol-based polymer, poly(2-hydroxy-3-cardanylpropyl methacrylate) (PHCPM), was utilized as the gate dielectric of an organic field-effect transistor (OFET). PHCPM has good surface properties, appropriate gate dielectric characteristics, and good compatibility with solution-processed semiconducting polymers. The electrical properties of an FET that was prepared with natural resource-based PHCPM as a gate dielectric layer and solution-processed poly[2,5-bis(3-dodecylthiophen-2-yl)thieno[3,2-b]thiophene] (PBTTT) as a semiconducting layer were investigated on flexible substrates. The flexible PBTTT-OFET device with the PCHPM gate dielectric exhibited high mobility and reliable performance, even in the bending state, without significant hysteresis.     

Parylene based bilayer flexible gate dielectric layer for top-gated organic field-effect transistors

In this paper, we report on a bilayer insulating film based on parylene-c for gate dielectric layers in top-gate/bottom-contact inkjet-printed organic field-effect transistors (OFETs) with indacenodithiophene-co-benzothiadiazole (IDTBT) and poly([N,N’-bis(2-octyldodecyl)-naphthalene-1,4,5,8-bis(dicarboximide)-2,6-diyl]-alt-5,5’-(2,2’-bitthiophene)) (P(NDI2OD-T2)) as with p- and n-channel semiconductors. The thin parylene-c film (t = 210 nm) show large gate leakage density (2.52 nA/cm² at 25 V) and low breakdown voltage (2.2 MV/cm). In addition, a degraded field-effect mobility (μ) was observed in printed IDTBT and P(NDI2OD-T2) OFETs with the parylene-c single-layered dielectric. X-ray photoelectron spectroscopy (XPS) analysis reveals that the degradation of μ is due to unwanted chemical interaction between parylene-c and the conjugated polymer surface during the parylene-c deposition process. By inserting 50-nm thick poly(methyl-methacrylate) (PMMA) and polystyrene (PS) layer in-between the parylene-c and conjugated polymer film, highly improved gate leakage density and breakdown voltage are achieved. The printed IDTBT and P(NDI2OD-T2) OFETs with a bilayer dielectric compose of parylene-c and PMMA and PS show significantly improved hole and electron μ of 0.47 cm²/Vs and 0.13 cm²/Vs, respectively, and better operation stability. In addition, we demonstrate inkjet-printed polymer complementary inverter with a high voltage gain of 25.7 by applying a PS/parylene-c bilayer dielectric.     

Low-voltage p-channel, n-channel and ambipolar organic thin-film transistors based on an ultrathin inorganic/polymer hybrid gate dielectric layer

A key issue in research into organic thin-film transistors (OTFTs) is low-voltage operation. In this study, we fabricated low-voltage operating (below 3V) p-channel, n-channel and ambipolar OTFTs based on pentacene or/and C₆₀ as the active layers, respectively, with an ultrathin AlO_X/poly(methyl methacrylate co glycidyl methacrylate) (P(MMA–GMA)) hybrid layer as the gate dielectric. Benefited from the enhanced crystallinity of C₆₀ layer and greatly reduced density of electron trapping states at the interface of channel/dielectric due to the insertion of ultrathin pentacene layer between C₆₀ and P(MMA–GMA), high electron mobility can be achieved in present pentacene/C₆₀ heterostructure based ambipolar OTFTs. The effect of the thickness of pentacene layer and the deposition sequence of pentacene and C₆₀ on the device performance of OTFTs was studied. The highest electron mobility of 3.50 cm²/V s and hole mobility of 0.25 cm²/V s were achieved in the ambipolar OTFT with a pentacene (3.0 nm)/C₆₀ (30 nm) heterostructure.     

Preparation of a new gate dielectric material HfTiON film

A new gate dielectric material HfTiON is deposited by reactive co-sputtering of Hf and Ti targets in N2/O2 ambient, followed by annealing in N2 at 600 ℃ and 800 ℃ respectively for 2 min. Capacitance-voltage and gate-leakage properties are characterized and compared for different anneal conditions. The results indicate that the sample annealed at 800 ℃ exhibits lower interface-state and oxide-charge densities, and better device reliability. This is attributed to the fact that the rapid thermal annealing at the higher temperature of 800 ℃ can effectively remove the damage-induced precipitation, forming a hardened dielectric/Si interface with high reliability.     

Cyanoethylated pullulan as a high-k solution processable polymer gate dielectric for SWCNT TFTs

Cyanoethylated pullulan (CEP), a high-k solution processable polymer gate dielectric, is used to fabricate bottom gated single wall carbon nanotube (SWCNT) network thin film transistors (TFTs). Both aqueous and organic dispersions of highly semiconducting enriched SWCNTs are used as the channel material. Use of CEP as the dielectric enables fabrication of devices operating at low voltage (<3 V) with high on-state currents, good on/off ratios (∼10⁵), low subthreshold swings (∼200 mV/decade) and minimal hysteresis (<1 V). However, despite high apparent mobilities extracted from gate voltage sweeps, driving these devices at even modest frequencies (>1 Hz) is found to significantly decrease the transconductance. This is shown to be related to a significant frequency dependence of the capacitance associated with a slow polarization response of the dielectric. Despite this limitation, CEP could be a useful dielectric in SWCNT TFTs for applications such as sensors and low frequency amplifiers.     

High performance organic thin film transistors using chemically modified bottom contacts and dielectric surfaces

A compatible process of orthogonal self-assembled monolayers (SAMs) is applied to intentionally modify the bottom contacts and gate dielectric surfaces of organic thin film transistors (OTFTs). This efficient interface modification is first achieved by 4-fluorothiophenol (4-FTP) SAM to chemically treat the silver source–drain (S/D) contacts while the silicon oxide (SiO₂) dielectric interface is further primed by either hexamethyldisilazane (HMDS) or octyltrichlorosilane (OTS-C8). Results show that the field effect mobilities of the bottom-gate bottom-contact PTDPPTFT4 transistors were significantly improved to 0.91 cm² V⁻¹ s⁻¹.     

Bias-stress stability of low-voltage p-channel and n-channel organic thin-film transistors on flexible plastic substrates

The bias-stress stability of low-voltage organic p-channel and n-channel thin-film transistors (TFTs) based on five promising organic semiconductors and fabricated on flexible polyethylene naphthalate (PEN) substrates has been investigated. In particular, it has been studied to which extent the bias-stress-induced decay of the on-state drain current of the TFTs is affected by the choice of the semiconductor and by the gate-source and drain-source voltages applied during bias stress. It has been found that for at least some of the organic p-channel TFTs investigated in this study, the bias-stress stability is comparable to that of a-Si:H and metal-oxide TFTs, despite the fact that the organic TFTs were fabricated at significantly lower process temperatures, which is important in view of the fabrication of these devices on plastic substrates.     

Morphology transformations of pentacene on an UV-patternable polymer insulator and their effect on performance of flexible organic thin-film transistors

This work presents a low temperature with high resolution capability UV-patternable polymer, i.e. mr-UVCur06, for use as a gate insulator in OTFTs, by investigating the morphology transformation of pentacene deposited on the mr-UVCur06. The device structure is polyethylene terephthalate (PET)/indium-tin oxide (ITO)/mr-UVCur06/pentacene/Au (source/drain). In addition to its solution-processable capability, mr-UVCur06 is directly patterned by UV light in a low-temperature process. UV/ozone post-treatment of the patternable mr-UVCur06 can illuminate organic contaminants from its surface and increases surface energy. Experimental results indicate that a high surface energy existing at the mr-UVCur06 surface has produced in a larger ratio of I_{thin film phase}/I_{triclinic bulk phase} in pentacene. Then, the distance of pentacene molecular crystal structure, which is arranged in the thin film phase, is shorter than that in triclinic bulk phase. The performance of pentacene-based OTFTs can be enhanced with few contaminants and a high surface energy on the UV-patternable gate insulator. By performing UV/ozone post-treatment on the mr-UVCur06 insulator surface for 60 s, the OTFTs demonstrate a mobility, on/off drain current ratio, and V_T of 0.34 cm²/V s, 5.5 × 10⁴, and 2.5 V, respectively. Furthermore, the low-temperature photopatternable polymer dielectric paves the way for a relatively easy and low-cost fabrication of an OTFT array without expensive and complicated photolithography and dry etching.     

Low-voltage organic transistors with steep subthreshold slope fabricated on commercially available paper

Organic thin-film transistors were fabricated directly on the surface of commercially available cleanroom paper using the vacuum-deposited small-molecule semiconductor dinaphtho[2,3-b:2′,3′-f]thieno[3,2-b]thiophene (DNTT). A thin, high-capacitance gate dielectric that allows the TFTs to be operated with low voltages of 2 V was employed. The TFTs have a charge-carrier mobility of 1.6 cm²/Vs, an on/off current ratio of 10⁶, and a subthreshold slope of 90 mV/decade. In addition, the TFTs also display a very large differential output resistance, which is an important requirement for applications in analog circuits and active-matrix displays.     

绝缘层/有源层界面修饰及对有机薄膜晶体管性能的影响

制备了具有修饰层的有机薄膜场效应晶体管,采用高掺杂Si作为栅极,传统的无机绝缘材料SiO2作为栅绝缘层,有机绝缘材料PMMA或OTS作为修饰层,CuPc作为有源层,Au作为源、漏极.测试结果表明,采用经过修饰的栅绝缘层SiO2/OTS和SiO2/PMMA的两种器件的开关电流比最高可达8×104,迁移率最高为1.22×10-3cm2/(V·s),而漏电流仅为10-10A,总体性能优于单层SiO2器件.     

绝缘层/有源层界面修饰及对有机薄膜晶体管性能的影响

制备了具有修饰层的有机薄膜场效应晶体管,采用高掺杂Si作为栅极,传统的无机绝缘材料SiO2作为栅绝缘层,有机绝缘材料PMMA或OTS作为修饰层,CuPc作为有源层,Au作为源、漏极.测试结果表明,采用经过修饰的栅绝缘层SiO2/OTS和SiO2/PMMA的两种器件的开关电流比最高可达8×104,迁移率最高为1.22×10-3cm2/(V·s),而漏电流仅为10-10A,总体性能优于单层SiO2器件.     

Pentacene organic field-effect transistors with polymeric dielectric interfaces: Performance and stability

Low-voltage pentacene organic field-effect transistors (OFETs) with different gate dielectric interfaces are studied and their performance in terms of electrical properties and operational stability is compared. Overall high electrical performance is demonstrated at low voltage by using a 100 nm-thick high-κ gate dielectric layer of aluminum oxide (Al₂O₃) fabricated by atomic layer deposition (ALD) and modified with hydroxyl-free low-κ polymers like polystyrene (PS), divinyltetramethyldisiloxane-bis(benzocyclobutene) (BCB) (Cyclotene™, Dow Chemicals), and as well as with the widely used octadecyl-trichlorosilane (OTS). Devices with PS and BCB dielectric surfaces exhibit almost similar electrical performance with high field-effect mobilities, low subthreshold voltages, and high on/off current ratios. The higher mobility in pentacene transistors with PS can be correlated to the better structural ordering of pentacene films, as demonstrated by atomic force microscopy (AFM) images and X-ray diffraction (XRD). The devices with PS show good electrical stability under bias stress conditions (V_GS = V_DS = −10 V for 1 h), resulting in a negligible drop (2%) in saturation current (I_DS) in comparison to that in devices with OTS (12%), and to a very high decay (30%) for the devices with BCB.     

Solution processed inverter based on zinc oxide nanoparticle thin-film transistors with poly(4-vinylphenol) gate dielectric

An enhancement-load inverter using bottom-gated ZnO nanoparticle thin-film transistors and a polymer gate dielectric is demonstrated. The deposition of the ZnO active layer is done by spin coating of a colloidal dispersion and is hence cost-effective. Since the maximum process temperature is 200 °C, the presented device is furthermore suitable for plastic substrates. Although hysteresis is observed, the inverter shows reasonable transfer characteristics with a gain of up to 5.5 V/V at a supply voltage between 10 V and 15 V, whereas the static power dissipation is lower than 6 μW.     

Direct tunneling gate current model for symmetric double gate junctionless transistor with SiO2/high-k gate stacked dielectric

A junctionless transistor is emerging as a most promising device for the future technology in the decananometer regime. To explore and exploit the behavior completely, the understanding of gate tunneling current is of great importance. In this paper we have explored the gate tunneling current of a double gate junctionless transistor(DGJLT) for the first time through an analytical model, to meet the future requirement of expected high-k gate dielectric material that could replace SiO₂. We therefore present the high-k gate stacked architecture of the DGJLT to minimize the gate tunneling current. This paper also demonstrates the impact of conduction band offset, workfunction difference and k-values on the tunneling current of the DGJLT.