Si／SiGe／Si HBT的优化设计

给出了常温和低温Ｓｉ／ＳｉＧｅ／ＳｉＨＢＴ的设计原则，并进行了讨论。指出了低温和室温ＨＢＴ设计上的差异。这些原则可用于设计特定要求的Ｓｉ／ＳｉＧｅ／ＳｉＨＢＴ。     

Current transport characteristics of SiGeC/Si heterojunction diode

The characteristics of heterojunction diodes fabricated from p-type epitaxial Si_0.07Ge_0.91C_0.02 alloy grown by molecular beam epitaxy on n-type Si(100) have been examined by using current-voltage, capacitance-voltage, and Hall effect measurements. The SiGeC/Si heterojunction diode shows good rectification with nearly ideal forward bias behavior and low reverse leakage currents compared to Ge/Si heterojunction diodes. The temperature dependence of the current-voltage behavior indicates that the principle conduction mechanism is by electron injection over a barrier. Reverse breakdown occurs by the avalanche mechanism     

Enhanced Carbon Confinement of Ultranarrow Boron Profiles in SiGeC HBTs

This paper reports on observations of enhanced carbon confinement of ultranarrow boron profiles in silicon–germanium–carbon heterojunction bipolar transistors (SiGeC HBTs). Electrical measurements of HBT devices with base regions formed during a low-pressure chemical-vapor deposition, with this method shows that a current gain$(beta)$is increased, base sheet resistance$(R_ bs)$is reduced, and the maximum oscillation frequency$(f_max)$is improved.     

TiN栅薄膜全耗尽SOI CMOS器件

制备并研究了TiN栅薄膜全耗尽SOI CMOS器件,并对其关键工艺进行了详细阐述.相对于双多晶硅栅器件,在不改变阈值电压的前提下,可以减小nMOS和pMOS的沟道掺杂浓度,进而提高迁移率.由于TiN的功函数处于中间禁带,在几乎相同的调整阈值注入剂量下,可以得到对称的阈值电压.当顶层硅膜厚度减小时,可以改善短沟道效应.     

CMOS兼容近红外Si0.7Ge0.3/Si p-i-n(SOI)光电探测器

报道了一种采用UHV/CVD锗硅工艺和CMOS工艺流程在SOI衬底上制作的横向叉指状Si0.7Ge0.3/Si p-i-n光电探测器.测试结果表明:其工作波长范围为0.7～1.1μm,在峰值响应波长为0.93μm,响应度为0.38A/W.在3.0V的偏压下,其暗电流小于1nA,寄生电容小于1.0pF,上升时间为2.5ns.其良好的光电特性以及与CMOS工艺的兼容性,为研制能有效工作于近红外光的高速、低工作电压硅基光电集成器件提供了一种新的尝试,在高速光信号探测等应用中有一定的价值.     

CMOS兼容近红外Si0.7Ge0.3/Si p-i-n(SOI)光电探测器

报道了一种采用UHV/CVD锗硅工艺和CMOS工艺流程在SOI衬底上制作的横向叉指状Si0.7Ge0.3/Si p-i-n光电探测器.测试结果表明:其工作波长范围为0.7～1.1μm,在峰值响应波长为0.93μm,响应度为0.38A/W.在3.0V的偏压下,其暗电流小于1nA,寄生电容小于1.0pF,上升时间为2.5ns.其良好的光电特性以及与CMOS工艺的兼容性,为研制能有效工作于近红外光的高速、低工作电压硅基光电集成器件提供了一种新的尝试,在高速光信号探测等应用中有一定的价值.     

W/TiN Gate Thin-Film Fully-Depleted SOI CMOS Devices

TiN gate thin-film fully-depleted SOI CMOS devices are fabricated and discussed.Key process technologies are demonstrated.Compared with the dual polysilicon gate devices,the channel doping concentration of nMOS and pMOS can be reduced without changing threshold voltage (VT)，which enhances the mobility.Symmetrical VT is achieved by nearly the same VT implant dose because of the near mid-gap workfunction of TiN gate.The SCE effect is improved when the thin-film thickness is reduced.     

SiGeC/Si异质结二极管特性分析与优化设计

基于异质结理论,提出了一种新型p+(SiGeC)-n--n+异质结功率二极管结构。分析了C对SiGe合金的应变补偿作用的物理机理。利用MEDICI模拟、对比分析了C的引入对器件电特性的影响,并针对不同Ge/C组分比进行优化设计。结果表明:在SiGe/Si功率二极管中加入少量的C,在基本不影响器件正向I-V特性和反向恢复特性的前提下,大大减少了器件的反向漏电流,提高了器件稳定性,而且对于一定的Ge含量存在一个C的临界值,使得二极管具有最小的反向漏电流,该临界值的提出,对研究其它结构SiGeC/Si异质结半导体器件有一定的参考意义。     

SiGeC/Si功率二极管的数值模拟与分析

将SiGeC技术应用于功率半导体器件的特性改进,提出了一种新型p+(SiGeC)-n--n+异质结功率二极管结构.在分析SiGeC合金材料物理特性的基础上,给出了该结构的关键物理参数模型,并在此基础上利用MEDICI模拟,对比分析了C的引入对器件各种电特性的影响.此外,还模拟比较了不同p+区厚度对器件反向漏电流的影响.结果表明:在SiGe/Si功率二极管中加入少量的C,在基本不影响器件正向I-V特性和反向恢复特性的前提下,大大减少了器件的反向漏电流,并且C的加入还减小了器件特性对材料临界厚度的依赖性,提高了器件稳定性.     

SiGeC/Si功率二极管的数值模拟与分析

将SiGeC技术应用于功率半导体器件的特性改进,提出了一种新型p (SiGeC)-n--n 异质结功率二极管结构.在分析SiGeC合金材料物理特性的基础上,给出了该结构的关键物理参数模型,并在此基础上利用MEDICI模拟,对比分析了C的引入对器件各种电特性的影响.此外,还模拟比较了不同p 区厚度对器件反向漏电流的影响.结果表明:在SiGe/Si功率二极管中加入少量的C,在基本不影响器件正向I-V特性和反向恢复特性的前提下,大大减少了器件的反向漏电流,并且C的加入还减小了器件特性对材料临界厚度的依赖性,提高了器件稳定性.     

Si/SiGe/Si HBT频率特性的解析模型与模拟

用解析的方法模拟了T＝300K和77K时，fT和fmax与集电极电流密度Jc的关系，在大电流下考虑了异质结势垒效应的影响。模拟结果和用数值方法以及实验所得到的结果一致。同时，还建立了与之相应的Si／SiGeeb异质结和SiGe／Sibc异质结电容模型。     

Dynamic characterisation of Si/SiGe power HBTs

Si/SiGe power heterojunction bipolar transistors (HBTs) grown by MBE were dynamically characterised in the common-base configuration. At an emitter current density of 1.1×10⁵ A/cm², a maximum frequency of oscillation of 49 GHz was observed. At 10 GHz a maximum unilateral gain of 14 dB is available, and a CW output power of 1.3 W/mm for a device with 10 parallel emitter-fingers of 1×10 μm² each was predicted, from CW measurements     

SiGe HBTs on bonded SOI incorporating buried silicide layers

A technology is described for fabricating SiGe heterojunction bipolar transistors (HBTs) on wafer-bonded silicon-on-insulator (SOI) substrates that incorporate buried tungsten silicide layers for collector resistance reduction or buried groundplanes for crosstalk suppression. The physical structure of the devices is characterized using cross section transmission electron microscopy, and the electrical properties of the buried tungsten silicide layer are characterized using sheet resistance measurements as a function of bond temperature. Possible contamination issues associated with the buried tungsten silicide layer are investigated by measuring the collector/base reverse diode tics. A resistivity of 50 /spl mu//spl Omega/cm is obtained for the buried silicide layer for a bond anneal of 120 min at 1000/spl deg/C. Collector/base reverse diode tics show a voltage dependence of approximately V/sup 1/2/, indicating that the leakage current is due to Shockley-Read-Hall generation in the depletion region. Fitting of the current-voltage tics gives a generation lifetime of 90 ns, which is as expected for the collector doping of 7 /spl times/ 10/sup 17/ cm/sup -3/. These results indicate that the buried tungsten silicide layer does not have a serious impact on junction leakage.     

薄膜SOI器件研究与展望

本文详细地分析了薄膜SOI器件一系列有益的特性,如:较大的亚阈值陡度,扭曲(kink)效应的消除以及短沟道效应的削弱等。最后指出,薄膜SOI器件技术是今后设计制造新型亚微米器件及电路的一种有效的方法。     

Ultrathin Si Thin-Film Transistor on Glass

We have studied the fabrication of ultrathin single-crystalline-silicon thin-film transistors (TFTs) on glass. The single-crystalline Si layer was transferred to glass by hydrogen implantation and anodic bonding. The thickness of the silicon-on-glass (SiOG) was controlled down to 10 nm by dry etching. The p-channel SiOG TFTs with 10-nm-thick Si exhibited the field-effect mobility of 134.9 $hbox{cm}^{2}/hbox{V}cdot hbox{s}$, threshold voltage of $-$1.5 V, and gate voltage swing of 0.13 V/dec. The TFTs were found to be stable against gate bias stress of $+$30 or $-$30 V.      

Ultrathin HfO2 gate dielectrics on partially strain compensated SiGeC/Si heterostructure

Ultrathin HfO₂ gate dielectrics have been deposited on strain-compensated Si_0.69Ge_0.3C_0.01 layers by rf magnetron sputtering. X-ray diffraction spectra show the films to be polycrystalline having both monoclinic and tetragonal phases. The formation of an interfacial layer has been observed by high-resolution transmission electron microscopy. Secondary ion mass spectroscopy and Auger electron spectroscopy analyses show the formation of an amorphous Hf-silicate interfacial layer between the deposited oxide and SiGeC films. The average concentration of Ge at the interfacial layer is found to be 2–3 at%. The leakage current density of HfO₂ gate dielectrics is found to be several orders of magnitude lower than that reported for thermal SiO₂ with the same equivalent thickness.     

新型薄膜SOI高压MOSFET的研制

研制了两种薄膜SOI高压MOSFET,一种是一般结构,另一种是新的双漂移区结构.两者的栅宽均为760μm,有源区面积为8.58×10-2mm2,测试表明其击穿电压分别为17V和26V,导通电阻分别为80Ω和65Ω.     

新型薄膜SOI高压MOSFET的研制

研制了两种薄膜SOI高压MOSFET,一种是一般结构,另一种是新的双漂移区结构.两者的栅宽均为76 0μm,有源区面积为8.5 8×10 - 2 m m2 ,测试表明其击穿电压分别为17V和2 6 V,导通电阻分别为80Ω和6 5Ω.