A 1-V 10-MHz clock-rate 13-bit CMOS ΔΣ modulator usingunity-gain-reset op amps

The problem of low-voltage operation of switched-capacitor circuits is discussed, and several solutions based on using unity-gain-reset of the opamps are proposed. Due to the feedback structure, the opamps do not need to be switched off during the reset phase of the operation, and hence can be clocked at a high rate. A low-voltage ΔΣ modulator, incorporating pseudodifferential unity-gain-reset opamps, is described. A test chip, realized in a 0.35-μm CMOS process and clocked at 10.24 MHz, provided a dynamic range of 80 dB and a signal-to-noise+distortion (SNDR) ratio of 78 dB for a 20-kHz signal bandwidth, and a dynamic range of 74 dB and SNDR of 70 dB for a 50-kHz bandwidth, with a 1-V supply voltage     

A delta-sigma modulator for a 1-bit digital switching amplifier

A seventh-order single-loop single-bit delta-sigma modulator for a 1-bit digital audio switching amplifier is presented. To achieve high SNR and ensure the modulator stability for a large input range, the positions of the modulator loop filter poles and zeros are optimized, and a feedback comparator is used. A test chip was fabricated in a 0.35-/spl mu/m CMOS process with optional 5-V transistors. The modulator achieves an SNR of 111 dB and 0.0015-% THD+N over the audio band. The normalized maximum allowable input range is 0.89. There are two modulators on one chip, one for each left and right audio channel. The isolation between both channels is over 135 dB. The chip area is 12.6 mm/sup 2/ and it draws 60 mA from a 5-V supply.     

A 0.5-GHz CMOS digital RF memory chip

In the application of digital RF memory (DRFM) chips for radar jamming, an RF signal is sampled, stored in random access memory (RAM) and later recreated from the stored data. A CMOS (l/SUB eff/=1 /spl mu/m) DRFM chip is described that integrates static RAM, control circuitry, and two channels of shift registers on a single chip. The sample rate achieved was 0.5 GHz. VLSI density was made possible by the low-power dissipation of quiescent CMOS circuits. An 8K RAM prototype chip has been built and tested.     

Direct digital-RF amplitude modulator in CMOS 90nm

Two different wireless transmitter topologies based on an direct digital-RF amplitude modulator (DAM) are presented: a polar modulator and a direct digital-RF IQ modulator prototype. The DAM consists of 255 basic cells digitally activated by an 8-bit amplitude code to shape a non-constant envelope RF output. The cells are segment-addressed resulting in a very compact 0.007 mm² chip area in CMOS 90nm. In order to reduce the spectral images due to the discrete-time to continuous-time conversion a 2-fold interpolation has been implemented. The DAM reaches a peak output power of 5 dBm at 2.45 GHz with 23% drain efficiency. Both direct digital modulator architectures fulfill WLAN 802.11g linearity constrains at 2.45 GHz.     

一种低功耗10位流水线结构的CMOS A/D转换器的设计

本文设计了一种可满足视频速度应用的低电压低功耗10位流水线结构的CMOS A/D转换器.该转换器由9个低功耗运算放大器和19个比较器组成,采用1.5位/级共9级流水线结构,级间增益为2并带有数字校正逻辑.为了提高其抗噪声能力及降低二阶谐波失真,该A/D转换器采用了全差分结构.全芯片模拟结果表明,在3V工作电压下,以20MHz的速度对2MHz的输入信号进行采样时,其信噪失调比达到53dB,功率消耗为28.7mW.最后,基于0.6μm CMOS工艺得到该A/D转换器核的芯片面积为1.55mm2.     

A wide-band microwave light modulator

An experimental potassium dihydrogen phosphate (KDP) light modulator with a 10 percent (half-m) bandwidth at 6 GHz is described. When arranged for amplitude modulation, a modulation depth of 40 percent was obtained with 10 watts of input power at band center. With a different optical arrangement, phase modulation is also possible. The modulator uses a ring-plane traveling-wave circuit with cylindrical KDP crystals filling the space inside the rings. The crystals are used in the longitudinal mode, i.e., with the light beam along the optic axis, thus avoiding some of the thermal problems associated with transverse node operation. The circuit provides adequate cooling for the crystals and CW or pulsed operation at average RF levels of 10 watts is possible. Measurements indicate that the limitation in bandwidth is due mainly to the dispersion of the circuit and that with suitable modifications bandwidths of 20 percent are quite feasible.     

A CMOS stereo 16-bit D/A converter for digital audio

A complete monolithic stereo 16-bit D/A converter primarily intended for use in compact-disc players and digital audio tape recorders is described. The D/A converter achieves 16-bit resolution by using a code-conversion technique based upon oversampling and noise shaping. The band-limiting filters required for waveform smoothing and out-of-band noise reduction are included. Owing to the oversampling principle most applications will require only a few components for an analog postfilter. The converter has a linear characteristic and linear phase response. The chip is processed in a 2-/spl mu/m CMOS process and the die size is 44 mm/SUP 2/. Only a single 5-V supply is needed.     

A 13-bit, 1.4-MS/s sigma-delta modulator for RF baseband channelapplications

A 13-bit, 1.4-MS/s, sixth-order cascaded sigma-delta modulator oversampling at 16 X is implemented in a 0.72 μm complementary metal-oxide-semiconductor process for use in the baseband path of a radio-frequency receiver. The modulator achieves 77 dB of dynamic range and dissipates 81 mW from a 3.3 V supply. It is characterized for the blocking and intermodulation requirements of a cordless telephone application     

A low-power stereo 16-bit CMOS D/A converter for digital audio

A low-power 16-bit CMOS D/A (digital/analog) converter for portable digital audio is described. The converter is based on current division. To guarantee monotonicity and a good small-signal reproduction, a dynamic segmentation technique is used. A geometric averaging technique is used to minimize the harmonic distortion of the converter at high signal levels. The dynamic range is 95 dB. The circuit operates in a time-multiplex mode at a sample frequency of 44 kHz in a power supply range of 2.5-5 V and has a power consumption of 15 mW. A 2-μm CMOS technology is used and the active chip area is 5 mm²      

将RF信号转换为数字信号的CMOS转换器

从频率计数与合成到传感器信号调整等很多应用都需要将RF信号转换为数字逻辑电平。在这些情况下,设计者一般采用一个高速电压比较器完成RF到数字信号的转换工作。由于电压比较器具有高增益,它们一般有很好的灵敏度,但也会带来一些问题。高速比较器价格高,很难找到现成的商品,并且易于被快速淘汰。     

A digitally self-calibrating 14-bit 10-MHz CMOS pipelined A/Dconverter

A digitally self-calibrating pipelined analog-to-digital converter (ADC) featuring 1.5-bit/stage structure is presented. The integral (INL) and differential nonlinearity (DNL) errors are removed using a novel digital calibration algorithm, which also eliminates missing codes that can occur with other calibration algorithms near the extremes of the input range. After calibration, the measured DNL is ±0.6 LSB and the INL is ±2.5 LSB at the 14-bit level. Sampling at a 10-MHz rate, the chip dissipates 220 mW and (post-calibration) yields a signal-to-noise ratio of 77 dB and a spurious-free dynamic range of 95 dB with 4.8-MHz sine wave input signal. The chip is fabricated in 0.5-μm CMOS double-poly double-metal process, measures 3.8 mm × 3.3 mm (150 mil × 130 mil), and operates from a single 5-V supply     

A general purpose differential digital modulator implementationincorporating a direct digital synthesis method

A highly versatile digital modulator that uses a direct digital synthesis method to perform signal modulation is described. In contrast to the customary methods of implementing I-Q modulation schemes utilizing in-phase and quadrature branches, this design approach is based on directly accessing many of the digitally stored carrier modulating symbols according to the information bearing input signals. Apart from the digital-to-analog converter, all the previous stages are digital. To demonstrate the concept, a differential 16-QAM modulator was implemented. The technique lends itself to VLSI implementation. It can be considered as a digital implementation of a digital modulator     

应用于高速CMOS图像传感器的10比特列并行循环式ADC

This paper presents a high-speed column-parallel cyclic analog-to-digital converter(ADC) for a CMOS image sensor.A correlated double sampling(CDS) circuit is integrated in the ADC,which avoids a stand-alone CDS circuit block.An offset cancellation technique is also introduced,which reduces the column fixed-pattern noise(FPN) effectively.One single channel ADC with an area less than 0.02 mm~2 was implemented in a 0.13μm CMOS image sensor process.The resolution of the proposed ADC is 10-bit,and the conversion rate is 1.6 MS/s. The measured differential nonlinearity and integral nonlinearity are 0.89 LSB and 6.2 LSB together with CDS, respectively.The power consumption from 3.3 V supply is only 0.66 mW.An array of 48 10-bit column-parallel cyclic ADCs was integrated into an array of CMOS image sensor pixels.The measured results indicated that the ADC circuit is suitable for high-speed CMOS image sensors.     

A 10-bit 200-MHz CMOS video DAC for HDTV applications

This paper describes a 10-bit 200-MHz CMOS current steering digital-to-analog converter (DAC) for HDTV applications. The proposed 10-bit DAC is composed of a unit decoded matrix for 6 MSBs and a binary weighted array for 4 LSB’s, considering linearity, power consumption, routing area, and glitch energy. A new switching scheme for the unit decoded matrix is developed to improve linearity further. Cascade current sources and differential switches with deglitch latch improve dynamic performance. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.3 LSB and 0.2 LSB, respectively. The converter achieves a spurious-free dynamic range (SFDR) of above 55 dB over a100-MHz bandwidth and low glitch energy of 1.5 pVs. The circuit is fabricated in a 0.25 μm CMOS process and occupies 0.91 mm². When operating at 200 M Sample/s, it dissipates 82 mW from a 3.3 V power supply.     

A micropower amplitude modulator

Amplitude modulation using micropower transistors is often required for many applications in communications and instrumentation. A micropower current-gain block with its hFEstabilized over several ICdecades can be used with additional circuitry for this purpose. This letter describes such a modulator and its operating characteristics.     

A wide-band linear amplitude modulator for polar transmitters based on the concept of interleaving delta modulation

Polar transmission techniques offer the capability of multimode wireless transmission and the potential for significant efficiency gains over solutions based on I/Q. However, polar transmitters are difficult to implement because of the wide bandwidths associated with the phase and envelope signals. Moreover, accurate synchronization between envelope and phase components is essential in minimizing distortion. A concept named Interleaving Delta Modulation (iDM) is proposed to overcome some of the issues associated with polar transmission. IDM minimizes distortion and improves efficiency by replacing a stream of fast drive pulses to the amplitude modulator with a parallel stream of slower pulses. Circuitry to implement iDM has been designed, fabricated, and measured in 0.35-/spl mu/m CMOS technology.     

A 14-bit high-temperature /spl Sigma//spl Delta/ modulator in standard CMOS

Experimental verification is given for the use of /spl Sigma//spl Delta/ modulation for high-temperature applications (/spl ges/approximately 150/spl deg/C) in a standard CMOS process. Switched-capacitor circuits are used to implement a second-order single-stage and a third-order 2-1 MASH /spl Sigma//spl Delta/ modulator with single-bit quantization. The two modulators have an oversampling ratio of 256 with an input signal bandwidth of 500 Hz. The modulators were fabricated in a 1.5-/spl mu/m standard CMOS technology. A fully differential signal path and near minimum sized switches are used to mitigate the effect of large junction-to-substrate leakage current present at high temperatures. Experimental results show both modulators are capable of over 14 bits of resolution at 225/spl deg/C and over 13 bits of resolution at 255/spl deg/C. Results show that the single-stage modulator is more resistant to high-temperature circuit impairment than is the MASH cascaded structure.     

A wide-band,high-precision CMOS rectifier

A novel architecture for a precision rectifier is introduced. A new arrangement of a MOS switch and an amplifier has been developed for better precision and higher switching speed. The precision rectifier can rectify signals as low as 10 mV and frequencies up to 20 MHz with excellent linearity.     

一种基于FPGA的直接数字射频上变频方案

传统模拟器件实现射频(RF)上变频方法存在硬件复杂度高,灵活性差,功耗大等缺点。随着半导体器件的发展,软件无线电要求将上变频中射频或中频的信号处理尽量往基带数字信号处理靠拢。本文利用多相滤波器原理,提出一种基于现场可编程门阵列(FPGA)的直接数字RF上变频架构和实施方案,并且通过软硬件仿真验证了该方案的可行性。