Short channel epi-MOSFET model

We show how threshold voltages and the electric field perpendicular to a channel are controlled by varying the thickness of the epi-layer in long epitaxial channel MOSFET devices (epi-MOSFETs). Using our proposal of a two-region polynomial potential distribution and a universal boundary condition that effectively expresses the variation of depletion width along a channel, we calculated the two-dimensional (2-D) potential distribution. We also derived a threshold voltage model for short channel epi-MOSFETs. Our model reproduces the numerical data of sub-0.1-/spl mu/m gate length devices, and predicts that the short channel immunity of these devices is not as good as predicted by the previous model. However, their performance is superior to that of double-gate SOI MOSFETs.     

Threshold voltage of narrow channel field effect transistors

A new effect associated with Metal-Oxide-Silicon Field-Effect-Transistors (MOS-FET's) is presented in this paper. MOS-FET's show an increase of threshold voltage with decreasing ratio of channel width to gate depletion width. This narrow channel effect is explained by means of geometrical edge effects. With decreasing channel width the transition from the field oxide depletion region to the gate oxide depletion region becomes comparable to the gate width and cannot be neglected in the derivation of the threshold voltage equation.A theoretical model is given to explain the influence of decreasing channel width on the threshold voltage as well as on other electrical parameters. This theoretical model is in good agreement with experimental results given in this paper.     

Scanning electron microscope measurements on short channel MOS transistors

Several methods are discussed for measurement of PN junction shapes and channel field conditions in short (≈1 μm gate lengths) MOS transistors. A special test structure for short channel MOS transistor measurements with a scanning electron microscope (SEM) is presented. Secondary electron measurements on lased scribed and angle lapped and stained PN junctions are discussed. Methods for sectional imaging of electrically active, cleaved transistors using electron-beam-induced current (EBIC) are presented. An approximate quantitative model of the EBIC imaging process is presented which allows the calculation of current in a MOS transistor. Using this model the current is shown to be dominated by electric field effects in the depletion region of the transistor.     

An analytic and accurate model for the threshold voltage of short channel MOSFETs in VLSI

Based on the two-dimensional Poisson equation, the surface potential distribution along the surface channel of a MOSFET has been analytically derived by assuming negligible source and drain junction depths and its minimum potential is then used to determine the threshold voltage. The existence of a minimum surface potential point along the channel of a MOSFET under an applied drain bias is consistent with the numerical results of the two-dimensional analysis. The effects of finite source and drain junction depths have been elegantly included by modifying the depletion capacitance under the gate and the resulted threshold voltage model has been compared to the results of the two-dimensional numerical analysis. It has been shown that excellent agreement between these results has been obtained for wide ranges of substrate doping, gate oxide thickness, channel length (< 1 μm), substrate bias, and drain voltage. Moreover, comparisons between the developed model and the existing experimental data have been made and good agreement has been obtained. The major advantages of the developed model are that no iterations and no adjustable fitting parameters are required. Therefore, this simple and accurate threshold voltage model will become a useful design tool for ultra short channel MOSFETs in future VLSI implementation.     

A geometrical model of the threshold voltage of short and narrow channel MOSFETs

A simple geometrical model allows the calculation of the threshold voltage of short and narrow channel MOSFETs as a function of gate length, gate width, source and drain depth, substrate voltage and source drain voltage. Input parameters of the program are the customary values such as oxide thickness and, furthermore, an effective impurity concentration in the field region. The flat band voltage and the effective impurity concentration in the channel region can be calculated by a modified SUPREM program.     

Characteristics of buried-channel pMOS devices with shallowcounter-doped layers fabricated using channel preamorphization

Channel preamorphization, which is a technique used for shallow boron counter doping of pMOSFETs to suppress short-channel effects, improves gate oxide quality in MOS capacitors with the field-edge structure. This indicates that the source of gate oxide quality degradation is located near the field oxide edge, and is eliminated in channel preamorphization process by the gettering effects of defects induced near the original amorphous/crystalline interface. The leakage current of junction diodes, on the other hand, is increased by channel preamorphization. The leakage current increases because the defects near the original amorphous/crystalline interface act as generation centers in the depletion layers. This problem will be overcome by increasing the preamorphization depth. Hot carrier immunity of pMOSFETs is improved by channel preamorphization, especially in short-channel devices     

深亚微米槽栅PMOSFET结构参数对其抗热载流子效应和短沟道抑制作用的影响

基于流体动力学能量输运模型 ,利用二维仿真软件 Medici对深亚微米槽栅 PMOS器件的结构参数 ,如凹槽拐角、负结深、沟道和衬底掺杂浓度对器件抗热载流子特性和短沟道效应抑制作用的影响进行了研究 .并从器件内部物理机理上对研究结果进行了解释 .研究发现 ,随着凹槽拐角、负结深的增大和沟道杂质浓度的提高 ,器件的抗热载流子能力增强 ,阈值电压升高 ,对短沟道效应的抑制作用增强 .而随着衬底掺杂浓度的提高 ,虽然器件的短沟道抑制能力增强 ,但抗热载流子性能降低     

Analysis and impact of process variability on performance of junctionless double gate VeSFET

This paper presents an in-depth analysis of junctionless double gate vertical slit FET (JLDG VeSFET) device under process variability. It has been observed that junctionless FETs (JLDG VeSFET) are significantly less sensitive to many process parameter variations due to their inherent device structure and geometric properties. Sensitivity analysis reveals that the slit width, oxide thickness, radius of the device, gate length and channel doping concentration imperceptibly affect the device performance of JLDG VeSFET in terms of variation in threshold voltage, on current, off current and subthreshold slope (Ssub) as compared to its junction based counterpart i.e. MOSFET, because various short channel effects are well controlled in this device. The maximum variation in off current for JLDG VeSFET due to variation in different devices parameters is 5.6% whereas this variation is 38.8% for the MOS junction based device. However, variation in doping concentration in the channel region displays a small deviation in the threshold voltage and on current characteristics of the MOSFET device as compared to JL DG VeSFET.     

Modeling and simulation of a nanoscale three-region tri-material gate stack (TRIMGAS) MOSFET for improved carrier transport efficiency and reduced hot-electron effects

Two-dimensional (2-D) analytical modeling for a novel multiple region MOSFET device architecture-Tri-Material Gate Stack MOSFET-is presented, which shows reduced short-channel effects at short gate lengths. Using a three-region analysis in the horizontal direction and a universal depletion width boundary condition, the 2-D potential and electric field distribution in the channel region along with the threshold voltage of the device are obtained. The proposed model is capable of modeling electrical characteristics like surface potential, electric field, and threshold voltage of various other existent MOSFET structures like dual-material-gate, electrically induced shallow junction/straddle-gate (side-gate), and single-material-gate MOSFETs, with and without the gate stack architecture. The 2-D device simulator ATLAS is used over a wide range of parameters and bias conditions to validate the analytical results.     

槽栅NMOSFET结构与性能仿真

基于流体动力学能量输运模型 ,利用二维器件模拟器 MEDICI对深亚微米槽栅 NMOSFET器件的结构参数 ,如结深、凹槽拐角及沟道长度等对器件性能的影响进行了仿真研究 ,并与相应的常规平面器件特性进行了对比 .研究表明在深亚微米范围内 ,槽栅器件能够很好地抑制短沟道效应和热载流子效应 ,但电流驱动能力较平面器件小 ,且器件性能受凹槽拐角和沟道长度的影响较显著     

Optically-controlled ion-implanted GaAs MESFET characteristic withopaque gate

An analytical modelling has been carried out for an ion-implanted GaAs MESFET having a Schottky gate opaque to incident radiation. The radiation is absorbed in the device through the spacings of source, gate, and drain unlike the other model where gate is transparent/semitransparent. Continuity equations have been solved for the excess carriers generated in the neutral active region, the extended gate depletion region and the depletion region of active (n) and substrate (p) junction. The photovoltage across the channel and the p-layer junction and that across the Schottky junction due to generation in the arc region of the gate depletion layer are the two important controlling parameters. The I-V characteristics and the transconductance of the device have been evaluated and discussed     

A subthreshold surface potential model for short-channel MOSFET taking into account the varying depth of channel depletion layer due to source and drain junctions

An analytical subthreshold surface potential model for short-channel MOSFET is presented. In this model, the effect of varying depth of the channel depletion layer on the surface potential has been considered. The effect of the depletion layers around the source and drain junctions on the surface potential, which is very important for short channel devices is included in this model. With this, the drawback of the existing models that assume a constant channel depletion layer thickness is removed resulting in a more accurate prediction of the surface potential. A pseudo-two-dimensional method is adopted to retain the accuracy of two-dimensional analysis yet resulting in a simpler manageable one-dimensional analytical expression. The subthreshold drain current is also evaluated utilizing this surface potential model.     

A calibrated model for the subthreshold operation of a short channel MOSFET including surface states

Describes a simple two-dimensional subthreshold model for short channel MOSFET's. The effects of surface state density are also included in the model. A regional charge density approximation was used in the solution of Poisson's equation and an analytical solution of the continuity equation in two dimensions was derived. Excessive computations are avoided in the present model; this was made possible by the use of a valid regional charge approximation. The model was experimentally verified by performing measurements on short channel devices. The model was calibrated from measurements on a long channel device which was present on the same silicon chip. Results are presented for the subthreshold leakage current as a function of substrate bias, polysilicon gate length, diffusion depth and surface state density.     

STUDY ON THE RELATION BETWEEN STRUCTURE AND HOT CARRIER EFFECT IMMUNITY FOR DEEP SUB-MICRON GROOVED GATE NMOSFET''''s

Grooved gate structure Metal-Oxide-Semiconductor (MOS) device is considered as the most promising candidate used in deep and super-deep sub-micron region, for it can suppress hot carrier effect and short channel effect deeply. Based on the hydrodynamic energy transport model, using two-dimensional device simulator Medici, the relation between structure parameters and hot carrier effect immunity for deep-sub-micron N-channel MOSFET's is studied and compared with that of counterpart conventional planar device in this paper. The examined structure parameters include negative junction depth, concave corner and effective channel length. Simulation results show that grooved gate device can suppress hot carrier effect deeply even in deep sub-micron region. The studies also indicate that hot carrier effect is strongly influenced by the concave corner and channel length for grooved gate device. With the increase of concave corner, the hot carrier effect in grooved gate MOSFET decreases sharply, and with the redu     

SiC隐埋沟道MOS结构夹断模式下的C-V特性畸变

用数值和解析的方法研究了SiC隐埋沟道MOS结构夹断模式下C-V特性的畸变.隐埋沟道MOSFET中存在一个pn结,在沟道夹断以后,半导体表面耗尽区和pn结耗尽区连在一起,这时总的表面电容是半导体表面耗尽区电容和pn结电容的串联,使埋沟MOS结构的C-V特性发生畸变.文中通过求解泊松方程,用解析的方法分析了这种畸变发生的物理机理,并对栅电容进行了计算,计算结果与实验结果符合得很好.     

An analytic threshold-voltage model for short-channel enhancement mode n-channel MOSFETs with double boron channel implantation

This paper presents an analytic threshold-voltage model for n-channel MOSFETs with double boron channel implantation, in which the implanted boron profile in the substrate is approximated by a triple-step profile. The surface potential at strong inversion has been calculated from the condition of equal rate change of depletion layer charge density and inversion layer charge density with respect to the surface potential. The built-in voltage of the high-low junction in a triple-step profile has been correctly included in calculating the surface potential and maximum depletion width at strong inversion. This consideration removes the discontinuities of the threshold voltage with respect to the applied back-gate bias as the maximum depletion width passes through the high-low junction. Based on the above considerations, an analytic threshold-voltage model for short-channel MOSFETs with a triple-step profile in the substrate has been developed by using the modified charge sharing scheme. The geometric factors of the charge sharing scheme have been incorporated into the developed threshold-voltage model by means of the depletion charge superposition which also guarantees continuous threshold voltage change as the back-gate bias is continuously applied. Moreover, the developed threshold-voltage model has been compared with the experimental results of fabricated devices. Satisfactory agreement between these comparisons has been obtained for wide ranges of effective channel lengths and back-gate biases.     

High channel mobility in normally-off 4H-SiC buried channel MOSFETs

We have fabricated buried channel (BC) MOSFETs with a thermally grown gate oxide in 4H-SiC. The gate oxide was prepared by dry oxidation with wet reoxidation. The BC region was formed by nitrogen ion implantation at room temperature followed by annealing at 1500°C. The optimum doping depth of the BC region has been investigated. For a nitrogen concentration of 1×10¹⁷ cm^-3, the optimum depth was found to be 0.2 μm. Under this condition, a channel mobility of 140 cm²/Vs was achieved with a threshold voltage of 0.3 V. This channel mobility is the highest reported so far for a normally-off 4H-SiC MOSFET with a thermally grown gate oxide     

Substrate bias effect of epitaxial delta-doped channel MOS transistor for low-power applications

Conventional planar transistor shows shrinking substrate bias effect at scaled technology. On the other hand, epitaxial delta-doped channel (EδDC) transistor shows substantial amount of substrate bias effect even at 16-nm channel length. This paper unveils the physics behind the substrate bias effect of an n-channel EδDC transistor through Technology Computer Aided Design simulation with analytical justifications. The depletion width for an EδDC transistor very weakly depends upon the applied substrate bias, and with scaling down of channel length, the depletion width insignificantly gets widened. The substrate control over the channel is high so that significant amount of substrate depletion charge terminates on the gate, instead of on the source and the drain. The degradation of threshold voltage roll off and drain-induced barrier lowering coefficient with the increase of substrate bias, is less for the EδDC transistor, compared to that of a conventional halo free transistor. The dependence of the substrate bias sensitivity on the thickness of the low-doped epitaxial layer and concentration of the high-doped layer is explored. The effects of reverse substrate bias on leakage power dissipation and intrinsic delay of EδDC and conventional transistors are discussed.     

A new field dependent mobility model for high frequency channel thermal noise of deep submicron RFCMOS

In this paper, a new field dependent effective mobility model including the drain-induced vertical field effect (DIVF) is presented to calculate the channel thermal noise of short channel MOSFETs operating at high frequencies. Based on the new channel thermal noise model, the simulated channel thermal noise spectral densities have been compared to the channel thermal noise directly extracted from noise measurements on devices fabricated using GLOBALFOUNDRIES’ 0.13 μm RFCMOS technology. The comparison has been done across different channel length, finger width and number of finger for different frequencies, gate biases and drain biases. Excellent agreement between simulated and extracted noise data has shown that the proposed model is scalable over different dimensions and operating conditions. The proposed model is simple and can be easily implemented in a circuit simulation environment.     

凹槽栅MOSFET凹槽拐角的作用与影响研究

短沟道效应是小尺寸ＭＯＳＦＥＴ中很重要的物理效应之一，凹槽栅ＭＯＳＦＥＴ对短沟道效应有很强的抑制能力，通过对凹槽栅ＭＯＳＦＥＴ结构，特性的研究，发现凹槽拐角对凹槽栅ＭＯＳＦＥＴ的阈值电压及特性有着显著的影响，凹槽拐角处的阈值电压决定着整个凹槽栅ＭＯＳＦＥＴ的阈值电压，凹槽拐角的曲率半径凹槽ＭＯＳＦＥＴ一个重要的结构参数，通过对凹槽拐角的曲率半径，源漏结深及沟道掺杂浓度进行优化设计，可使凹槽栅ＭＯＳ