共查询到20条相似文献,搜索用时 10 毫秒
1.
Kye-Hyun Kyung Hi-Choon Lee Ki-Whan Song Ho-Sung Song Keewook Jung Joon-Seo Moon Byoung-Sul Kim Sung-Burn Cho Changhyun Kim Soo-In Cho 《Solid-State Circuits, IEEE Journal of》2001,36(5):735-743
A 2.5-V 288-Mb packet-based DRAM with 32 banks and 18-DQ organization architecture achieving a peak bandwidth of 2.0-GB/s at V DD=2.25 V and T=100°C has been developed using (1) an area- and performance-efficient chip architecture with a mixture of high-speed interface circuits with DRAM peripheral circuits to increase cell efficiency; (2) a multilevel controlled bitline equalizing scheme and a distributed sense amplifier driving scheme to enhance DRAM core timing margin while increasing the number of cells per wordline for cell efficiency over the previous subwordline driving scheme; (3) a flexible column redundancy scheme with multiple fuse boxes instead of excessive spare memory cell arrays for 143 internal I/O architecture; and (4) optimized I/O circuits and pin parasitic design including pad and package to maximize the operating frequency 相似文献
2.
Jei-Hwan Yoo Chang-Hyun Kim Kyu-Chan Lee Kye-Hyun Kyung Seung-Moon Yoo Jung-Hwa Lee Moon-Hae Son Jin-Man Han Bok-Moon Kang Ejaz Haq Sang-Bo Lee Jai-Hoon Sim Joung-Ho Kim Byung-Sik Moon Keum-Yong Kim Jae-Gwan Park Kyu-Phil Lee Kang-Yoon Lee Ki-Nam Kim Soo-In Cho Jong-Woo Park Hyung-Kyu Lim 《Solid-State Circuits, IEEE Journal of》1996,31(11):1635-1644
This paper describes a 32-bank 1 Gb DRAM achieving 1 Gbyte/s (500 Mb/s/DQ pin) data bandwidth and the access time from RAS of 31 ns at V cc=2.0 V and 25°C. The chip employs (1) a merged multibank architecture to minimize die area; (2) an extended small swing read operation and a single I/O line driving write scheme to reduce power consumption; (3) a self-strobing I/O schemes to achieve high bandwidth with low power dissipation; and (4) a block redundancy scheme with increased flexibility. The nonstitched chip with an area of 652 mm 2 has been fabricated using 0.16 μm four-poly, four-metal CMOS process technology 相似文献
3.
Yong-Weon Jeon Young-Hyun Jun Suki Kim 《Electronics letters》2000,36(11):940-942
A new column redundancy scheme is presented that can minimise the die area overhead by repair circuits and also achieve fast access speed in high density dynamic random access memories (DRAMs) with wide data widths. The proposed scheme has a large redundancy-area-unit (RAU) which operates a flexible column redundancy scheme that consecutively shifts RDQ (redundant I/O) to neighbouring MDQ (main I/O) without any speed penalty. By using the proposed mapping fuse algorithm. The number of fuses required to store the fail bit address can be reduced, and the chip area reduced. 相似文献
4.
Ki-Won Lee Joo-Hwan Cho Byoung-Jin Choi Geun-Il Lee Ho-Don Jung Woo-Young Lee Ki-Chon Park Yong-Suk Joo Jae-Hoon Cha Young-Jung Choi Moran P.B. Jin-Hong Ahn 《Solid-State Circuits, IEEE Journal of》2007,42(11):2369-2377
Three circuit techniques for a 1.5 V, 512 Mb graphic DDR4 (GDDR4) SDRAM using a 90-nm DRAM process have been developed. First, a dual-clock system increases clocking accuracy and expands internal timing margins for harmonious core operation regardless of external clock frequency. Second, a four-phase data input strobe scheme helps to increase the input data valid window. Third, a fully analog delay-locked loop which provides a stable I/O clock and has 31.67 ps peak-to-peak jitter characteristics is designed. On the basis of these circuit techniques, the data rate is 3.2 Gbps/pin, which corresponds to 12.8 Gbps in times32 GDDR4-based I/O. Also, a multidivided architecture consisting of four independent 128 Mb core arrays is designed to reduce power line and output noise. 相似文献
5.
Jae-Goo Lee Young-Hyun Jun Chilgee Lee Bai-Sun Kong 《Electronics letters》2000,36(24):1996-1997
A novel I/O divided column redundancy (IDCR) scheme that can improve the effectiveness of repair and minimise the overhead of the die area is presented. The IDCR scheme has greater flexibility than conventional schemes in multiple I/O DRAMs. Since an IDCR can share neighbouring redundant column lines (RCLs), the RCLs of neighbouring I/O blocks can be used to repair the defective column lines of a self-block. This work also shows that the IDCR scheme improves the data access speed of normal column lines or redundant column lines by reducing the data bus loading 相似文献
6.
Hara T. Fukuda K. Kanazawa K. Shibata N. Hosono K. Maejima H. Nakagawa M. Abe T. Kojima M. Fujiu M. Takeuchi Y. Amemiya K. Morooka M. Kamei T. Nasu H. Chi-Ming Wang Sakurai K. Tokiwa N. Waki H. Maruyama T. Yoshikawa S. Higashitani M. Pham T.D. Yupin Fong Watanabe T. 《Solid-State Circuits, IEEE Journal of》2006,41(1):161-169
An 8-Gb multi-level NAND Flash memory with 4-level programmed cells has been developed successfully. The cost-effective small chip has been fabricated in 70-nm CMOS technology. To decrease the chip size, a one-sided pad arrangement with compacted core architecture and a block address expansion scheme without block redundancy replacement have been introduced. With these methods, the chip size has been reduced to 146 mm/sup 2/, which is 4.9% smaller than the conventional chip. In terms of performance, the program throughput reaches 6 MB/s at 4-KB page operation, which is significantly faster than previously reported and very competitive with binary Flash memories. This high performance has been achieved by the combination of the multi-level cell (MLC) programming with write caches and with the program voltage compensation technique for neighboring select transistors. The read throughput reaches 60 MB/s using 16I/O configuration. 相似文献
7.
Yi Tang Kuang-Wei Cheng Gupta S. Paramesh J. Allstot D.J. 《IEEE transactions on circuits and systems. I, Regular papers》2008,55(3):817-827
A complex analog-to-digital converter (ADC) intended for digital intermediate frequency (IF) receiver applications digitizes analog signals at IFs with excellent power/bandwidth efficiency. However, it is vulnerable to mismatches between its in-phase and quadrature (I/Q) paths that can dramatically degrade its performance. The proposed solution mitigates I/Q mismatch effects using a complex sigma-delta (SigmaDelta) modulator cascaded with 9-bit pipeline converters in each of the I and Q paths. The quantization noise of the first stage complex modulator is eliminated using an adaptive scheme to calibrate finite-impulse response digital filters in the digital noise-cancellation logic block. Although low-pass SigmaDelta cascade ADCs are widely used because of their inherent stability and high-order noise shaping, the complex bandpass cascade architecture introduced herein maintains these advantages and doubles the noise shaping bandwidth. Digital calibration also reduces the effects of analog circuit limitations such as finite operational amplifier gain, which enables high performance and low power consumption with high-speed deep-submicrometer CMOS technology. Behavioral simulations of the complex SigmaDelta/pipeline cascade bandpass ADC using the adaptive digital calibration algorithm predict a signal-to-noise ratio (SNR) of 78 dB over a 20-MHz signal bandwidth at a sampling rate of 160 MHz in the presence of a 1% I/Q mismatch. 相似文献
8.
Sungjoon Kim Kyeongho Lee Yongsam Moon Deog-Kyoon Jeong Yunho Choi Hyung Kyu Lim 《Solid-State Circuits, IEEE Journal of》1997,32(5):691-700
This paper describes an I/O scheme for use in a high-speed bus which eliminates setup and hold time requirements between clock and data by using an oversampling method. The I/O circuit uses a low jitter phase-locked loop (PLL) which suppresses the effect of supply noise. Measured results show peak-to-peak jitter of 150 ps and r.m.s. jitter of 15.7 ps on the clock line. Two experimental chips with 4-pin interface have been fabricated with a 0.6 μm CMOS technology, which exhibits the bandwidth of 960 Mb/s per pin 相似文献
9.
Ryu C. Chung D. Lee C. Kim J. Bae K. Yu J. Lee S. 《Microwave and Wireless Components Letters, IEEE》2006,16(12):651-653
Cascaded repeaters are indispensable circuit elements in conventional on-chip clock distribution networks due to heavy loss characteristics of on-chip global interconnections. However, cascaded repeaters cause significant jitter and skew problems in clock distribution networks when they are affected by power supply switching noise generated by digital logic blocks located on the same die. In this letter, we present a new three-dimensional (3-D) stacked-chip star-wiring interconnection scheme to make a clock distribution network free from both on-chip and package-level power supply noise coupling. The proposed clock distribution scheme provides an extremely low-jitter and low-skew clock signal by replacing the cascaded repeaters with lossless star-wiring interconnections on a 3-D stacked-chip package. We have demonstrated a 500-MHz input/output (I/O) clock delivery with 34-ps peak-to-peak jitter and a skew of 11ps, while a conventional I/O clock scheme exhibited a 146-ps peak-to-peak jitter and a 177-ps skew in the same power supply noise environment 相似文献
10.
Kim C.H. Lee J.H. Lee J.B. Kim B.S. Park C.S. Lee S.B. Lee S.Y. Park C.W. Roh J.G. Nam H.S. Kim D.Y. Lee D.Y. Jung T.S. Yoon H. Cho S.I. 《Solid-State Circuits, IEEE Journal of》1998,33(11):1703-1710
A 64-Mbit bidirectional data strobed, double-data-rate SDRAM achieves a peak bandwidth of 2.56 GByte/s on a 64-bit-channel, 256-MByte memory system at Vcc=3.3 V and T=25°C. The circuit features are: (1) a bidirectional data strobing scheme to eliminate the clock-related skews of I/O data in a multimodule system, (2) a low-power delay-locked loop having a wide range of locking frequency (40-160 MHz) with fast access time and minimal variations, and (3) a twisted data bussing architecture with minimized loading difference between I/O data paths and small chip-size overhead associated with the 2-bit prefetch operation 相似文献
11.
Tapani Tuikkanen Arto Kivi Timo Rahkonen 《Analog Integrated Circuits and Signal Processing》2002,30(1):7-14
An 8-bit, 50 MS/s pipeline converter is presented with peak SNR and SFDR of 43.1 dB and 52.5 dB, corresponding to effective number of bits of 6.9. The circuit is implemented in a 0.35 m CMOS process, the core area is 0.36 mm2 and its analog and digital current consumptions (including I/O buffers) are 6.2 mA and 4.5 mA from a 3 V supply. The low power consumption is achieved by using two banks of sampling capacitors (double sampling) and a mixed architecture giving 1+1+1+2+3 bits per stage. The mixed architecture means that a full ninth bit cannot be coded, but instead it is a employed as an almost 6 dB overdrive input range. The maximum allowable comparator errors in different architectures are calculated and the benefits of excess redundancy are discussed. 相似文献
12.
We implemented 72-Mb direct Rambus DRAM with new memory architecture suitable for multibank. There are two novel schemes: flexible mapping redundancy (FMR) technique and additional refresh scheme. This paper shows that multibank reduces redundancy area efficiency. But with the FMR technique, this 16-bank DRAM realizes the same area efficiency as a single-bank DRAM. In other words, FMR reduces chip area by 13%. This paper also describes that additional refresh scheme reduces data retention power to 1/4. Its area efficiency is about four times better than that of the conventional redundancy approach 相似文献
13.
14.
《Advanced Packaging, IEEE Transactions on》2009,32(2):237-247
15.
A new dynamic RAM (DRAM) signal sensing principle, a divided/shared bit-line (DSB) sensing scheme, is proposed. This sensing scheme provides folded bit-line sensing operation in a crosspoint-type memory cell array. The DSB scheme offers a high-density DRAM memory core with the common-mode array noise eliminated. A bit-line architecture based on this new sensing principle and its operation are demonstrated. A divided/pausing bit-line sensing (DIPS) scheme, which is an application of this DSB principle to the conventional folded bit-line type of memory cell arrangement, is also proposed. The DIPS architecture achieves complete pausing states for alternate bit lines throughout the active period. These alternate pausing bit lines shield the inter-bit-line coupling noise between active bit lines. Here the inter-bit-line coupling noise is eliminated by a slight architectural change to the conventional folded bit-line memory cell array. These new memory core design alternatives provide high-density DRAM memory cores suitable for the 64-Mb level and beyond. with the memory array noise reduced significantly 相似文献
16.
8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology 总被引:1,自引:0,他引:1
Uksong Kang Hoe-Ju Chung Seongmoo Heo Duk-Ha Park Hoon Lee Jin Ho Kim Soon-Hong Ahn Soo-Ho Cha Jaesung Ahn DukMin Kwon Jae-Wook Lee Han-Sung Joo Woo-Seop Kim Dong Hyeon Jang Nam Seog Kim Jung-Hwan Choi Tae-Gyeong Chung Jei-Hwan Yoo Joo Sun Choi Changhyun Kim Young-Hyun Jun 《Solid-State Circuits, IEEE Journal of》2010,45(1):111-119
An 8 Gb 4-stack 3-D DDR3 DRAM with through-Si-via is presented which overcomes the limits of conventional modules. A master-slave architecture is proposed which decreases the standby and active power by 50 and 25%, respectively. It also increases the I/O speed to > 1600 Mb/s for 4 rank/module and 2 module/channel case since the master isolates all chip I/O loadings from the channel. Statistical analysis shows that the proposed TSV check and repair scheme can increase the assembly yield up to 98%. By providing extra VDD/VSS edge pads, power noise is reduced to < 100 mV even if all 4 ranks are refreshed every clock cycle consecutively. 相似文献
17.
Esch G. Jr. Chen T. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2004,12(11):1253-1257
Matching input/output (I/O) driver output resistance to transmission line impedance is critical for high-speed I/O operation in source series termination environments. Tuning driver output resistance can be accomplished through the use of calibration circuitry. Under ideal conditions, calibration circuitry can properly calibrate an I/O driver. Operating in an environment with die process, voltage, and temperature variations, that same calibration circuitry may perform improperly. This brief presents an I/O driver design that is less sensitive to process, voltage, and temperature variations. The proposed driver design provides a near linear or flat, output resistance response verses output voltage. Advantages of the proposed I/O driver architecture lie in applications where the output DC operating point may have a large variation, thus, reducing the error in matching output resistance. 相似文献
18.
Zero-delay lossy source coding schemes are considered for both individual sequences and random sources. Performance is measured by the distortion redundancy, which is defined as the difference between the normalized cumulative mean squared distortion of the scheme and the normalized cumulative distortion of the best scalar quantizer of the same rate that is matched to the entire sequence to be encoded. By improving and generalizing a scheme of Linder and Lugosi, Weissman and Merhav showed the existence of a randomized scheme that, for any bounded individual sequence of length n, achieves a distortion redundancy O(n/sup -1/3/logn). However, both schemes have prohibitive complexity (both space and time), which makes practical implementation infeasible. In this paper, we present an algorithm that computes Weissman and Merhav's scheme efficiently. In particular, we introduce an algorithm with encoding complexity O(n/sup 4/3/) and distortion redundancy O(n/sup -1/3/logn). The complexity can be made linear in the sequence length n at the price of increasing the distortion redundancy to O(n/sup -1/4//spl radic/logn). We also consider the problem of minimax distortion redundancy in zero-delay lossy coding of random sources. By introducing a simplistic scheme and proving a lower bound, we show that for the class of bounded memoryless sources, the minimax expected distortion redundancy is upper and lower bounded by constant multiples of n/sup -1/2/. 相似文献
19.
Sanchez H. Sigel J. Nicoletta C. Nissen J.P. Alvarez J. 《Solid-State Circuits, IEEE Journal of》1999,34(11):1501-1511
This I/O driver supports 3.3/2.5/1.8-V interfaces in a 3.5-nm Tox, 1.8-V CMOS technology. A bias generator, its switch capacitors, and a level shifter with protection network guarantee reliability and improve noise rejection. Measured output timing degradation is 2.5 ps per I/O switching. Buried resistors limit variation in output impedance. Interface delay of 2 ns with worst case I/O switching allows 400-MHz operation 相似文献
20.
This paper describes the design and the implementation of input-output (I/O) interface circuits for serial data links in the gigabit-per-second range. The cells were implemented in a 3.3-V 0.35-μm CMOS technology in a couple of test chips. The transmitter is fully compatible (DC coupling) with 100K positive emitter-coupled logic (PECL) systems and it is based on the voltage-switching principle in order to allow different termination schemes besides the canonical ECL termination, i.e., 50-Ω toward (VDD-2) V. The addition of some circuit techniques such as dynamic biasing and strobed current switching boosts the dynamic performance of the basic voltage-switching scheme and relaxes the requirements for a high bias current and large-size output devices at the same time. Moreover, thanks to the developed reference circuit, using both feedforward and feedback controls, the output levels are within the 100K tolerance over the full range of process, supply voltage, and temperature (PVT) variations without resorting to external components or on-chip trimming. The receiver cell is based on a complementary-differential architecture providing high speed and low error on the duty cycle of the CMOS output signal. The integrated receiver-transmitter chain exhibits a maximum toggle frequency of 1 GHz, while a chip-to-chip transmission link using the developed I/O interface was tested up to 1.2 Gb/s 相似文献