功率MOSFET器件SEGR敏感区域的模拟研究

单粒子栅极穿通（SEGR）是功率MOSFET器件在空间应用时非常重要的失效模式。功率MOSFET的元胞区被普遍认为是对SEGR最敏感的区域。然而试验结果表明SEGR可能会发生在栅极的走线区域,而不是元胞区域。本文通过仿真软件对功率MOSFET内部的三种结构进行模拟评估,发现如果满足某些条件,元胞区域以外的区域可能成为SEGR的敏感区域。最后,对于不同区域本为给出了抑制SEGR的建议。     

全耗尽SOI MOSFETs阈值电压和电势分布的温度模型

提出了一个全耗尽SOI MOSFETs器件阈值电压和电势分布的温度模型. 基于近似的抛物线电势分布模型,利用适当的边界条件对二维的泊松方程进行求解. 同时利用阈值电压的定义得到了阈值电压的模型. 该温度模型详细地研究了电势分布和阈值电压跟温度之间的变化关系,同时还近似地探讨了短沟道效应. 为了进一步验证模型的正确性,利用SILVACO ATAS软件进行了相应的模拟. 结果表明,模型计算与软件模拟吻合较好.     

全耗尽SOI MOSFETs阈值电压和电势分布的温度模型

提出了一个全耗尽SOI MOSFETs器件阈值电压和电势分布的温度模型.基于近似的抛物线电势分布模型,利用适当的边界条件对二维的泊松方程进行求解.同时利用阈值电压的定义得到了阈值电压的模型.该温度模型详细地研究了电势分布和阈值电压跟温度之间的变化关系,同时还近似地探讨了短沟道效应.为了进一步验证模型的正确性,利用SILVACO ATAS软件进行了相应的模拟.结果表明,模型计算与软件模拟吻合较好.     

槽栅功率MOSFET单粒子微剂量效应电荷沉积模型

重离子会在槽栅功率MOSFET器件中引起电压电流特性漂移,即单粒子微剂量效应。为表征该效应,本文提出了一个电荷沉积模型。该模型可用来计算重离子轰击氧化层后引起的电荷沉积及电荷输运过程。应用本模型计算了单个Xe离子在二氧化硅/硅界面沉积的空穴正电荷。通过将该计算结果导入Sentaurus仿真软件中,模拟了单个Xe离子轰击槽栅MOSFET后引起的电压电流曲线漂移。模拟结果与相关实验结果一致。最后,应用本模型研究了不同参数对槽栅功率MOSFET单粒子微剂量效应的影响。     

Avalanche behavior of power MOSFETs under different temperature conditions

The ability of high-voltage power MOSFETs to withstand avalanche events under different temperature conditions are studied by experiment and two-dimensional device simulation.The experiment is performed to investigate dynamic avalanche failure behavior of the domestic power MOSFETs which can occur at the rated maximum operation temperature range(-55 to 150℃).An advanced ISE TCAD two-dimensional mixed mode simulator with thermodynamic non-isothermal model is used to analyze the avalanche failure mechanism.The unclamped inductive switching measurement and simulation results show that the parasitic components and thermal effect inside the device will lead to the deterioration of the avalanche reliability of power MOSFETs with increasing temperature.The main failure mechanism is related to the parasitic bipolar transistor activity during the occurrence of the avalanche behavior.     

功率MOS器件在不同温度条件下雪崩特性研究

本文使用实验和二维器件模拟仿真方法研究了高压功率MOS器件在不同温度条件下的耐雪崩能力。实验研究了国产功率MOS器件在最大额定工作温度范围(-55℃～150℃)发生的雪崩能量烧毁行为。采用包含电热非等温模型的ISE TCAD二维仿真软件模拟分析器件发生雪崩失效的机理。无嵌位电感实验数据及模拟结果证明,由于器件内部寄生效应及热效应影响,功率MOS器件雪崩耐量可靠性随着温度升高而退化,其主要原因与雪崩过程引起器件内部寄生双极管开启相关。     

功率MOS和IGBT器件在无嵌位电感开关条件下的动态雪崩特性研究

The ability of high-voltage power MOSFETs and IGBTs to withstand avalanche events under unclamped inductive switching(UIS) conditions is measured.This measurement is to investigate and compare the dynamic avalanche failure behavior of the power MOSFETs and the IGBT,which occur at different current conditions.The UIS measurement results at different current conditions show that the main failure reason of the power MOSFETs is related to the parasitic bipolar transistor,which leads to the deterioration of the avalanche reliability of power MOSFETs.However,the results of the IGBT show two different failure behaviors.At high current mode,the failure behavior is similar to the power MOSFETs situation.But at low current mode,the main failure mechanism is related to the parasitic thyristor activity during the occurrence of the avalanche process and which is in good agreement with the experiment result.     

Analog and radio-frequency performance analysis of silicon-nanotube MOSFETs

This work presents a comparative study of the influence of various parameters on the analog and RF properties of silicon-nanotube MOSFETs and nanowire-based gate-all-around (GAA) MOSFETs. The important analog and RF performance parameters of SiNT FETs and GAA MOSFETs, namely drain current (I_d), transconductance to drain current ratio (g_m/I_d), I_on/I_off, the cut-off frequency (f_T) and the maximum frequency of oscillation (f_MAX) are evaluated with the help of Y- and H-parameters which are obtained from a 3-D device simulator, ATLAS^TM. It is found that the silicon-nanotube MOSFETs have far more superior analog and RF characteristics (g_m/I_d, f_T and f_MAX) compared to the nanowire-based gate-all-around GAA MOSFETs. The silicon-nanotube MOSFET shows an improvement of~2.5 and 3 times in the case of f_T and f_MAX values respectively compared with the nanowire-based gate-all-around (GAA) MOSFET.     

Temperature dependent model for threshold voltage and subthreshold slope of strained-Si channel MOSFETs with a polysilicon gate

We present a temperature dependent model for the threshold voltage V_t and subthreshold slope S of strained-Si channel MOSFETs and validate it with reported experimental data for a wide range of temperature, channel doping concentration, oxide thickness and strain value. Such model includes the effect of lattice strain on material, temperature dependent effective mass of carriers, interface-trapped charge density and bandgap narrowing due to heavy channel doping. Also considered are polydepletion effects, carrier localization effect in the ultra-thin channel and quantum-mechanical effects. Our investigation reveals that the threshold voltage reduces linearly with increasing temperature whereas the subthreshold slope increases. In addition V_t is found to be sensitive to strain while S is weakly dependent on strain. Moreover, the channel doping concentration influences both V_t and S, and also the rate of change of V_t with temperature. Furthermore, S decreases for a lightly doped channel particularly at lower temperatures.     

Accurate Characterization of Silicon-On-Insulator MOSFETs for the Design of Low-Voltage, Low-Power RF Integrated Circuits

The maturation of low cost Silicon-on-Insulator (SOI) MOSFET technology in the microwave domain has brought about a need to develop specific characterization techniques. An original scheme is presented, which, by combining careful design of probing and calibration structures, rigorous in-situ calibration, and a new powerful direct extraction method, allows reliable identification of the parameters of the non-quasi-static small-signal model and the high-frequency noise parameters for MOSFETs. The extracted model is shown to be valid up to 40 GHz.     

功率VDMOS器件的SEB致SEGR效应研究

功率VDMOS器件是航天器电源系统配套的核心元器件之一,在重粒子辐射下会发生单粒子烧毁(SEB)和单粒子栅穿(SEGR)效应,严重影响航天器的在轨安全运行。本文在深入分析其单粒子损伤机制及微观过程的基础上,发现了功率VDMOS器件在重粒子辐射下存在SEBIGR效应,并在TCAD软件和¹⁸¹Ta粒子辐射试验中进行了验证。引起该效应的物理机制是,重粒子触发寄生三极管,产生瞬时大电流,使得硅晶格温度升高,高温引起栅介质层本征击穿电压降低,继而触发SEGR效应。SEBIGR效应的发现为深入分析功率MOSFET器件的单粒子辐射效应奠定了理论基础。     

Gate-edge charges related effects and performance degradation in advanced multiple-gate MOSFETs

This paper analyzes the influence of negative charges (NC) located at the gate edges on the advanced MOSFETs behavior, paying particular attention to the subthreshold slope, S, maximum transconductance, G_mmax, and analog figures of merit, such as transconductance over drain current ratio, G_m/I_D, output conductance, G_D, Early voltage, V_EA, and intrinsic gain. General trends obtained by two-dimensional numerical simulations on double-gate (DG) structures are whenever possible qualitatively correlated with experimental data obtained on FinFETs. We show that the presence of negative charges at the gate edges while degrading the subthreshold behavior and analog figures of merit (especially for long-channel devices) can result in apparent improved control of short-channel effects and higher G_mmax. The origin of such twofold impact of negative charges at the gate edges on the device behavior is also analyzed by 2-D device simulations and a simplified two-transistors model.     

Modeling and simulation of centroid and inversion charge density in cylindrical surrounding gate MOSFETs including quantum effects

An analytical model for surrounding gate metal–oxide–semiconductor field effect transistors(MOSFETs)considering quantum effects is presented.To achieve this goal,we have used a variational approach for solving the Poisson and Schrodinger equations.This model is developed to provide an analytical expression for the inversionchargedistributionfunctionforallregionsofthedeviceoperation.Thisexpressionisusedtocalculatethe other important parameters like the inversion charge centroid,threshold voltage and inversion charge density.The calculated expressions for the above parameters are simple and accurate.The validity of this model was checked for the devices with different device dimensions and bias voltages.The calculated results are compared with the simulation results and they show good agreement.     

长沟道圆柱围栅高K栅栈结构MOSFETs器件的直接隧穿电流解析模型

An analytical direct tunneling gate current model for cylindrical surrounding gate（CSG） MOSFETs with high-k gate stacks is developed. It is found that the direct tunneling gate current is a strong function of the gate＇s oxide thickness, but that it is less affected by the change in channel radius. It is also revealed that when the thickness of the equivalent oxide is constant, the thinner the first layer, the smaller the direct tunneling gate current.Moreover, it can be seen that the dielectric with a higher dielectric constant shows a lower tunneling current than expected. The accuracy of the analytical model is verified by the good agreement of its results with those obtained by the three-dimensional numerical device simulator ISE.     

纳米双栅MOSFET栅极漏电流的二维量子模拟(英文)

基于非平衡格林函数(NEGF)的量子输运理论框架,对双栅MOSFET进行了二维实空间数值模拟。在对表征载流子电势的泊松方程自洽求解后,感兴趣的物理量(如亚阈值摆幅、漏致势垒下降、载流子密度、电流密度等)可以被求得,观察了由栅极注入效应导致的二维电荷分布,并对不同电介质材料对栅极漏电流的影响进行了研究。此外,还通过调整电介质参数并进行比较的方法,研究了电介质的有效质量、介电常数、导带偏移对栅极漏电流的影响。该模拟方法为双栅MOSFET中载流子自栅极的注入提供了良好的物理图景,对器件特性的分析和比较有助于栅氧层高k电介质材料的选取。     

Cylindrical surrounding-gate MOSFETs with electrically induced source/drain extension

A novel cylindrical surrounding gate MOSFETs with electrically induced source/drain extension is proposed and demonstrated by numerical simulation for the first time. In the new device, a constant voltage is applied to the side-gate to form inversion layers acting as the extremely shallow virtual source/drain. Using three-dimensional device simulator, we have investigated the device performance focusing on the threshold voltage roll-off, the drain induced barrier lowering, the subthreshold swing, electrical field and carrier temperature. Based on our simulation results, we demonstrate that the proposed structure exhibits better suppression of short channel effects and hot carrier effects when compared to the conventional cylindrical surrounding gate MOSFETs.     

槽栅型SiC MOSFET器件单粒子响应特性研究

利用TCAD Sentaurus模拟仿真软件,研究分析了三种不同结构的槽栅型1 200 V SiC MOSFET单粒子响应特性,器件包括传统单沟槽MOSFET、双沟槽MOSFET和非对称沟槽MOSFET结构。仿真结果表明,双沟槽MOSFET的抗单粒子特性优于其它两种结构器件。通过分析可知,双沟槽MOSFET结构的优越性在于有较深的源极深槽结构,有助于快速收集单粒子碰撞过程产生的载流子,从而缓解大量载流子聚集带来的内部电热集中,相比其它两种结构能有效抑制引起单粒子烧毁的反馈机制。     

Normally-off 4H-SiC trench-gate MOSFETs with high mobility

A new 4H-SiC trench-gate MOSFET structure with epitaxial buried channel for accumulation-mode operation, has been designed and fabricated, aiming at improving channel electron mobility. Coupled with improved fabrication processes, the MOSFET structure eliminates the need of high dose N⁺ source implantation. High dose N⁺ implantation requires high-temperature (1550 °C) activation annealing and tends to cause substantial surface roughness, which degrades MOSFET threshold voltage stability and gate oxide reliability. The buried channel is implemented without epitaxial regrowth or accumulation channel implantation. Fabricated MOSFETs subject to ohmic contact rapid thermal annealing at 850 °C for 5 min exhibit a high peak field-effect mobility (μ_FE) of 95 cm²/V s at room temperature (25 °C) and 255 cm²/V s at 200 °C with stable normally-off operation from 25 °C to 200 °C. The dependence of channel mobility and threshold voltage on the buried channel depth is investigated and the optimum range of channel depth is reported.     

Light emission from interface traps and bulk defects in SiC MOSFETs

Images and spectra of light emission have been observed in 4H and 6HSiC n-type MOSFETs originating from electron-hole recombination at interface traps and from the bulk under the channel. Low mobility and high interface trap density impedes the flow of electrons into the channel. Its time evolution was imaged. It is slower in 4H than in 6H MOSFETs due to the lower channel mobility and higher interface trap density in the former. Emission images reveal triangular shaped 3C inclusions and these defects were found to alter the formation of the inversion layer.     

高K栅堆叠结构MOSFET器件阈值电压不稳定度的半经验解析模型

A semi-empirical analytic model for the threshold voltage instability of MOSFET is derived from the Shockley-Read-Hall (SRH) statistics in this paper to account for the transient charging effects in a MOSFET high-k gate stack. Starting from the single energy level and single trap assumption, an analytical expression of the filled trap density in terms of the dynamic time is derived from the SRH statistics. The semi-empirical analytic model of the threshold voltage instability is developed based on the MOSFET device physics between the threshold voltage and the induced trap density. The obtained model is also verified by the extensive experimental data of the trapping and de-trapping stress from the different high k gate configuration.