Room temperature quantum cascade detector operating at 4.3 μm

A strain-compensated InP-based InGaAs/InAlAs quantum cascade detector grown by solid source molecular beam epitaxy is demonstrated. The device operates at 4.3 μm up to room temperature (300 K) with a responsivity of 1.27 mA/W and a Johnson noise limited detectivity of 1.02×10⁷ cm·Hz^1/2/W. At 80 K, the responsivity and detectivity are 14.55 mA/W and 1.26×10¹⁰ cm·Hz^1/2/W, respectively. According to the response range, this detector is much suitable for greenhouse gas detection.     

S-band low noise amplifier using 1 μm InGaAs/InAlAs/InP pHEMT

This paper discusses the design of a wideband low noise amplifier (LNA) in which specific architecture decisions were made in consideration of system-on-chip implementation for radio-astronomy applications. The LNA design is based on a novel ultra-low noise InGaAs/InAlAs/InP pHEMT. Linear and non-linear modelling of this pHEMT has been used to design an LNA operating from 2 to 4 GHz. A common-drain in cascade with a common source inductive degeneration, broadband LNA topology is proposed for wideband applications. The proposed configuration achieved a maximum gain of 27 dB and a noise figure of 0.3 dB with a good input and output return loss (S₁₁ < -10 dB, S₂₂ < -11 dB). This LNA exhibits an input 1-dB compression point of -18 dBm, a third order input intercept point of 0 dBm and consumes 85 mW of power from a 1.8 V supply.     

An 8.12 μ W wavelet denoising chip for PPG detection and portable heart ratemonitoring in 0.18 μm CMOS

A low power wavelet denoising chip for photoplethysmography (PPG) detection and portable heart rate monitoring is presented. To eliminate noise and improve detection accuracy, Harr wavelet (HWT) is chosen as the processing tool. An optimized finite impulse response structure is proposed to lower the computational complexity of proposed algorithm, which is benefit for reducing the power consumption of proposed chip. The modulus maxima pair location module is design to accurately locate the PPG peaks. A clock control unit is designed to further reduce the power consumption of the proposed chip. Fabricated with the 0.18 μm N-well CMOS 1P6M technology, the power consumption of proposed chip is only 8.12 μ W in 1 V voltage supply. Validated with PPG signals in multiparameter intelligent monitoring in intensive care databases and signals acquired by the wrist photoelectric volume detection front end, the proposed chip can accurately detect PPG signals. The average sensitivity and positive prediction are 99.91% and 100%, respectively.     

A 0.18 μm CMOS Gilbert low noise mixer with noise cancellation

This paper presents a broadband Gilbert low noise mixer implemented with noise cancellation technique operating between 10 MHz and 0.9 GHz. The Gilbert mixer is known for its perfect port isolation and bad noise performance. The noise cancellation technique of LNA can be applied here to have a better NF. The chip is implemented in SMIC 0.18 μm CMOS technology. Measurement shows that the proposed low noise mixer has a 13.7-19.5 dB voltage gain from 10 MHz to 0.9 GHz, an average noise figure of 5 dB and a minimum value of 4.3 dB. The core area is 0.6 × 0.45 mm².     

A novel HBT trigger SCR in 0.35 μm SiGe BiCMOS technology

The silicon-controlled rectifier (SCR) device is known as an efficient electrostatic discharge (ESD) protection device due to the highest ESD robustness in the smallest layout area. However, SCR has some drawbacks, such as high trigger voltage and low holding voltage. In order to reduce the trigger voltage of the SCR device for ESD protection, a new heterojunction bipolar transistor (HBT) trigger silicon controlled rectifier (HTSCR) device in 0.35 μm SiGe BiCMOS technology are proposed. The underlying physical mechanisms critical to the trigger voltage are demonstrated based on transmission line pulsing (TLP) measurement and physics-based simulation results. The simulation results prove that the trigger voltage of the HTSCR is decided by the collector-to-emitter breakdown voltage of the HBT structure in floating base configuration. The ESD experiment test results demonstrate the HTSCR can offer superior performance with a small trigger voltage, an adjustable holding voltage and a high ESD robustness. In comparison to the conventional MLSCR, the trigger voltage of the fabricated HTSCR can reduce to less than 50% of that of the MLSCR, and the I_t2 of the HBT trigger SCR is 80% more than that of the MLSCR.     

A reconfigurable passive mixer for multimode multistandard receivers in 0.18 μm CMOS

This paper presents a reconfigurable quadrature passive mixer for multimode multistandard receivers. By using controllable transconductor and transimpedance-amplifier stages, the voltage conversion gain of the mixer is reconfigured according to the requirement of the selected communication standard Other characteristics such as noises figure, linearity and power consumption are also reconfigured consequently. The design concept is verified by implementing a quadrature passive mixer in 0.18 μm CMOS technology. On wafer measurement results show that, with the input radio frequency ranges from 700 MHz to 2.3 GHz, the mixer achieves a controllable voltage conversion gain from 4 to 22 dB with a step size of 6 dB. The measured maximum ⅡP3 is 8.5 dBm and the minimum noise figure is 8.0 dB. The consumed current for a single branch (I or Q) ranges from 3.1 to 5.6 mA from a 1.8 V supply voltage. The chip occupies an area of 0.71 mm² including pads.     

Design of GGNMOS ESD protection device for radiation-hardened 0.18 μm CMOS process

In this paper, the ESD discharge capability of GGNMOS (gate grounded NMOS) device in the radiation-hardened 0.18 μm bulk silicon CMOS process (Rad-Hard by Process: RHBP) is optimized by layout and ion implantation design. The effects of gate length, DCGS and ESD ion implantation of GGNMOS on discharge current density and lattice temperature are studied by TCAD and device simulation. The size of DCGS, multi finger number and single finger width of ESD verification structures are designed, and the discharge capacity and efficiency of GGNMOS devices in ESD are characterized by TLP test technology. Finally, the optimized GGNMOS is verified on the DSP circuit, and its ESD performance is over 3500 V in HBM mode.     

Dilute nitrides and 1.3 μm GaInNAs quantum well lasers on GaAs

We present epitaxial growth of GaInNAs on GaAs by molecular beam epitaxy (MBE) using analog, digital and N irradiation methods. It is possible to realize GaInNAs quantum wells (QWs) with a maximum substitutional N concentration up to 6% and a strong light emission up to 1.71 μm at 300 K. High quality 1.3 μm GaInNAs multiple QW edge emitting laser diodes have been demonstrated. The threshold current density (for a cavity of 100×1000 μm²) is 300, 300, 400 and 940 A/cm² for single, double, triple and quadruple QW lasers, respectively. The maximum 3 dB bandwidth reaches 17 GHz and high-speed transmission at 10 Gb/s up to 110 °C under a constant voltage has been demonstrated.     

Low fabrication cost wavelength tunable WG-FP hybrid-cavity laser working over 1.7 μm

A wide wavelength tuning range and single-mode hybrid cavity laser consists of a square Whispering-Gallery (WG) microcavity and a Fabry–Pérot (FP) was introduced and demonstrated. A wavelength tuning range over 12.5 nm from 1760.87 to 1773.39 nm which was single-mode emitting was obtained with the side-mode suppression ratio over 30 dB. The hybrid cavity laser does not need grating etching and special epitaxial structure, which reduces the fabrication difficulty and cost, and shows the potential for gas sensing with absorption lines in this range.     

Extremely low threshold current density strained InGaAs／AlGaAs quantum well lasers by molecular beam epitaxy

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1.3 μm GaAs-based quantum well and quantum dot lasers: Comparative analysis

New generation of long-wavelength (1.3 μm) GaAs based lasers is discussed. The modal gain, threshold current, quantum efficiency characteristics and temperature stability of lasers based on InGaAsn quantum wells and InAs/InGaAs quantum dots are compared.     

Tapered quantum cascade lasers operating at 9.0μm

正The tapered quantum cascade lasers operating at about 9.0μm are reported.In contrast to the common ridge waveguide laser,tapered devices give rather small horizontal beam divergence.Performances of devices with identical 11μm ridge waveguide sections and different tapered gain sections are comparatively studied.The optimal taper angle of 3°leads to a relative high output power and a very small horizontal beam divergence of 7.1°.     

Tapered quantum cascade lasers operating at 9.0μm

The tapered quantum cascade lasers operating at about 9.0μm are reported. In contrast to the common ridge waveguide laser, tapered devices give rather small horizontal beam divergence. Performances of devices with identical 11μm ridge waveguide sections and different tapered gain sections are comparatively studied. The optimal taper angle of 3° leads to a relative high output power and a very small horizontal beam divergence of 7.1°.     

An integrated front-end vertical hall magnetic sensor fabricated in 0.18 μm low-voltage CMOS technology

An integrated front-end vertical CMOS Hall magnetic sensor is proposed for the in-plane magnetic field measurement. To improve the magnetic sensitivity and to obtain low offset, a fully symmetric vertical Hall device (FSVHD) has been optimized with a minimum size design. A new four-phase spinning current modulation associated with a correlated double sampling (CDS) demodulation technique has been further applied to compensate for the offset and also to provide a linear Hall output voltage. The vertical Hall sensor chip has been manufactured in a 0.18 μm low-voltage CMOS technology and it occupies an area of 1.54 mm². The experimental results show in the magnetic field range from –200 to 200 mT, the entire vertical Hall sensor performs with the linearity of 99.9% and the system magnetic sensitivity of 1.22 V/T and the residual offset of 60 μT. Meanwhile, it consumes 4.5 mW at a 3.3 V supply voltage. The proposed vertical Hall sensor is very suitable for the low-cost system-on-chip (SOC) implementation of 2D or 3D magnetic microsystems.     

High power lasers based on submonolayer InAs–GaAs quantum dots and InGaAs quantum wells

Broad area lasers based on InAs-GaAs quantum dots formed by submonolayer deposition were fabricated. High modal gain of submonolayer quantum dots permits the use of broad-waveguide and highly doped design. Continuous wave output power of 6 W limited by mirror damage and conversion efficiency of 58% were demonstrated at 20 °C. The characteristic temperature of 150 K was achieved.     

1.46μm room-temperature emission from InAs/InGaAs quantum dot nanostructures

We present a study on InAs/InGaAs QDs nanostmctures grown by molecular beam epitaxy on InGaAs metamorphic buffers,that are designed so as to determine the strain of QD and, then, to shift the luminescence emission towards the 1.5 μm region (QD strain engineering). Moreover, we embed the QDs in InAlAs or GaAs barriers in addition to the InGaAs confining layers, in order to increase the activation energy for confined carrier thermal escape; thus, we reduce the thermal quenching of the photoluminescence, which prevents room temperature emission in the long wavelength range. We study the dependence of QD properties, such as emission energy and activation energy, on barrier thickness and height and we discuss how it is possible to compensate for the barrier-induced QD emission blue-shift taking advantage of QD strain engineering. Furthermore, the combination of enhanced barriers and QD strain engineering in such metamorphic QD nanostructures allowed us to obtain room temperature emission up to 1.46 μm, thus proving how this is a valuable approach in the quest for 1.55 μm room temperature emission from QDs grown on GaAs substrates.     

A fractional-N frequency divider for multi-standard wireless transceiver fabricated in 0.18 μm CMOS process

With the rapid evolution of wireless communication technology,integrating various communication modes in a mobile terminal has become the popular trend.Because of this,multi-standard wireless technology is one of the hot spots in current research.This paper presents a wideband fractional-N frequency divider of the multi-standard wireless transceiver for many applications.High-speed divider-by-2 with traditional sourcecoupled-logic is designed for very wide band usage.Phase switching technique and a chain of divider-by-2/3 are applied to the programmable frequency divider with 0.5 step.The phase noise of the whole frequency synthesizer will be decreased by the narrower step of programmable frequency divider.△-Σ modulator is achieved by an improved MASH 1-1-1 structure.This structure has excellent performance in many ways,such as noise,spur and input dynamic range.Fabricated in TSMC 0.18 μm CMOS process,the fractional-N frequency divider occupies a chip area of 1130 × 510μm2 and it can correctly divide within the frequency range of 0.8-9 GHz.With 1.8 V supply voltage,its division ratio ranges from 62.5 to 254 and the total current consumption is 29 mA.     

A 10 bit 200 MS/s pipeline ADC using loading-balanced architecture in 0.18 μm CMOS

A new loading-balanced architecture for high speed and low power consumption pipeline analog-to-digital converter (ADC) is presented in this paper. The proposed ADC uses SHA-less, op-amp and capacitor-sharing technique, capacitor-scaling scheme to reduce the die area and power consumption. A new capacitor-sharing scheme was proposed to cancel the extra reset phase of the feedback capacitors. The non-standard inter-stage gain increases the feedback factor of the first stage and makes it equal to the second stage, by which, the load capacitor of op-amp shared by the first and second stages is balanced. As for the fourth stage, the capacitor and op-amp no longer scale down. From the system''s point of view, all load capacitors of the shared OTAs are balanced by employing a loading-balanced architecture. The die area and power consumption are optimized maximally. The ADC is implemented in a 0.18 μm 1P6M CMOS technology, and occupies a die area of 1.2×1.2 mm². The measurement results show a 55.58 dB signal-to-noise-and-distortion ratio (SNDR) and 62.97 dB spurious-free dynamic range (SFDR) with a 25 MHz input operating at a 200 MS/s sampling rate. The proposed ADC consumes 115 mW at 200 MS/s from a 1.8 V supply.     

GaAs-based 1.3 µm InGaAs quantum dot lasers: A status report

We review the present status of InGaAs quantum dot lasers on GaAs sub-strates emitting near and at 1.3 μm. Such lasers are shown to be extremely promising for cost-efficient commercial applications in optical fiber communication. Threshold current densities a low as ∼20 Acm⁻² per QD sheet are achieved. Room temperature continuous wave operation at 2.7 W for broad stripe devices is demonstrated. The maximum differential efficiency amounts to 57%. Moreover, single lateral mode continuous wave operation with a maximum output power of 110 mW is realized. Prospects for 1.3 μm GaAs-based vertical cavity surface emitting lasers are given. We also show that the longest wavelength of QD GaAs-based light emitting devices can be potentially extended to 1.7 μm.     

A 10 bit 50 MS/s SAR ADC with partial split capacitor switching scheme in 0.18 μm CMOS

This paper presents a 10 bit successive approximation register (SAR) analog-to-digital converter (ADC) in 0.18 μ m 1P6M CMOS technology with a 1.8 V supply voltage. To improve the conversion speed, a partial split capacitor switching scheme is proposed. By reducing the time constant of the bit cycles, the proposed technique shortens the settling time of a capacitive digital-to-analog converter (DAC). In addition, a new SAR control logic is proposed to reduce loop delay to further enhance the conversion speed. At 1.8 V supply voltage and 50 MS/s the SAR ADC achieves a signal-to-noise and distortion ratio (SNDR) of 57.5 dB and spurious-free dynamic range (SFDR) of 69.3 dB. The power consumption is 2.26 mW and the core die area is 0.096 mm².