分离栅式快闪存储器擦除性能的工艺优化

随着电子产品的普及,分离栅式快闪存储器作为闪存的一种,由于具有高效的编程速度以及能够完全避免过擦除的能力,无论是在单体还是在嵌入式产品方面都得到了人们更多的关注。随着闪存市场高集成度的发展需求,分离栅式快闪存储器的尺寸也在逐渐地缩小。从结构和工艺优化方面探讨在这一微缩过程中,如何有效提高分离栅式快闪存储器的擦除效率。通过实验发现通过形成非对称性浮栅结构,优化浮栅到擦除栅侧的结构形貌,可以显著改进分离栅式工艺快闪存储器的擦除性能。     

Gate stress effect on low temperature data retention characteristics of split-gate flash memories

In modeling post-cycling low temperature data retention (LTDR) characteristics of split-gate flash memories, gate stress is used to accelerate the charge gain effect responsible for bit cell current reduction among tail bits. To determine the adequate stress condition, various gate stress voltages are performed to enhance the charge gain effect of the flash memory cells. In addition, by analyzing the leakage mechanism and the data retention behavior of cells under gate stress conditions, reliability tests can be completed in a much shorter period and still provide accurate lifetime prediction for embedded memory products.     

Erase voltage impact on 0.18μm triple self-aligned split-gate flash memory endurance

The erase voltage impact on the 0.18μm triple self-aligned split-gate flash endurance is studied.An optimized erase voltage is necessary in order to achieve the best endurance.A lower erase voltage can cause more cell current degradation by increasing its sensitivity to the floating gate voltage drop,which is induced by tunnel oxide charge trapping during program/erase cycling.A higher erase voltage also aggravates the endurance degradation by introducing select gate oxide charge trapping.A progressive erase voltage method is proposed and demonstrated to better balance the two degradation mechanisms and thus further improve endurance performance.     

Improving radiation hardness of EEPROM/flash cell by N2Oannealing

The effects of an N₂O anneal on the radiation effects of a split-gate electrical erasable programmable read only memory (EEPROM)/flash cell with a recently-proposed horn-shaped floating gate were studied. We have found that although the cells appear to survive 1 Mrad(Si) Co⁶⁰ irradiation without data retention failure, the write/erase cycling endurance was severely impeded after irradiation. Specifically, the write/erase cycling endurance was degraded to 20 K from the pre-irradiation value of 50 K. However, by adding an N₂ O annealing step after the interpoly oxidation, the after-irradiation write/erase cycling endurance of the resultant cell can be significantly improved to over 45 K. N₂O annealing also improves the after-irradiation program and erase efficiencies. The N₂O annealing step therefore presents a potential method for enhancing the robustness of the horn-shaped floating-gate EEPROM/flash cells for radiation-hard applications     

Gate current injection in MOSFET's with a split-gate (virtualdrain) structure

Gate current injection into the gate oxide of MOSFETs with a split-gate (virtual drain) structure is examined. The split-gate structure is commonly encountered in flash EEPROM and CCDs. An important parameter characterizing the gate current injection is the ratio φ _b/φ_i (where φ_b is the effective energy barrier for electron injection into gate oxide, and φ_i , is the impact ionization energy). Measurements of φ_b /φ_i at relatively constant vertical and lateral electric fields are reported. Through the use of a novel triple-gate MOSFET, the drain current as well as the lateral and vertical electric field at the point of injection were independently controlled during the measurements. The measured φ_b/φ_i showed a dependence on gate and drain biases not reported previously     

Statistical simulations for flash memory reliability analysis and prediction

In this paper, through the use of a recently proposed statistical model of stress-induced leakage current, we will investigate the reliability of actual flash memory technologies and predict future trends. We investigate either program disturbs (namely gate and drain disturbs) and data retention of state-of-the-art flash memory cells and use this model to correlate the induced threshold voltage shift to the typical outputs coming from oxide characterization, that are density, cross section, and energy level of defects. Physical mechanisms inducing the largest threshold voltage (V/sub T/) degradation will be identified and explained. Furthermore, we predict the effects of tunnel oxide scaling on flash memory data retention, giving a rule of thumb to scale the tunnel oxide while maintaining the same retention requirements.     

Memory characterization of SiGe quantum dot flash memories with HfO/sub 2/ and SiO/sub 2/ tunneling dielectrics

In this study, we have developed a SiGe dot floating-gate flash memory with high-K dielectric (HfO/sub 2/) tunneling oxide. Using SiGe dots and HfO/sub 2/ tunneling oxide, a low program/erase voltage can be achieved, along with good endurance and charge retention characteristics as compared to the SiGe dots with a SiO/sub 2/ tunneling oxide. We have also examined the impact of Ge concentration in the SiGe dots on charge retention time. This demonstrates that the SiGe dots with HfO/sub 2/ tunneling oxide can be used as the floating gate to replace SiGe dots with SiO/sub 2/ tunneling oxide and have a high potential for further scaling of floating gate memory devices.     

用分离栅极闪存单元实现可编程逻辑阵列

我们开发了一种新型可配置逻辑阵列测试结构,它采用高度可伸缩且兼具功耗低和配置时间短两大优势的第3代分离栅极闪存单元。此分离栅极Super Flash配置元件(SCE)已通过90nm嵌入式闪存技术进行了演示。得到的SCE消除了对深奥的制造工艺、检测和SRAM电路的需求,并缩短了可编程阵列(PA)(例如,FPGA和CPLD)的配置时间。此外,SCE本身还具有SST分离栅极闪存技术的优点,包括紧凑的区域、低电压读操作、低功耗多晶硅间(pol y-t o-pol y)擦除、源极侧通道热电子(SSCHE)注入编程机制以及超高的可靠性。     

Investigation of read disturb in split-gate memory and its feasible solution

The intrinsic read disturb mechanism in split-gate memory cells has been studied based on large amounts of experimental data and simulation results of 0.11 μm NOR SuperFlash® technology memory cells. It is shown that non-planar Floating Gate (FG) structure induced field enhance effect helps to cause Fowler-Nordheim Tunneling (F-N tunneling) in tunnel oxide during read operation, which will further lead to the leakage of electrons from FG to Word Line (WL). Then, the sensitivity of read disturb to process variation is investigated to expound the difference between typical cells and weak cells. The experiment has also demonstrated the weakening of read disturb due to induced tunnel oxide traps after program/erase (P/E) cycles. Based on these findings, we have rationally proposed possible solutions to reduce the read disturb on the perspectives of chip testing. The study of intrinsic read disturb mechanism is significant to the scaling of split-gate memory technology as well as to the assessment of read disturb risk in split-gate memory products.     

The impacts of control gate voltage on the cycling endurance ofsplit gate flash memory

In this paper, the “erase” degradation in program/erase (P/E) cycling endurance of split-gate flash memory has been investigated. It is found that increasing the control-gate (CG) voltage (V_CG) during erasing can slow down the “window closure” of cycling endurance since a higher V_CG can “push” the FG potential into gradual part of I_Read-out -V_FG curve and in turn reduce the read-out current degradation. Moreover, the experimental results show that scaling down the gate oxide thickness under FG can effectively reduce the I_Read-out degradation in the cycling endurance test     

Investigation of the soft-write mechanism in source-side injectionflash EEPROM devices

The soft-write effect which occurs when reading the content of a source-side injection (SSI) flash EEPROM cell has been identified and thoroughly investigated. This effect is caused by an electron injection mechanism which has the same physical origin as the enhanced (or source-side) hot-electron injection that is used for fast flash EEPROM programming. A procedure for the prediction of the associated soft-write lifetime is proposed, subsequently applied to a state-of-the-art split-gate SSI cell, and found to be noncritical for a reliable device operation. Therefore, source and drain do not have to be interchanged during the read-out operation with respect to the programming operation, and the traditional forward read-out scheme can be maintained for SSI flash memories     

A simple and efficient self-limiting erase scheme for highperformance split-gate flash memory cells

This paper presents a fast self-limiting erase scheme for split-gate flash EEPROMs. In this technique the conventional erasing is rapidly followed by an efficient soft programming to correct for over-erase within the given voltage pulsewidth. The typical erasing time is about 400 ms and the final erased threshold voltage is accurately controlled via the base level read mode voltage within 0.3 V. The proposed scheme can he used for high throughput erasing in low voltage, high density, multilevel operation split-gate flash memory cells     

A highly robust process integration with scaled ONO interpolydielectrics for embedded nonvolatile memory applications

We have developed a process sequence for a flash EEPROM memory embedded in an advanced microcontroller circuit. This process simultaneously forms a thick top oxide on the interpoly ONO dielectric in the memory array and a stacked gate-oxide for the logic transistors. We have fabricated one-transistor, flash bit-cells with good data retention characteristics that incorporate a 17 nm ONO film along with high-quality stacked gate oxides     

High-quality high-k HfON formed with plasma jet assisted PVD process and application as tunnel dielectric for flash memories

We demonstrate low-trap-density HfON film made by the molecular-atomic deposition (MAD) technique, which is an Ar/N₂ plasma jet assisted physical vapor deposition process. This high-k HfON can be deposited on top of the nearly trap-free MAD-Si₃N₄ to form a single-side crested tunnel barrier. The Al/(HfON-Si₃N₄)/Si capacitor structure with HfON/Si₃N₄ stack as the tunnel barrier demonstrates steeper I-V slope than that of a single layer SiO₂ with the same EOT, and is readily applicable to improve the programming speed and data retention of flash memories.     

3D NAND闪存数据保持力与初始状态依赖性研究

数据保持力是NAND闪存重要的可靠性指标,本文基于用户在使用模式下,通过设计测试方法,研究了电荷捕获型3D NAND闪存初始阈值电压-2V至3V的范围内数据保持力特性.结果表明初始状态为编程态时,可以有效降低NAND闪存高温数据保留后的误码率,特别是随着擦写次数的增加,不同初始状态下电荷捕获型3D NAND闪存数据保持力差异更加明显,结论表明闪存最适宜存放的状态为0-1V,电荷捕获型3D NAND闪存器件应避免长期处于深擦除状态.并基于不同初始状态闪存高温数据保留后的数据保持力特性不同的现象进行了建模和演示,通过设计实验验证,机理解释模型符合实验结果.该研究可为电荷捕获型3D NAND闪存器件的长期存放状态提供理论参考.     

一种新颖的对称式,双比特位,分栅闪存结构单元

A fully self-aligned symmetrical split-gate cell structure for 2-bit per cell flash memory with a very competitive bit size is presented. One common select gate is located between two floating gates and a pair of source/drain junctions are shared by the 2 bits. The fabrication method utilized here to create a self-aligned structure is to form a spacer against the prior layer without any additional mask. Although the cell consists of three channels in a series, the attributes from conventional split gate flash are still preserved with appropriate bias conditions. Program and erase operation is performed by using a source side injection （SSI） and a poly-to-poly tunneling mechanism respectively.     

A novel split-gate MOSFET design realized by a fully silicided gate process for the improvement of transconductance and output resistance

Work function tuning of nickel silicide (NiSi) gates was utilized to fabricate a novel split-gate MOSFET with improved device performance. The MOSFET with a NiSi split gate has been achieved by implanting antimony into the polysilicon gate from the drain side with a tilt angle, followed by a full nickel-silicidation process. The laterally nonuniform antimony implantation causes the NiSi gate work function to vary from the source side to the drain side due to the dopant segregation effect. Improved current drive and output resistance are observed in the MOSFET with such a NiSi split gate. Metal gate advantages and NiSi process simplicity were also realized in the split-gate process, and gate oxide quality did not degrade due to the low temperature process. This split-gate design is expected to be applicable in the nanoscale regime by optimizing process conditions.     

Analytical percolation model for predicting anomalous charge loss in flash memories

Data retention in flash memories is limited by anomalous charge loss. In this work, this phenomenon is modeled with a percolation concept. An analytical model is constructed that relates the charge-loss distribution of moving bits in flash memories with the geometric distribution of oxide traps. The oxide is characterized by a single parameter, the trap density. Combined with a trap-to-trap direct tunneling model, the physical parameters of the electron traps involved in the leakage mechanism are determined. Flash memory failure rate predictions for different oxide qualities, thicknesses and tunnel-oxide voltages are calculated.     

A new scalable self-aligned dual-bit split-gate charge-trapping memory device

Devices based on charge trapping are a promising solution for Flash memory scaling. The nonconductivity of their storage medium makes them more robust with respect to data loss by charge leakage through the bottom oxide, which, on the contrary sets a hard limit to floating-gate Flash scalability. Their simple processing, highly compatible with CMOS, makes them rapidly integrable into short-term solutions. The well-known SONOS concept however, still suffers from insufficient data throughput and retention. On the other hand, the recently proposed NROM concept, storing two bits in a cell, offers very interesting characteristics by using hot carrier based program/erase operations. However, important drawbacks remain, like insufficient isolation of the bits for scalability, high-power programming, and degradation of the retention after cycling. In this paper, we present a dual-bit trapping device which solves most of these problems by using a split-gate structure which was inspired by the HIMOS concept. The device has a fully self-aligned structure which allows for both bits to be physically isolated in the cell. Those features make it very scalable. Programming can be performed by the very efficient source-side injection mechanism, while erase is done by injection of band-to-band tunneling induced hot holes, which compensate for the trapped electrons. This leads to performances comparable to NROM but with lower power consumption, and lower operating voltages.