共查询到20条相似文献,搜索用时 31 毫秒
1.
Compact physical models are presented for on-chip double-sided shielded transmission lines, which are mainly used for long global interconnects where inductance effects should not be ignored. The models are then used to optimize the width and spacing of long global interconnects with repeater insertion. The impacts of increasing line width and spacing on various performance parameters such as delay, data-flux density, power dissipation and total repeater area are analysed. The product of data-flux density and reciprocal delay per unit length are defined as a figure of merit (FOM). By maximizing the FOM, the optimal width and spacing of shielded RLC global interconnects are obtained for various international technology roadmap for semiconductors (ITRS) technology nodes. 相似文献
2.
Xiao-Chun Li Jun-Fa Mao Hui-Fen Huang Ye Liu 《Electron Devices, IEEE Transactions on》2005,52(10):2272-2279
This paper addresses a novel methodology optimizing global interconnect width and spacing for International Technology Roadmap for Semiconductors technology nodes. Global interconnects with and without buffer insertion are considered. The effects of the width and spacing of global interconnects on performance, such as delay, bandwidth, total repeater area and energy dissipation, are analyzed. The product of delay and bandwidth is used as the figure of merit for simultaneous short latency and large bandwidth and the proposed methodology can optimize global interconnects for the maximal figure of merit. It is demonstrated that buffers should not be inserted in global interconnects if interconnect length is shorter than a critical length, which is a constant for a given technology. For global interconnects with buffer insertion, the optimal width and spacing have analytical expressions and are constants for a given technology. For global interconnects without buffer insertion, the optimal width and spacing are dependent on both the technology parameters and interconnect length and can be computed numerically. 相似文献
3.
A power-optimal repeater insertion methodology for global interconnects in nanometer designs 总被引:9,自引:0,他引:9
This paper addresses the problem of power dissipation during the buffer insertion phase of interconnect performance optimization. It is shown that the interconnect delay is actually very shallow with respect to both the repeater size and separation close to the minimum point. A methodology is developed to calculate the repeater size and interconnect length which minimizes the total interconnect power dissipation for any given delay penalty. This methodology is used to calculate the power-optimal buffering schemes for various ITRS technology nodes for 5% delay penalty. Furthermore, this methodology is also used to quantify the relative importance of the various components of the power dissipation for power-optimal solutions for various technology nodes. 相似文献
4.
《Microelectronics Journal》2007,38(4-5):649-655
The effect of voltage-scaling on interconnect delay minimization by CMOS-repeater insertion is analyzed. Analytical models are developed to calculate the optimum number of repeaters as function of CMOS supply voltage. The analytically obtained results are in good agreement with SPICE extracted results. Analysis shows that voltage-scaling decreases power dissipation and the optimum number of repeaters required for delay minimization in long interconnects. Both resistive and inductive interconnects have been considered. At highly scaled voltages, the inductive interconnect has the advantage of lower power-delay product. It is also seen that voltage-scaling affects delay improvement due to repeater insertion. 相似文献
5.
Singh P. Seo J.-s. Blaauw D. Sylvester D. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2008,16(6):673-677
In this paper, we propose a new circuit technique called self-timed regenerator (STR) to improve both speed and power for on-chip global interconnects. The proposed circuits are placed along global wires to compensate the loss in resistive wires and to amplify the effect of wire inductance in the wires to enable transmission line like behavior. For different wire widths, the number of STR and sizing of the transistors are optimized to accelerate the signal propagation while consuming minimum power. In 90-nm CMOS technology, STR design achieved a delay improvement of 14% over the conventional repeater design. Furthermore, 20% power reduction is achieved for iso-delay, and 8% delay improvement for iso-power compared with the repeater design. The proposed technique has also been applied to a clock distribution network, reducing clock power by 26%. 相似文献
6.
Bashirullah R. Wentai Liu Cavin R.K. III 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2003,11(3):406-417
This paper addresses propagation delay and power dissipation for current mode signaling in deep submicrometer global interconnects. Based on the effective lumped element resistance and capacitance approximation of distributed RC lines, simple yet accurate closed-form expressions of delay and power dissipation are presented. A new closed-form solution of delay under step input excitation is first developed, exhibiting an accuracy that is within 5% of SPICE simulations for a wide range of parameters. The usefulness of this solution is that resistive load termination for current mode signaling is accurately modeled. This model is then extended to a generalized delay formulation for ramp inputs with arbitrary rise time. Using these expressions, the optimum-line width that minimizes the total delay for current mode circuits is found. Additionally, a new power-dissipation model for current-mode signaling is developed to understand the design tradeoffs between current and voltage sensing. Based on the results and derived formulations, a comparison between voltage and current mode repeater insertion for long global deep submicrometer interconnects is presented. 相似文献
7.
Deodhar V.V. Davis J.A. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2005,13(3):308-318
The technique of optimal voltage scaling and repeater insertion is analyzed in this paper to reduce power dissipation on global interconnects. An analytical model for the maximum bit-rate of a very large scale integration interconnect with repeaters has been derived and results are compared with HSPICE simulations. The analytical model is also used to study the effects of interconnect length and scaling on throughput. The throughput-per-bit-energy is analyzed to determine an optimum combination of supply voltage and repeaters for a low-power global interconnect with 250 nm /spl times/ 250 nm cross-sectional dimensions implemented with the 180 nm micro-optical silicon system technology node. It is shown that the optimal supply voltage is approximately equal to twice the threshold voltage. A case study illustrates that a combination of 1 V supply along with one repeater per millimeter increases the throughput-per-bit-energy to over three times that of a latency-centric interconnect of 2 V, which results in a 70% reduction in power dissipation without any loss of throughput performance. 相似文献
8.
Joshi A.J. Lopez G.G. Davis J.A. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2007,15(9):990-1002
Every new VLSI technology generation has resulted in interconnects increasingly limiting the performance, area, and power dissipation of new processors. Subsequently, it is necessary to devise efficient interconnect design techniques to reduce the impact of VLSI interconnects on overall system design. New optimizations of a wave-pipelined multiplexed (WPM) interconnect routing circuit are described in this paper. These WPM circuits can be used with current interconnect repeater circuits to further reduce interconnect delay, interconnect area, transistor area, and/or power dissipation. For example, new area constrained WPM circuit optimizations illustrate that the interconnect circuit power can be reduced by 26% or the interconnect performance can be improved by 74%. Moreover, in both these cases, because a significant number of repeaters are eliminated, the transistor area can reduce by 41% or 29%, respectively. Finally, the tolerance of WPM circuits to crosstalk noise, power supply noise, clock skew, and manufacturing variations is also presented. This study of tolerance levels defines the conditions under which the WPM circuit will function correctly, and it is shown in this paper for the first time that WPM circuits are robust enough to operate with variability that can be encountered in deep submicrometer technologies. 相似文献
9.
Maheshwari A. Burleson W. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2007,15(11):1239-1244
In this paper, hybrids based on current-sensing and repeaters are proposed for on-chip interconnects in an effort to overcome the limitations of these techniques. A novel receiver for current-sensing results in static power savings and allows an easier transition from current-sensing to traditional full rail voltage signals. Measurements of hybrids on a 0.18-m CMOS technology show significant gains over repeater insertion in delay across wire lengths. Hybrids can also be used in placement constrained and low-noise scenarios to achieve delay and power benefits. 相似文献
10.
Optimal global interconnects for GSI 总被引:2,自引:0,他引:2
Performance of a high-speed chip is largely affected by both latency and bandwidth of global interconnects, which connect different macrocells. Therefore, one of the important goals is to design high-bandwidth and fast buses that connect a processor and its on-chip cache memory or link different processors within a multiprocessor chip. In this paper, the width of global interconnects is optimized to achieve a large "data-flux density" and a small latency simultaneously. Data-flux density is the product of interconnect bandwidth and reciprocal wire pitch, which represents the number of bits per second that can be transferred across a unit-length bisectional line. The optimal wire width, which maximizes the product of data-flux density and reciprocal latency, is independent of interconnect length and can be used for all global interconnects. It is rigorously proved that the optimal wire width is the width that results in a delay that is 33% larger than the time-of-flight (ToF). Using the optimal wire width decreases latency, energy dissipation, and repeater area considerably, compared to a sub-optimal wire width (e.g., 42% smaller latency, 30% smaller energy-per-bit, and 84% smaller repeater area compared with the W/sub opt//2 case) at the cost of a small decrease in data-flux density (e.g., 14% smaller compared with W/sub opt//2 case). A super-optimal wire width, however, causes a slight decrease in latency (e.g., 14% for 2W/sub opt/) at the cost of a large decrease in data-flux density (e.g., 35% for 2W/sub opt/). 相似文献
11.
Strollo A.G.M. De Caro D. Napoli E. Petra N. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2005,13(11):1266-1274
A new sense-amplifier-based flip-flop is presented. The output latch of the proposed circuit can be considered as an hybrid solution between the standard NAND-based set/reset latch and the NC-/sup 2/MOS approach. The proposed flip-flop provides ratioless design, reduced short-circuit power dissipation, and glitch-free operation. The simulation results, obtained for a 0.25-/spl mu/m technology, show improvements in the clock-to-output delay and the power dissipation with respect to the recently proposed high-speed flip-flops. The new circuit has been successfully employed in a high-speed direct digital frequency synthesizer chip, highlighting the effectiveness of the proposed flip-flop in high-speed standard cell-based applications. 相似文献
12.
《Electron Devices, IEEE Transactions on》2009,56(9):1787-1798
13.
Awwad F.R. Nekili M. Ramachandran V. Sawan M. 《IEEE transactions on circuits and systems. I, Regular papers》2008,55(1):322-335
14.
Ja Chun Ku Ismail Y. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2007,15(8):963-970
In this paper, the impact of thermal effects on low-power repeater insertion methodology is studied. An analytical methodology for thermal-aware repeater insertion that includes the electrothermal coupling between power, delay, and temperature is presented, and simulation results with global interconnect repeaters are discussed for 90- and 65-nm technology. Simulation results show that the proposed thermal-aware methodology can save 17.5% more power consumed by the repeaters compared to a thermal-unaware methodology for a given allowed delay penalty. In addition, the proposed methodology also results in a lower chip temperature, and thus, extra leakage power savings from other logic blocks. 相似文献
15.
Maheshwari A. Burleson W. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2004,12(12):1321-1329
This paper presents a differential current-sensing technique as an alternative to existing circuit techniques for on-chip interconnects. Using a novel receiver circuit, it is shown that, delay-optimal current-sensing is a faster (20% on an average) option as compared to the delay-optimal repeater insertion technique for single-cycle wires. Delay benefit for current-sensing increases with an increase in wire width. Unlike repeaters, current-sensing does not require placement of buffers along the wire, and hence, eliminates any placement constraints. Inductive effects are negligible in differential current-sensing. Current-sensing also provides a tighter bound on delay with respect to process variations. However, current-sensing has some drawbacks. It is power inefficient due to the presence of static-power dissipation. Current-sensing is essentially a low-swing signaling technique, and hence, it is sensitive to full swing aggressor noise. 相似文献
16.
BiCMOS circuit technology for a high-speed and large-capacity ECL-compatible static RAM (SRAM) is described. To obtain high-speed and low-power operation, a decoder with a pre-main decode configuration having an ECL-interface circuit and a word driver with BiCMOS inverter are proposed. A BiCMOS multiplexer with a single emitter-follower driver is also proposed. An optimization method for memory cell array configuration is presented that minimizes the total delay time and the total power dissipation of SRAMs. Circuit simulation results show that a 64-kbit ECL-compatible SRAM with an access time of less than 7 ns and a power dissipation of less than 1 W is obtainable 相似文献
17.
In this article, two consecutive augmenting transistor P-channel metal oxide semiconductor (ATPMOS) configurations are proposed. These two ATPMOS configurations (ST ATPMOS and DT ATPMOS) are implemented on a 4 × 1 (multiplexer) mux circuit. Leakage power dissipation, dynamic power dissipation and delay performance parameters are calculated for both (ST ATPMOS and DT ATPMOS) ATPMOS configurations-based 4 × 1 mux circuits at different values of transistor’s width. Due to simulation, it is realised that the leakage power dissipation and dynamic power dissipation are reduced and delay is improved (delay is reduced) in the DT ATPMOS configuration-based mux circuit compared to the ST ATPMOS configuration-based mux circuit. The whole simulation process was carried out in 45-nm technology. The circuits were operated at 1-V power supply. 相似文献
18.
El-Moursy M.A. Friedman E.G. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2005,13(8):971-975
Exponentially tapered interconnect can reduce the dynamic power dissipation of clock distribution networks. A criterion for sizing H-tree clock networks is proposed. The technique reduces the power dissipated for an example clock network by up to 15% while preserving the signal transition times and propagation delays. Furthermore, the inductive behavior of the interconnects is reduced, decreasing the inductive noise. Exponentially tapered interconnects decrease by approximately 35% the difference between the overshoots in the signal at the input of a tree. As compared to a uniform tree with the same area overhead, overshoots in the signal waveform at the source of the tree are reduced by 40%. 相似文献
19.
《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2008,16(9):1230-1239
20.
《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2009,17(9):1267-1274