Optimization of throughput performance for low-power VLSI interconnects

The technique of optimal voltage scaling and repeater insertion is analyzed in this paper to reduce power dissipation on global interconnects. An analytical model for the maximum bit-rate of a very large scale integration interconnect with repeaters has been derived and results are compared with HSPICE simulations. The analytical model is also used to study the effects of interconnect length and scaling on throughput. The throughput-per-bit-energy is analyzed to determine an optimum combination of supply voltage and repeaters for a low-power global interconnect with 250 nm /spl times/ 250 nm cross-sectional dimensions implemented with the 180 nm micro-optical silicon system technology node. It is shown that the optimal supply voltage is approximately equal to twice the threshold voltage. A case study illustrates that a combination of 1 V supply along with one repeater per millimeter increases the throughput-per-bit-energy to over three times that of a latency-centric interconnect of 2 V, which results in a 70% reduction in power dissipation without any loss of throughput performance.     

VLSI随机工艺变化下互连线建模与延迟分析

目前互连线的工艺变化问题已成为影响超大规模集成电路性能的重要因素.考虑了互连线工艺变化的空间相关性,将工艺参数变化建模为具有自相关性的随机过程,采用数值仿真及拟合方法得到寄生参数的近似表达式,最后基于Elmore延迟度量分析了随机工艺变化对互连延迟的影响,提出了工艺变化下互连延迟统计特性的估算方法,并通过仿真实验对方法的有效性进行了验证.     

Wire shaping of RLC interconnects

The optimum wire shape to produce the minimum signal propagation delay across an RLC line is shown to exhibit a general exponential form. The line inductance makes exponential tapering more attractive for RLC lines than for RC lines. For RLC lines, optimum wire tapering achieves a greater reduction in the signal propagation delay as compared to uniform wire sizing. For RLC lines, exponential tapering outperforms uniform repeater insertion. As technology advances, wire tapering becomes more effective than repeater insertion, since a greater reduction in the propagation delay is achieved. Optimum wire tapering achieves a reduction of 36% in the propagation delay in long RLC interconnect as compared to uniform repeater insertion.

Wire tapering can reduce both the propagation delay and power dissipation. Optimum tapering for minimum propagation delay reduces the propagation delay by 15% and power dissipation by 16% for an example circuit. The optimum tapering factor to minimize the transient power dissipation of a circuit is described in this paper. An analytic solution to determine the optimum tapering factor that exhibits an error of less than 2% is provided. Wire tapering is also shown to reduce the power dissipation of a circuit by up to 65%.

Wire tapering can also improve signal integrity by reducing the inductive noise of the interconnect lines. Wire tapering reduces the effect of impedance mismatch in digital circuits. The difference between the overshoots and undershoots in the signal waveform of an example clock distribution network is decreased by 34% as compared to a uniformly sized network producing the same signal characteristics.     

FDTD based transition time dependent crosstalk analysis for coupled RLC interconnects

The performance of high density chips operating in the GHz range is mostly affected by on-chip interconnects. The interconnect delay depends on many factors, a few of them are inputs toggling patterns, line ＆ coupling parasitics, input rise/fall time and source/load characteristics. The transition time of the input is of prime importance in high speed circuits. This paper addresses the FDTD based analysis of transition time effects on functional and dynamic crosstalk. The analysis is carried out for equal and unequal transition times of coupled inputs. The analysis of the effects of unequal rise time is equally important because practically, it is quite common to have mismatching in the rise time of the signals transmitting through different length wires. To demonstrate the effects, two distributed RLC lines coupled inductively and capacitively are taken into consideration. The FDTD technique is used because it gives accurate results and carries time domain analysis of coupled lines. The number of lumps in SPICE simulations is considered the same as those of spatial segments. To validate the FDTD computed results, SPICE simulations are run and results are compared. A good agreement of the computed results has been observed with respect to SPICE simulated results. An average error of less than 3.2% is observed in the computation of the performance parameters using the proposed method.     

Design and analysis of a low-swing driver scheme for long interconnects

Market forces are continually demanding devices with increased functionality/unit area; these demands have been satisfied through aggressive technology scaling which, unfortunately, has impacted adversely on the global interconnect delay subsequently reducing system performance. Line drivers have been used to mitigate the problems with delay; however, these have large power consumption. A solution to reducing the power dissipation of the drivers is to use lower supply voltages. However, by adopting a lower power supply voltage, the performance of the line drivers for global interconnects is impaired unless low-swing signalling techniques are implemented. The paper describes the design of a low-swing signalling scheme which consists of a low-swing driver, called the nLVSD driver which is an improved version of the MJ-driver [1] designed by Juan A. Montiel-Nelson and Jose C. Garcia. Subsequently, both low-swing driver schemes are analysed and compared focusing on their power consumption and performance characteristics, which are the main issues in present day IC design. A comparison between the two driver schemes showed that the nLVSD driver exhibited a 34% improvement regarding power consumption and a 28% improvement in delay when driving a 10 mm length of interconnect. A comparison between the two schemes was also undertaken in the presence of ±3σ Process and Voltage (PV) variations. The analysis indicated that the nLVSD driver scheme was more robust than the MJ-driver with a 33% and 44% improvement with respect to power consumption and delay variations. In order to further improve the robustness of the nLVSD scheme against process variation, the scheme was further analysed to identify which process variables had the most impact on circuit delay and power consumption. For completeness the effects of process variation on interconnect delay and power consumption was also undertaken.     

Bus encoder design for reduced crosstalk,power and area in coupled VLSI interconnects

This research work presents a novel circuit for simultaneous reduction of power, crosstalk and area using bus encoding technique in RC modeled VLSI interconnect. Bus-invert method is used to reduce inter-wire coupling, which is actually responsible for crosstalk, delay and power dissipation in coupled interconnects. The proposed method focuses on simplified and improved encoder circuit for 4, 8 and 16 coupled lines. In past, the researchers developed encoders that usually focused on minimizing power dissipation and/or crosstalk, thereby paying heavy penalty in terms of chip area. However, the proposed encoder and decoder while significantly reducing crosstalk demonstrates an overall reduction of power dissipation by 68.76% through drastically limiting switching activity. Furthermore, while reducing the complexity, chip area and transistor count of the circuit is reduced by more than 57%.     

TD-SCDMA直放站实现同步和切换的方法

随着第三代移动通信(简称3G)系统TD-SCDMA(时分同步码分多址)技术的不断成熟和3G牌照的即将发放,无线网络的建设和优化及TD-SCDMA直放站的广泛应用必不可少.本文介绍了一种简便实用的解决TD-SCDMA直放站实现同步和上下行切换的方法.     

现代通信直放站监控技术的分析与研究

对目前国内通信直放站的现状做了具体的分析,阐述了直放站监控技术的必要性.从结构、功能的角度对当前直放站监控系统做了具体的介绍,从硬件的角度分析了基于单片机监控系统发展过程及其工作原理,通过软件流程的研究,提出了软件设计方法.根据当前趋势简要说明了直放站监控系统的建设现状,并对今后的发展趋势做出展望.     

Detection and measurement of radio frequency feedback for an on‐frequency repeater

The radio frequency feedback (RFF) occurs when the insulation is insufficient between the antennas of an on‐frequency repeater, increasing digital transmission errors. In addition, a strong RFF could compromise system stability of the on‐frequency repeater because of the growing power in the closed‐loop. Automatic gain control is widely used by the on‐frequency repeater to regulate the power, this solution being generally used with echo cancellation processes. Most of echo cancellation techniques are based on digital processing such as adaptive filters whose the effectiveness and the algorithm speed are depending on the signal frequency, the bandwidth and the closed‐loop parameters. This paper describes a solution of RFF estimation and detection regardless of the receiving signal modulation. By using the frequency scanning and the analysis of the power spectral density peaks in the system, this solution is reliable whatever are the values of the gain‐margin and the loop‐delay. Simulations and experimental implementation using field‐programmable gate array validate the solution. In addition, an example of applications is given in the context of the interference cancellation.     

VLSI scaling methods and low power CMOS buffer circuit

Device scaling is an important part of the very large scale integration(VLSI) design to boost up the success path of VLSI industry, which results in denser and faster integration of the devices. As technology node moves towards the very deep submicron region, leakage current and circuit reliability become the key issues. Both are increasing with the new technology generation and affecting the performance of the overall logic circuit. The VLSI designers must keep the balance in power dissipation and the circuit’s performance with scaling of the devices. In this paper, different scaling methods are studied first. These scaling methods are used to identify the effects of those scaling methods on the power dissipation and propagation delay of the CMOS buffer circuit. For mitigating the power dissipation in scaled devices, we have proposed a reliable leakage reduction low power transmission gate(LPTG) approach and tested it on complementary metal oxide semiconductor(CMOS) buffer circuit. All simulation results are taken on HSPICE tool with Berkeley predictive technology model(BPTM) BSIM4 bulk CMOS files. The LPTG CMOS buffer reduces 95.16% power dissipation with 84.20% improvement in figure of merit at 32 nm technology node. Various process, voltage and temperature variations are analyzed for proving the robustness of the proposed approach. Leakage current uncertainty decreases from 0.91 to 0.43 in the CMOS buffer circuit that causes large circuit reliability.     

The analytical model for crosstalk noise of current-mode signaling in coupled RLC interconnects of VLSI circuits

With the continuous advancement of semiconductor technology,the interconnects crosstalk has had a great influence on the performances of VLSI circuits.To date,most of the research about the interconnects of VLSI circuits focus on the voltage-mode signaling (VMS) scheme while the current-mode signaling (CMS) scheme is rarely analyzed.First of all,an equivalent circuit model of two-line coupled interconnects is presented in this paper, which is applicable to both the CMS and VMS schemes.The coupling capacitive and mutual inductive are taken into account in the equivalent circuit model.Secondly,the output noise of CMS and VMS schemes are investigated in the paper according to the decoupling technique andABCD parameter matrix approach at local level,intermediate level and global level,respectively.Moreover,the experimental results show that the CMS interconnects have lesser noise peak,noise width and noise amplitude than the VMS interconnects in the same cases,and the CMS scheme is especially suitable for the global interconnects communication of VLSI circuits.It is found that the results obtained by ABCD parameter matrix approach are in good accordance with the simulation results of the advanced design system.     

High-speed low-power voltage-programmed driving scheme for AMOLED displays

A new voltage-programmed driving scheme named the mixed parallel addressing scheme is presented for AMOLED displays, in which one compensation interval can be divided into the first compensation frame and the consequent N-1 post-compensation frames without periods of initialization and threshold voltage detection. The proposed driving scheme has the advantages of both high speed and low driving power due to the mixture of the pipeline technology and the threshold voltage one-time detection technology. Corresponding to the proposed driving scheme, we also propose a new voltage-programmed compensation pixel circuit, which consists of five TFTs and two capacitors(5T2C). In-Zn-O thin-film transistors(IZO TFTs) are used to build the proposed 5T2C pixel circuit. It is shown that the non-uniformity of the proposed pixel circuit is considerably reduced compared with that of the conventional 2T1C pixel circuit. The number of frames(N) preserved in the proposed driving scheme are measured and can be up to 35 with the variation of the OLED current remaining in an acceptable range. Moreover, the proposed voltage-programmed driving scheme can be more valuable for an AMOLED display with high resolution, and may also be applied to other compensation pixel circuits.     

平行光纤互联技术：高性能和低能耗的结合

This paper analyzes the physical potential,computing performance benefit and power consumption of optical interconnects. Compared with electrical interconnections, optical ones show undoubted advantages based on physical factor analysis. At the same time, since the recent developments drive us to think about whether these optical interconnect technologies with higher bandwidth but higher cost are worthy to be deployed, the computing performance comparison is performed. To meet the increasing demand of large-scale parallel or multi-processor computing tasks, an analytic method to evaluate parallel computing performance of interconnect systems is proposed in this paper. Both bandwidth-limit model and full-bandwidth model are under our investigation. Speedup and efficiency are selected to represent the parallel performance of an interconnect system. Deploying the proposed models, we depict the performance gap between the optical and electrically interconnected systems. Another investigation on power consumption of commercial products showed that if the parallel interconnections are deployed, the unit power consumption will be reduced. Therefore, from the analysis of computing influence and power dissipation, we found that parallel optical interconnect is valuable combination of high performance and low energy consumption. Considering the possible data center under construction, huge power could be saved if parallel optical interconnects technologies are used.     

Annealing textures of copper damascene interconnects for ultra-large-scale integration

The annealing textures of copper interconnects depend upon their deposition textures and geometries. The copper interconnects are subjected to tensile stresses even at room temperature, which in turn gives rise to strain energies. The stress distributions in interconnects are not homogeneous due to trenches, resulting in non-fiber-type textures after annealing. To better understand the formation of the non-fiber-type textures, the textures of specimens of 0.2–6 μm in trench width with 0.2 μm in space were measured, and the strain energy and stress distributions have been simulated. The simulation results indicate that strain energy density is highest at the upper corners of trench. Therefore, the grain growth rate at the upper corners is fastest, resulting in the {111}〈110〉 annealing texture. As the trench width increases, the influence of stresses in the trench increases, even though the strain energy density in the trench is relatively low. In this case the {111}〈112〉 component increases, even though the formation of the {111}〈110〉 orientation cannot be excluded.     

无线RS485中继器用电信息采集系统中应用探索

根据2010年国家电网公司智能表更换工程的实施,近几年成武公司智能电能表的使用普及率已经达到了100%,单在实际运行过程中,用电信息采集系统常出现电能表信息采集率不高,通讯故障等问题,文章就其出现问题进行探索和研究。     

光致聚合物用于全息光互联光栅的研究

使用光致聚合物做记录介质,记录用于光互联的全息光栅。激光曝光后衍射效率可达5 5 %左右,用紫外光均匀照射后,在10 0℃下烘烤40分钟,衍射效率可达90 %左右。绘制了衍射效率与曝光时间和烘烤时间曲线,制作具有预期衍射效率的用于全息光互联的光栅。     

改进的合成孔径雷达间歇采样转发干扰

针对合成孔径雷达欺骗干扰过程中雷达参数侦测困难以及传统间歇采样导致假目标滞后的问题,提出一种改进的间歇采样转发方式,通过对采样存储的信号进行处理,根据线性调频信号延迟与频率偏移耦合的特征达到假目标串前移的效果,从而有效保护干扰机附近区域的场景目标.定量分析了假目标位置与信号处理阶数和延迟量的关系,仿真给出了不同参数情况下假目标串的干扰效果.改进方法在保留了间歇采样所有优势的情况下,解决了假目标滞后的问题,同时也隐藏了传统移频干扰会导致中心频率偏移的特征,并且所形成假目标的位置与雷达信号调频斜率无关,适用于雷达脉间调频斜率捷变的情况.     

基于单壁碳纳米管束的三维互连线设计与分析

Metallic carbon nanotubes(CNTs) have been proposed as a promising alternative to Cu interconnects in future integrated circuits(ICs) for their remarkable conductive, mechanical and thermal properties. Compact equivalent circuit models for single-walled carbon nanotube(SWCNT) bundles are described, and the performance of SWCNT bundle interconnects is evaluated and compared with traditional Cu interconnects at different interconnect levels for through-silicon-via-based three dimensional(3D) ICs. It is shown that at a local level, CNT interconnects exhibit lower signal delay and smaller optimal wire size. At intermediate and global levels, the delay improvement becomes more significant with technology scaling and increasing wire lengths. For 1 mm intermediate and 10 mm global level interconnects, the delay of SWCNT bundles is only 49.49% and 52.82% that of the Cu wires, respectively.     

Thermomechanical failures in microelectronic interconnects

Thermomechanical fatigue failures are an important class of failures in microelectronic interconnect structures. Thermomechanical stresses arise from differences in the coefficients of thermal expansion of the various materials comprising a microelectronics circuit. Polymer dielectrics and adhesives have larger coefficients of expansion than metal conductors. Dielectrics and adhesives may also exhibit large anisotropy in the coefficient of expansion, producing significant thermomechanical stresses in vias or other metal interconnect structures. During ambient thermal cycling or operational power dissipation, cyclic stresses are induced, which cause fatigue failures. The basic elements of thermomechanical fatigue behavior of microelectronic interconnect structures, such as lines and vias, are presented in this paper. In addition, a case study illustrating many of the concepts is presented for a complex 3-D interconnect.