Switchless compact dual-band matching networks for class-E power amplifiers

Two compact switchless dual-band load networks for class-E power amplifier (PA) operating at 800 and 1900 MHz are proposed, featuring small area and low loss which will be suitable for non-concurrent dual-band PA module in handset. Theoretical analysis and design equations are provided along with a loss model, including loss in the transistor and in the load network. Loss model is extracted for each structure to find the design parameters for optimized and balanced efficiency in both bands. Both designs are fabricated on Rogers RO4003 substrate with lumped components. Full PA simulations of both bands are carried out with co-simulation using a Triquint TGF2023-2-10 GaN transistor model, lumped components and EM models of load network layouts for both structures. The PA with transformer-based load network achieves a power added efficiency of 68.6 % at low band and 62.6 % at high band at an output power of 37.8 and 36.7 dBm respectively. The overall area consumed by the load network is 13.5 × 9.6 mm². The LC-based PA has a similar PAE of 68.3 and 60 % at low band and high band, respectively. The output power is 38.1 dBm in the low band and 37 dBm in the high-band. The overall area consumed by the load network is 9 × 10 mm²     

Design of efficient power amplifier for low power transmitters

This paper presents a fully integrated, low transmit-power and high-efficiency 2.4 GHz class-E power amplifier (PA) in TSMC 0.18 μm CMOS process for low-power transmitters such as wireless sensor networks (WSN). In this paper, a new output load has been proposed. Also, analytical design equations have been included to design an efficient low power circuit. This PA, employs the pad capacitance and bond-wire inductance of the output node, for satisfying class-E zero-voltage switching (ZVS) condition and matching the antenna’s 50 Ω resistance. By using bond-wire inductance instead of inductor in the output filter, smaller chip size and higher efficiency has been achieved compared to other works for low transmit-power applications. Also, the effectiveness of bulk-drive technique on faster switching and increasing efficiency have been evaluated. It has been proved that this technique leads to increase the efficiency of switching PAs. This PA delivers a range of output power from 2.7 to 7.2 dBm with a supply voltage range from 500 to 850 mV while achieving overall power efficiency range of 57.3–60.7%.     

A parallel circuit differential class-E power amplifier using series capacitance

Class-E amplifiers are attractive for wireless handsets because of their high efficiency and simple implementation. However, it requires inductors in its output matching network that are inherently low Q components affecting efficiency and may require significantly large area in fully integrated implementation. In this paper a novel approach of implementing parallel circuit differential class-E amplifier is presented. Instead of using an inductor parallel to the transistor drain of each amplifier, a single capacitor at the single ended side of the balun provides the parallel inductance effect to the switching transistors. As a result, number of inductors required for circuit implementation is reduced which means reduced losses, less area and better tuning of reactance can be achieved. A test circuit is implemented in 0.13 μm CMOS process. Measurement results verify the validity of the concept. The Power Amplifier achieves 22 dBm output power at 2.4 GHz from a 2.5 V with an overall Power Added Efficiency of 38 %.     

LDMOS管并联电容提取及E类功率放大器设计

研制了2.14GHz频段横向扩散金属氧化物半导体(LDMOS)晶体管的高效率E类功率放大器。采用并联谐振法结合ADS软件仿真提取出管子的关键参数Cds,并在此基础上进行电路仿真,设计了馈电网络和负载匹配网络,有效抑制谐波分量。给出了功率放大器的实验结果,输出功率达到38.55dBm时,附加效率达到64.1%,与仿真结果吻合良好。     

S波段高效F类/逆F类GaN HEMT功率放大器设计

为了解决F类和逆F类（F-1类）功率放大器设计过程中受晶体管寄生参数影响,导致功放效率低以及输出匹配电路结构复杂的问题,提出了一种新型的输出匹配电路结构.首先,在直流偏置线中加入谐波调谐功能,避免单独设计谐波控制电路;其次,为满足F类和F-1类功放在器件本征漏极端所需的阻抗状态,匹配寄生参数呈现的封装端谐波阻抗,采用一段L型传输线结构代替传统的L-C集总元件寄生补偿方法;最后,由两段串联的传输线实现最优基波阻抗与50 Ω负载间的匹配.为验证方法的有效性,采用CGH40010氮化镓高电子迁移率晶体管（Gallium nitride high electron mobility transistor,GaN HEMT）器件,设计并加工了两款工作在2.4 GHz的F类和F-1类功放.测试结果显示:F类功放的峰值功率附加效率（power added efficiency,PAE）为75.5%,饱和输出功率为40.8 dBm;F-1类功放的峰值PAE为77.6%,饱和输出功率为40.3 dBm.该方法降低了电路复杂度和设计难度,可以较容易地补偿晶体管寄生参数,功放在高频工作时的效率得到提升,为利用GaN HEMT器件设计高效功放提供了一种可行的方案.     

Performance Study of a Class-E Power Amplifier With Tuned Series-Parallel Resonance Network

This paper reports on a modified class-E amplifier with a tuned series-parallel resonance network. This configuration introduces two additional resonance frequencies. The design equations required to determine the optimum operations are analyzed in detail by introducing three additional boundary conditions. compared to the conventional class-E amplifier, the numerical results show that the improvements on load resistance, maximum transistor current, power output capability, and maximum frequency can be obtained by properly selecting the resonance frequencies of the tuned network. Comparisons between simulations and measurements of an experimental circuit of the new configuration are drawn to validate the feasibility. The drain efficiency of 81.77%, power-added efficiency of 79.58%, and output power of 32.71 dBm (1.866 W) at 250 MHz are measured.     

Broadband high-efficiency circularly polarized active antenna and array for RF front-end application

This paper presents a broadband high-efficiency circularly polarized (CP) active integrated antenna, and a broadband CP active array at 2 GHz. To realize the broadband CP antenna, a circular patch is aperture coupled by crossed slots in the ground plane, which are fed by an L-shaped microstrip feed line below the ground. The antenna is designed to serve the functions of both a radiator and a harmonics-terminated load for class-E high-efficiency power-amplifier (PA) integration. The broadband CP active antenna is realized by directly integrating the broadband CP antenna with the class-E PA. It achieves a 9% bandwidth (1.84-2.01 GHz) for axial ratio (AR) below 3 dB, and a 12% bandwidth for power-added efficiency (PAE) over 60%. To form the broadband CP active array, four active antenna elements are sequentially rotated, and each element is directly integrated with broadband class-E PA. A low-cost printed-circuit-board technology is employed in fabrication and a pseudomorphic high electron-mobility transistor is used. A peak drain efficiency of 71.5% for the class-E amplifier is measured at 1.95 GHz. The active array achieves a peak-effective radiated power of 39.7 dBm, and PAE is over 50% within a 22.6% bandwidth (1.72-2.16 GHz). The AR is below 3 dB over a 27% bandwidth (1.72-2.26 GHz).     

Design of 35 GHz 1 Watt GaAs pHEMT Power Amplifier MMIC

By using 0.15μm GaAs pHEMT (pseudomorphic high electron mobility transistor)technology,a design of millimeter wave power amplifier microwave monolithic integrated circuit(MMIC)is presented.With careful optimization on circuit structure,this two-stage power amplifier achieves a simulated gain of 15.5dB with fluctuation of 1 dB from 33 GHz to 37GHz.A simulated output power of more than 30dBm in saturation can be drawn from 3 W DC supply with maximum power added efficiency(PAE)of 26%.Rigorous electromagnetic simulation is performed to make sure the simulation results are credible.The whole chip area is 3.99mm2 including all bond pads.     

19WC-波段MMIC多芯片合成功率放大器

报告了一个两级 C-波段功率单片电路的设计、制作和性能 ,该单片电路包括完全的输入端和级间匹配 ,输出端的匹配在芯片外实现 ,该放大器在 5.2～ 5.8GHz带内连续波工作 ,输出功率大于 36.6d Bm,功率增益大于 18.6d B,功率附加效率 34 % ,4芯片合成的功率放大器在 4 .7～ 5.3GHz带内 ,输出功率大于 4 2 .8d Bm( 19.0 W) ,功率增益大于 18.8d B,典型的功率附加效率为 34 %。     

A class-E power amplifier for wireless biomedical systems

This letter presents the design, implementation and experimental results of a class-E power amplifier (PA) suitable for wireless biomedical sensor nodes (WBSNs) integrated into a wireless body area network (WBAN). A self-biased inverter is used as a preamplifier stage to provide a 50 %-duty-cycle square wave to drive the class-E PA. The design (PA with the preamplifier), which is fabricated in a 0.18-μm CMOS technology, achieves 40.2 % drain efficiency while output power is 14.7 dBm at 433 MHz under 1.2-V supply, as demonstrated by the experimental results.     

A 60 GHz SiGe-HBT Power Amplifier With 20% PAE at 15 dBm Output Power

A monolithic power amplifier (PA) operating in the 60 GHz band is presented. The circuit has been designed utilizing an advanced 0.25 SiGe-heterojunction bipolar transistor (HBT) technology, featuring npn transistors with and . A two-stage cascode architecture has been chosen for the implementation. Design techniques and optimization procedure are explained in detail. Measurements show a small signal gain of 18.8 dB and an output power of 14.5 dBm under 1 dB gain compression at 61 GHz. At this frequency, the saturated output power is 15.5 dBm and the peak power added efficiency (PAE) is 19.7%. To our knowledge, this is the highest PAE reported so far for a monolithic 61 GHz PA in SiGe-HBT technology.     

An RF Power Amplifier in a Digital CMOS Process

A two stage class B power amplifier for 1.9 GHz is presented. The amplifier is fabricated in a standard digital EPI-CMOS process with low resistivity substrate. The measured output power is 29 dBm in a 50 load. A design method to find the large signal parameters of the output transistor is presented. It separates the determination of the optimal load resistance and the determination of the large signal drain-source capacitance. Based on this method, proper values for on-chip interstage matching and off-chip output matching can be derived. A envelope linearisation circuit for the PA is proposed. Simulations and measurements of a fabricated linearisation circuit are presented and used to calculate the achievable linearity in terms of the spectral leakage and the error vector magnitude of a EDGE (3/8-8PSK) modulated signal.     

Experimental class-F power amplifier design using computationally efficient and accurate large-signal pHEMT model

This paper presents an experimental high-efficiency class-F power amplifier (PA) design, which integrates Rhodes's efficient low-pass matching network topology with the charge conservative, robust, and accurate WREN/COBRA nonlinear pseudomorphic high electron-mobility transistor (pHEMT) model for optimal drain efficiency. Large-signal model verification is undertaken where one-tone, load-pull, and wireless code-division multiple-access baseband time-domain tests are compared for simulated and experimental cases. Following a detailed theoretical analysis, a class-F matching network is proposed that suppresses the necessary load harmonics and delivers maximum drain efficiency. Utilizing the GaAs pHEMT model in computer-aided design, a microstrip matching network layout was generated and built at 2 GHz. The drain efficiency recorded for the first-pass effort was 70.5% with the use of no post-fabrication circuit tuning. Excellent agreement is also observed between the PAs simulated and measured performance, thus highlighting the advantages of an accurate device model in PA design.     

A high efficiency transmitter and receiver for magnetic resonant wireless battery charging system in 0.35 μm BCD

This paper presents a transmitter and receiver for magnetic resonant wireless battery charging system. In the receiver, a wide-input range CMOS multi-mode active rectifier is proposed for a magnetic resonant wireless battery charging system. The configuration is automatically changed with respect to the magnitude of the input AC voltage. The output voltage of the multi-mode rectifier is sensed by a comparator. Furthermore, the configuration of the multi-mode rectifier is automatically selected by switches as original rectifier mode, 1-stage voltage multiplier or 2-stage voltage multiplier mode. As a result, a rectified DC voltage is output from 7.5 to 19 V for an input AC voltage of 5–20 V. In the transmitter, a class-E power amplifier (PA) with an automatic power control loop and load compensation circuit is proposed to improve the power efficiency. The transmitted power is controlled by adjusting the signal applied to the gate of the power control transistor. In addition, a parallel capacitor is also controlled to enhance the efficiency and compensate for the load variation. This chip is implemented using 0.35 μm BCD technology with an active area of around 5,000 × 2,500 μm. When the magnitude of the input AC voltage is 10 V, the power conversion efficiency of the multi-mode active rectifier is about 94 %.The maximum power efficiency of the receiver is about 70 %. The transmitter provides an output power control range of 10–30.2 dBm. The maximum power efficiency of the PA is 71.5 %.     

A high-efficiency class-E GaN HEMT power amplifier at 1.9 GHz

A single stage class-E power amplifier in GaN high electron mobility transistor (HEMT) technology is reported. The circuit operates at 1.9 GHz. At 30-V drain bias, a power-added-efficiency (PAE) of 57% and a maximum output power of over 37dBm was achieved, corresponding to a power density of 5.25W/mm. At 40-V drain bias, an output power of 38.7dBm is achieved at 50% PAE corresponding to a power density of 7.4W/mm.     

A 3.4-3.6 GHz power amplifier in an InGaP/GaAs HBT

This paper presents a 3.4-3.6 GHz power amplifier（PA） designed and implemented in InGaP/GaAs HBT technology.By optimizing the off-chip output matching network and designing an extra input-matching circuit on the PCB,several problems are resolved,such as resonant frequency point migration,worse matching and lower gain caused by parasitics inside and outside of the chip.Under V_cc = 4.3 V and V_bias = 3.3 V,a P_1dB of 27.1 dBm has been measured at 3.4 GHz with a PAE of 25.8%,the 2nd and 3rd harmonics are -64 dBc and -51 dBc,respectively. In addition,this PA shows a linear gain more than 28 dB with S₁₁<-12.4dB and S₂₂<-7.4 dB in 3.4-3.6 GHz band.     

应用于无线传感器网络的功率放大器的设计

给出一种基于TSMC 0.18 μm RF CMOS工艺,应用于无线传感器网络的2.4 GHz 功率放大器的设计.该功率放大 器工作频率范围为2.4 GHz～2.4835 GHz,采用全差分AB类共源共栅电路结构,使用功率控制技术以节省功耗,当输入信号 功率-12.5 dBm时,输出功率在-10.4 dBm至5.69 ...     

2.4GHz 0.35-μm CMOS全集成线性功率放大器设计

片上系统射频功率放大器是射频前端的重要单元.通过分析和对比各类功率放大器的特点,电路采用SMIC0.35-μm CMOS工艺设计2.4 GHz WLAN全集成线性功率放大器.论文中设计的功率放大器采用不同结构的两级放大,驱动级采用共源共栅A类结构组成,输出级采用共源级大MOSFET管组成.电路采用SMIC 0.35-μ...     

CMOS linear high performance push amplifier for WiMAX power amplifier

In this work a novel and efficient approach is proposed to optimize the linearity and efficiency of power amplifiers used in mobile WiMAX applications. A linear and high performance push amplifier is designed and implemented in 0.18 μm CMOS technology to enhance the linearity of a class-E switched-mode power amplifier. The proposed push amplifier consists of two sections; analog and switching sections. The analog section provides required linearity and the switching section guarantees satisfying total efficiency level. Each block is designed and optimized to meet required specifications. The core power amplifier which is a class-E switched-mode power amplifier is also designed to have maximum possible efficiency. The implemented circuit is simulated using HSPICERF and TSMC models for active and passive elements. The proposed power amplifier provides a maximum output power of 25 dBm and a power added efficiency (PAE) as high as 48% at 2.5 GHz operation frequency and supply voltage of 1.8 V. At 1 dB compression point this PA exhibits 23 dBm of output power with 42% PAE and 4.5% EVM which was appropriate for 64QAM OFDM signals.     

一种新型双频宽负载整流电路

提出一种新型双频宽负载整流电路,它能有效回收环境中的微波电磁能量.该整流电路主要由阻抗压缩匹配网络、肖特基二极管和低通滤波器构成.其中,阻抗压缩匹配网络由一个L型阻抗调节器和一个Ⅱ型阻抗匹配器组成,该网络能够在200 ～ 4000Ω的负载区间内减小输入阻抗的变化范围,从而提高整流电路的匹配性能.ADS 2017软件仿真...