Analytical model of GaAs MESFET's

A simple analytical model of GaAs MESFET's is proposed. The model is based on the assumption that the current saturation in GaAs MESFET's is related to the stationary Gunn domain formation at the drain side of the gate rather than to a pinchoff of the conducting channel under the gate. The saturation current, channel conductance, transconductance, charge under the gate, gate-to-source and drain-togate capacitances, cutoff frequency, characteristic switching time, power-delay product, and breakdown voltage are calculated in the frame of this model. The results are verified by two-dimensional computer calculations. They agree well with the results of the computer analysis and experimental data for a 1-µm gate GaAs MESFET. It is shown that a stray gate-to-drain and gate-to-source capacitance sets up a limitation of a gate length which must be larger than or about 0.1 µm for a GaAs MESFET.     

Effect of mesh spacing on static negative resistance in GaAs MESFET simulation

Norton [1], [2] has postulated that the negative differential resistance in the drain characteristics of GaAs MESFET's which is predicted by device simulations may arise solely because the computational mesh spacing is too large, and he has presented finite difference calculations showing the effect in InP. This letter describes a 0.25-µm-gate length GaAs MESFET which is simulated in two dimensions using the finite-element method. The drain current calculated reveals a static negative differential resistance region for low drain-source and gate-source bias voltages. The value of the drain current and the differential negative resistance calculated are insensitive to the mesh spacing until extremely coarse mesh spacings are used. The grid constraint of Norton is, therefore, seen to be too stringent for the simulation of GaAs MESFET's with static negative differential resistance.     

Negative differential conductivity and isothermal drain breakdownof the GaAs MESFET

Electrical breakdown in GaAs MESFET's is simulated by two-dimensional (2-D) quasi hydrodynamic isothermal model with two types of carriers and “mixed” boundary conditions on the contacts-fixed drain current and fixed gate bias. It was demonstrated, that when some maximum drain voltage is reached the MESFET's differential conductivity becomes negative at every gate bias. The negative differential conductivity (NDC) is caused by the electric field reconstruction in the buffer by the injected carrier space charge. It is shown that the suggested breakdown model corresponds to the experimentally observed properties of the drain breakdown of the GaAs MESFET. The instantaneous burnout of the GaAs MESFET at the drain breakdown is explained by the uncontrollable drain current increase due to the NDC formation     

Surface-Oriented Transferred-Electron Devices

The application of MESFET technology to the manufacturing of surface-oriented transferred-electron devices (TED's) with parmeters close to GaAs MESFET's is discussed. The limitations related to the contact resistance, fringing capacitance, domain formation time, impact ionization, and heat sinking are analyzed for GaAs and InP devices. Our estimates show that the surface-oriented devices can be used as microwave LSA generators at higher frequencies than the conventional LSA diodes. In a domain mode, the surface-oriented TED's can yield low values of the power-delay product comparable to those of GaAs MESFET's at higher speeds. The analysis of impact ionization within a high-field domain leads to a conclusion that even InP logic devices with practical lengths of the active layer can be manufactured with doping densities up to 10/sup 17/cm/sup -3/. The estimate of the temperature rise indicates that a CW operation is possible for practical device parameters. Because the parameters of surface-oriented TED's are similar to those of GaAs MESFET's they may be manufactured using the rapidly developing GaAs integrated-circuit technology and used in combination with GaAs MESFET's.     

GaAs MESFET's with partial p-type drain regions

The use of a localized p-type region in the drain of a GaAs MESFET has been studied. Holes injected from this p-region compensate the negative space charge region at the channel-substrate interface, minimizing undesirable substrate effects. The MESFET's fabricated with p-type drain regions (called p-FET's) exhibited I-V characteristics with less hysteresis and low light sensitivity compared to standard n-type drain MESFET's. Also, less backgating effect has been observed in these p-FET's than in standard MESFET's.     

A comparative analysis of GaAs and Si ion-implanted MESFET's

In this work, numerical calculations of device characteristics including theI-Vcharacteristic, small-signal parameters, and cutoff frequency are reported for silicon-implanted MESFET devices. The device dimensions and impurity profile are similar to those of GaAs MESFET's. Although Si MESFET devices have not found practical applications, these calculations provide a good comparison of the intrinsic frequency limits of GaAs and Si. Comparative analysis shows that there are differences in the magnitude of the small-signal parameters and channel current between GaAs and Si MESFET devices with the same geometries and implanted profiles. However, the general variations of small-signal parameters with respect to the drain voltage is similar for both materials. In addition, the calculations show that a 1-µm channel length GaAs MESFET device has a higher cut-off frequency by a factor of 1.8 than a similar Si MESFET. These results indicate that GaAs devices are intrinsically better suited for very high-speed switching devices.     

Buried-channel GaAs MESFET's with immunity to ionizing optical radiation effects

The effects of high-intensity visible light upon various GaAs MESFET structures are examined and compared. The buried-channel MESFET's were found to be insensitive to ionizing radiation both in terms of increases of the drain current due to photocurrents and in terms of long-term transients due to charging of deep levels as is found in standard FET's. These results indicate that the buried-channel MESFET's should be significantly more immune to transient radiation effects in severe radiation environments.     

InP Schottky-gate field-effect transistors

MESFET's with gates 1 µm long were fabricated in LPE layers of InP on Cr-doped InP substrates. The quality of the LPE material is characterized by an electron concentration of 4 × 10¹⁵cm^-3with a mobility of 2.6 × 10⁴cm²V^-1s^-1at 77 K for growths from undoped melts. The devices have current gain cutoff frequencies of 20 GHZ or somewhat larger. This value is greater than that of the best analogous GaAs MESFET bya factor of 1.5. A factor of 1.3 is predicted on the basis of a simple theory. The highest power gain cutoff frequency, fmax, for the InP device is 33 GHz which is somewhat smaller than that of the best analogous GaAs device. The lowest minimum noise figure at 10 GHz for these first InP devices is 3.9 dB with an associated gain of 4.8 dB. The best result for the GaAs counterpart is 3.2 dB with an associated gain of 7.8 dB. The power gain of the InP device suffers compared to the GaAs device because of degenerative feedback resulting from a large gate-to-drain capacitance and because of a small output resistance. If the magnitudes of these two equivalent circuit elements were the same for MESFET's in the two materials, fmaxfor the InP device would be more than double its present value.     

A self-aligned gate GaAs MESFET with p-pocket layers forhigh-efficiency linear power amplifiers

This paper describes a newly developed GaAs metal semiconductor field-effect transistor (MESFET)-termed p-pocket MESFET-for use as a linear power amplifier in personal handy-phone systems. Conventional buried p-layer technology, the primary technology for microwave GaAs power MESFET's, has a drawback of low power efficiency for linear power applications. The low power efficiency of the buried p-layer MESFET is ascribed to the I-V kink which is caused by holes collected in the buried p-layer under the channel. In order to overcome this problem, we have developed the self-aligned gate p-pocket MESFET which incorporates p-layers not under the channel but under the source and drain regions. This new MESFET exhibited high transconductance and uniform threshold voltage. The problematic I-V kink was successfully removed and an improved power efficiency of 48% was achieved under bias conditions, which resulted in adjacent channel leakage power at 600-kHz offset as low as -59 dBc for 1.9-GHz π/4-shift QPSK modulated input     

GaAs MESFET's fabricated on InP substrates

This paper reports the first successful MESFET fabrication in GaAs layers grown directly on InP substrates by molecular beam epitaxy (MBE). The fabricated GaAs MESFET's exhibit good I-V curves with complete pinch-off and saturation characteristics. About 100-mS/ mm transconductance was obtained for a 1.2-µm gate length device.     

Comparison of SiC, GaAs, and Si RF MESFET power densities

The maximum power density of Si, GaAs, and 4H-SiC MESFET's was modeled using material parameters, a planar MESFET cross section, and a piecewise linear MESFET drain characteristic. The maximum power density for the Si, GaAs, and 4H-SiC was calculated to be 0.45 W/mm, 0.78 W/mm, and 17.37 W/mm at drain voltages of 8.4 V, 8.3 V, and 105 V, respectively. Modeling power density as a function of drain voltage showed that, for low voltage applications, the GaAs MESFET has the highest power density because of its high electron mobility and very low channel resistance (R_on). For high voltage applications, the 4H-SiC MESFET has the highest absolute power density because of the higher breakdown voltage of this material. Experiment data agree qualitatively with the modeled results     

Enhanced GaAs MESFET CAD model for a wide range of temperatures

We describe a new and enhanced GaAs MESFET model suitable for implementation in computer aided design (CAD) software packages such as, for example, SPICE. The model accurately reproduces both above-threshold and subthreshold characteristics of GaAs MESFET's in a wide temperature range, from 77 K to 350/spl deg/C. The current-voltage characteristics are described by a single continuous, analytical expression for all regimes of operation. The physics-based model includes effects such as velocity saturation in the channel, drain induced barrier lowering, finite output conductance in saturation, bias dependent series source and drain resistances, effects of bulk charge, bias dependent average low-field mobility, frequency dependent output conductance, backgating and sidegating, and temperature dependent model parameters. The output resistance and the transconductance are also accurately reproduced, making the model suitable for analog CAD.<>     

Stability of performance and interfacial problems in GaAs MESFET's

Interface effects in GaAs MESFET's were investigated from the viewpoint of stability of performance. It was clarified, on the basis of a simple analytical model, that even a small fluctuation of the effective channel thickness due to interface effects causes drastic changes or drifts in performance characteristics of a GaAs MESFET. Paying attention mainly to the behavior of drain current, the interface effects were experimentally investigated for VPE-gown 1-µm-gate GaAs MESFET's with and without a buffer layer. It was revealed that they are due to deep acceptors or hole traps, which exist at the interfaces and in the buffer layer and the semi-insulating substrate, and found that the long-term drift is attributed to Cr in the buffer layer as well as in the semi-insulating substrate.     

Stationary charge domain in GaAs MESFETs: dimensional and electrical characterisation

Numerical results of the location, size and voltage associated with stationary dipole charge layers in GaAs MESFETs and their dependences on gate and drain bias are presented. The results suggest the need of more analytical work describing the domain characteristics for a better understanding of how the dipole charge layer influences GaAs MESFET operation.<>     

A comprehensive analytical model for III-V compound MISFET's

A one-dimensional analytical model for III-V compound deep-depletion-mode MISFET's is developed. The model calculates transconductance, drain resistance, and gate capacitance beyond current saturation where these devices are normally operated-a regime not treated by other MISFET models. It is shown that insulator thicknesses less than 50 nm and surface state densities less than 1 × 10¹²eV^-1. cm^-2will be required for optimum MISFET devices. In a comparison of the expected performance differences between GaAs, InP, and InGaAs FET devices with similar geometries, it is shown that InP and InGaAs MISFET's will have lower gate capacitance, a greater cut-off frequency, and up to 2-dB improvement in minimum noise figure compared with a GaAs MESFET. Device characteristics predicted by this model agree with measured values to an accuracy of ±20 percent, which is well within the accuracy with which the modeled input parameters can be measured. This represents a factor of two improvement in accuracy when compared to other MISFET models. The model predicts the characteristics expected for a MESFET device in the limit of zero insulator thickness.     

A dc and microwave comparison of GaAs MESFET's on GaAs and Si substrates

In order to assess GaAs on Si technology, we have made a performance comparison of GaAs MESFET's grown and fabricated on Si and GaAs substrates under identical conditions and report the first microwave results. The GaAs MESFET's on Si with 1.2-µm gate length (290-µm width) exhibited transconductances (gm) of 180 mS/mm with good saturation and pinchoff whereas their counterparts on GaAs substrates exhibited gmof 170 mS/mm. A current gain cut-off frequency of 13.5 GHz was obtained, which compares with 12.9 GHz observed in similar-geometry GaAs MESFET's on GaAs substrates. The other circuit parameters determined from S-parameter measurements up to 18 GHz showed that whether the substrate is Si or GaAs does not seem to make a difference. Additionally, the microwave performance of these devices was about the same as that obtained in devices with identical geometry fabricated at Tektronix on GaAs substrates. The side-gating effect has also been measured in both types of devices with less than 10-percent decrease in drain current when 5 V is applied to a pad situated 5 µm away from the source. The magnitude of the sidegating effect was identical to within experimental determination for all side-gate biases in the studied range of 0 to -5 V. The light sensitivity of this effect was also very small with a change in drain current of less that 1 percent between dark and light conditions for a side gate bias of -5 V and a spacing of 5 µm. Carrier saturation velocity depth profiles showed that for both MESFET's on GaAs and Si substrates, the velocity was constant at 1.5 × 10⁷cm/s to within 100-150 Å of the active layer-buffer layer interface.     

Submicron Single-Gate and Dual-Gate GaAs MESFET's with Improved Low Noise and High Gain Performance

Microwave performance of single-gate and dual-gate GaAs MESFET's with submicron gate structure is described. Design consideration and device technologies are also discussed. The performance of these GaAs MESFET's exceeds previous performance with regard to lower noise and higher gain up to X band: 2.9-dB noise figure (NF) and 10.0-dB associated gain at 12 GHz for a 0.5-mu m single-gate MESFET, and 3.9-dB NF and 13.2-dB associated gain at the same frequency for a dual-gate MESFET with two 1-mu m gates.     

A temperature model for the GaAs MESFET

This paper describes a new two-dimensional method for study of GaAs Schottky-barrier MESFET's. A modified form of the conduction current is used in which transport properties are described in terms of electron temperature rather than electric field. Nonequilibrium velocity effects such as velocity overshoot are included. Results for the one-dimensional GaAs diode and the two-dimensional GaAs MESFET are presented and compared to other studies that utilize the Monte Carlo procedure. Larger values of current cut-off frequency are predicted for submicrometer gate length MESFET's than in previous two-dimensional simulations which utilize the steady-state transport properties.     

22 nm In0.75Ga0.25As channel-based HEMTs on InP/GaAs substrates for future THz applications

In this work, the performance of L_g=22 nm In_0.75Ga_0.25As channel-based high electron mobility transistor (HEMT) on InP substrate is compared with metamorphic high electron mobility transistor (MHEMT) on GaAs substrate. The devices features heavily doped In_0.6Ga_0.4As source/drain (S/D) regions, Si double δ-doping planar sheets on either side of the In_0.75Ga_0.25As channel layer to enhance the transconductance, and buried Pt metal gate technology for reducing short channel effects. The TCAD simulation results show that the InP HEMT performance is superior to GaAs MHEMT in terms of f_T, f_max and transconductance (g_{m_max}). The 22 nm InP HEMT shows an f_T of 733 GHz and an f_max of 1340 GHz where as in GaAs MHEMT it is 644 GHz and 924 GHz, respectively. InGaAs channel-based HEMTs on InP/GaAs substrates are suitable for future sub-millimeter and millimeter wave applications.     

Microwave performance of ion-implanted InP JFETs

These devices have a planar structure with the channel and gate regions formed by the selective implantation of silicon and beryllium into an Fe-doped semi-insulating InP substrate. The nominal gate length is 2 μm with a channel doping of 10¹⁷ cm^-3 and thickness of 0.2 μm. The measured values of f_T and f_max are 10 and 23 GHz, respectively. Examination of the equivalent circuit parameters and their variation with bias led to the following conclusions: (a) a relatively gradual channel profile results in lower than desired transconductance, but also lower gate-to-channel capacitance; (b) although for the present devices, the gate length and transconductance are the primary performance-limiting parameters, the gate contact resistance also reduces the power gain significantly; (c) the output resistance appears lower than that of an equivalent GaAs MESFET, and requires a larger V_DS to reach its maximum value; and (d) a dipole layer forms and decouples the gate from the drain with a strength that falls between that of previously reported GaAs MESFETs and InP MESFETs