GaAs／AlGaAs多量子阱红外探测器材料研究

本文报道ＧａＡｓ／ＡｌＧａＡｓ多量子阱长波长红外探测器材料的制备及其性能．这种材料由ＧａＡｓ阱和ＡｌＧａＡｓ势垒组成，除内ｎ型掺杂，具有５０个周期．利用分子束外延技术成功地生长出了大面积（２英寸）均匀（厚度△ｔ＿ｍａｘ／≤３％，组分△　ｘ＿ｍａｘ／ｘ≤３．４％，掺杂浓度△ｎｍａｘ／ｎ≤３％，椭圆缺陷≤３００ｃｍ－２）的外延材料．分析了暗电流的成因，通过加厚势垒（Ｌｂ≥３００）、控制掺杂（ｎ≤１×１０￣１８ｃｍ￣３）、精确设计子带结构，将暗电流降低了几个数量级，同时使电子的输运得到了改善．由此得到了高质量的     

GaN基HEMT器件结构设计及其性能仿真北大核心

利用Silvaco TCAD器件模拟软件研究了AlGaN/GaN高电子迁移率晶体管(HEMT)器件势垒层的厚度、沟道宽长比和掺杂浓度对器件的转移特性和跨导曲线的影响。结果表明,器件势垒层厚度的变化可以调节器件的电流开关比和开启电压,实现由耗尽型器件向增强型器件的转变;沟道宽长比的改变可以调节器件的开启电压,并且随着沟道宽长比的增加,栅极电压控制量子阱中二维电子气的能力增强;势垒层适量掺杂提高了输出电流,并且使跨导的峰值增大,但过度掺杂会造成器件不易关断情况出现。     

量子阱太赫兹探测材料设计与生长的研究*

子带跃迁的量子阱结构太赫兹探测器具有响应速度快等特点,有广泛的应用前景,越来越受到研究 人员的关注。以量子力学基本原理,量子阱结构材料光吸收的特性,以及光导型探测器暗电流分析为基础,进行了 量子阱厚度、势垒层Al 含量和量子阱掺杂浓度等参数的AlGaAs/ GaAs 量子阱太赫兹探测材料结构设计,按照优化 后的外延参数进行了材料生长,获得了符合设计要求的探测材料。     

非均匀GaAs/AlGaAs量子阱红外探测器材料表征和器件性能研究

本文利用分子束外延（MBE）技术成功生长了GaAs/AlGaAs非均匀量子阱红外探测器材料,并对相关微结构作了细致表征。分析比较了非均匀量子阱结构和常规量子阱红外探测器性能差异,并对比研究了不同势阱宽度下非均匀量子阱红外探测器的性能变化。通过高分辨透射电子显微镜（HRTEM）结合能谱仪（EDS）对非均匀量子阱红外探测器材料微结构进行了分析,并利用二次离子质谱仪（SIMS）对非均匀势阱掺杂进行了表征。结果表明,该量子阱外延材料晶体质量很好,量子阱结构和掺杂浓度也与设计值符合较好。对于非均匀量子阱红外探测器,通过改变每个阱的掺杂浓度和势垒宽度,可以改变量子阱电场分布,而与传统的均匀量子阱红外探测器相比,其暗电流显著下降（约一个数量级）。在不同阱宽下,非均匀量子阱的跃迁模式发生改变,束缚态到准束缚态跃迁模式下（B-QB）的器件具有较高的黑体响应率以及较低的暗电流。     

赝形δ掺杂AIGaAs／InGaAds／GaAs量子阱的光致发光性质研究

测量了一系列不同隔离层（ｓｐａｃｅｒ）厚度、阱宽和硅δ掺杂浓度的单边掺杂的赝形高电子迁移率晶体管（ｐＨＥＭＴｓ）量子阱的变温和变激发功率光致发光谱,详细研究了（ｅｌ－ｈｈ１）和（ｅ２－ｈｈ１）两人发光峰之间的动态竞争发光机制,并运用有限差分法自治求解薛定谔方程和泊松方程以得出电子限制势、子带能极以及相应的电子包络波函数、子带占据几率和δ掺杂电子转移效率,研究了两个峰的相对积分发光强度随隔离层厚度、阱宽和δ掺杂浓度的变化。     

子阱及非对称势垒对GaN RTD电学特性的影响

利用Silvaco软件对Al0.2Ga0.8N/GaN共振隧穿二极管(RTD)进行仿真,重点研究了InGaN子量子阱结构及相应非对称势垒结构设计对其电流特性的影响。对比分析了子量子阱结构中InGaN的In组分和子阱厚度对RTD微分负阻(NDR)特性的影响,得出了提升器件性能的最佳参数范围。为了克服Al0.2Ga0.8N/GaN RTD势垒低对器件电流峰谷比(PVCR)的影响,在子量子阱结构的基础上引入了非对称势垒结构设计,通过改变收集区侧势垒的高度和厚度,将AlGaN/GaN的Ip和PVCR由基本结构的0.42 A和1.25,提高到了0.583 A和5.01,实现了器件性能的优化,并为今后的器件研制提供了设计思路。     

高性能InGaAs/AlAs共振隧穿二极管的研制与器件模拟分析

在半绝缘的InP衬底上采用分子束外延的方法生长制备了不同势垒厚度的RTD材料样品,室温下测量的最高峰-谷电流比为18.39.通过模拟得到RTD直流特性与势垒厚度、势阱材料及厚度、隔离层厚度以及掺杂浓度间的关系,对结果进行了分析与讨论.     

高性能InGaAs/AlAs共振隧穿二极管的研制与器件模拟分析

在半绝缘的InP衬底上采用分子束外延的方法生长制备了不同势垒厚度的RTD材料样品,室温下测量的最高峰-谷电流比为18.39.通过模拟得到RTD直流特性与势垒厚度、势阱材料及厚度、隔离层厚度以及掺杂浓度间的关系,对结果进行了分析与讨论.     

量子阱间耦合对带结构的影响

用Matlab程序语言数值计算了多量子阱结构的能级,并研究了量子阱间耦合对其带结构的影响。多量子阱模型是在一个一维有限深势阱（阱边势垒高为 V0）中插入等高（Vb）等厚（b）的势垒方式建成,被分割而成的多量子阱厚度为w。通过增加插入壁垒的个数N、改变阱垒厚度比w/b 及势垒高度比V0/Vb,分别近似计算了对应的结构的能级及波函数。计算结果显示,量子阱间耦合受上述参数的强烈影响,改变参数N,w/b 或V0/Vb ,能带和带隙的宽度是可以被调节的。研究说明,量子阱的能带及带隙宽度达到期望值是完全有可能实现的。     

器件模拟对AIGaAs／GaAs RTD的特性分析

使用SILVACO公司的器件模拟软件ATLAS对A1GaAs／GaAs共振隧穿二极管(RTD)进行了器件模拟，得到了不同结构的RTD的I-V特性曲线。对量子阱宽度、掺杂浓度、势垒宽度和高度对RTD的I-V特性的影响进行了详细的分析。     

Hot-carrier injection suppression due to the nitride-oxide LDDspacer structure

The hot-carrier effects in silicon nitride lightly doped drain (LDD) spacer MOSFETs are discussed. It is found that the oxide thickness under the nitride film spacer affects the hot-carrier effects. The thinner the LDD spacer oxide becomes, the larger the initial drain current degradation becomes at the DC stress test and the smaller the stress time dependence becomes. After the DC stress test, reduced drain current recovers at room temperature. These phenomena are due to the large hot-carrier injection into the LDD nitride spacer, because the nitride film barrier height is much less than the silicon oxide barrier height. Therefore, it is necessary to form the LDD spacer oxide, in order to suppress the large hot-carrier injection in the nitride film LDD spacer MOSFET. The drain current shift mechanism in the nitride spacer MOSFETs is discussed, considering the lucky electron model     

A DBRTD with a High PVCR and a Peak Current Density at Room Temperature

AlAs/GaAs/In0.1Ga0.9As/GaAs/AlAs double-barrier resonant tunneling diodes(DBRTDs) grown on a semi-insulated GaAs substrate with molecular beam epitaxy is demonstrated.By sandwiching the In0.1Ga0.9As layer between GaAs layers,potential wells beside the two sides of barrier are deepened,resulting in an increase of the peak-to-valley current ratio (PVCR) and a peak current density.A special shape of collector is designed in order to reduce contact resistance and non-uniformity of the current;as a result the total current density in the device is increased.The use of thin barriers is also helpful for the improvement of the PVCR and the peak current density in DBRTDs.The devices exhibit a maximum PVCR of 13.98 and a peak current density of 89kA/cm2 at room temperature.     

无凹槽AlGaN/GaN肖特基势垒二极管正向电流输运机制

研究了无凹槽AlGaN/GaN肖特基势垒二极管(SBD)的正向电流输运机制。分别采用Ni/Au和TiN作为阳极金属材料制备了无凹槽AlGaN/GaN SBD,对比了两种SBD的直流特性。并通过测量器件的变温I-V特性,研究了器件的正向电流输运机制。结果表明,TiN-SBD(0.95 V@1 mA·mm^-1)与Ni/Au-SBD(1.15 V@1 mA·mm^-1)相比实现了更低的开启电压,从而改善了正向导通特性。研究发现两种SBD的势垒高度和理想因子都强烈依赖于环境温度,通过引入势垒高度的高斯分布模型解释了这种温度依赖性,验证了正向电流输运机制为与势垒高度不均匀分布相关的热电子发射机制。     

室温下高峰谷电流比、高峰电流密度的双势垒共振隧穿二极管

在半绝缘GaAs衬底上制作了AlAs/GaAs/In0.1Ga0.9As/GaAs/AlAs双势垒共振隧穿二极管.在GaAs层中加入In0.1Ga0.9As层用以降低势垒两边的势阱深度,从而提高了器件的峰谷电流比和峰电流密度.为了减小器件的接触电阻和电流的非均匀性,使用了独特形状的集电极,总的电流密度也因此提高.薄栅也有助于提高器件的PVCR和峰电流密度.在室温下测得其峰谷电流比高达13.98,峰电流密度大于89kA/cm2.     

器件模拟对AlGaAs/GaAs RTD的特性分析(英文)

使用SILVACO公司的器件模拟软件ATLAS对AlGaAs/GaAs共振隧穿二极管(RTD)进行了器件模拟,得到了不同结构的RTD的I-V特性曲线。对量子阱宽度、掺杂浓度、势垒宽度和高度对RTD的I-V特性的影响进行了详细的分析。     

Simulation and analysis of metamorphic high electron mobility transistors

In this paper, the metamorphic high electron mobility transistors (mHEMTs) are investigated numerically and compared with pseudo-morphic high electron mobility transistors (pHEMTs). The two-dimensional device simulator, MEDICI, is used to solve the Poisson's equation and the electron/hole current continuity equations. The influences of δ-doping concentration and position, gate width, spacer thickness, etc. on the performances of HEMTs are explored. It shows clearly that mHEMTs have higher transconductances, drain currents and DC voltage swings than pHEMTs.     

Simulation analysis of the DC current gain in an n-p-n a-Si:H/SiGe/Si heterojunction bipolar transistor

This paper presents the results of a simulation study focused on the evaluation of the DC characteristics of an n-p-n SiGe-based heterojunction bipolar transistor (HBT) performing an extremely thin n⁺ hydrogenated amorphous silicon (a-Si:H) emitter. The a-Si:H(n)/SiGe(p) structure exhibits an energy gap difference of approximately 0.8 eV mostly located at the valence band side and this results in an optimal configuration for the emitter/base junction to improve the emitter injection efficiency and thus the device performance.Considering a 20% Ge uniform concentration profile in the base region, simulations indicate that the DC characteristics of an a-Si:H/SiGe HBT are strictly dependent on two essential geometrical parameters, namely the emitter width and the base width. In particular, the emitter thickness degrades device characteristics in terms of current handling capabilities whereas higher current gains are obtained for progressively thinner base regions. A DC current gain exceeding 9000 can be predicted for an optimized device with a thin emitter and a 10 nm-thick, doped base.     

Fabrication,structural and electrical characterization of AlNi2Si based heterojunction grown by LPE

This work elucidates the applicability for Liquid-Phase Epitaxy (LPE) to grow epilayers of AlNi₂Si on single crystalline Si with a good crystalline quality and low series resistance. Surface morphology and crystalline structural characteristics of the heterojunction were characterized by scanning electron microscopy (SEM) and X-ray diffraction (XRD), respectively. Temperature dependence of the current–voltage (I–V) characteristics is studied to elucidate the predominant conduction mechanism in the temperature range 305–370 K. Heterojunction parameters such as ideality factor, series resistance, barrier height show temperature dependence in the desired temperature range. Cheung functions are applied for determination the heterojunction parameters and compared with each other. Temperature dependence of capacitance–voltage (C–V) characteristics was considered. The built-in potential, net carrier concentration, maximum barrier height, maximum barrier field and the width of the depletion region obtained from the C–V measurements were studied as a function of temperature.     

The device characteristics of Ir- and Ti-based Schottky gates AlSb/InAs high electron mobility transistors

In this work, the InAs/AlSb high electron mobility transistors (HEMTs) on GaAs semi-insulating substrate using refractory iridium (Ir) gate technology was proposed. The Ir-gate exhibited a superior metal work function which was beneficial for increasing Schottky barrier height of InAs/AlSb heterostructures to 0.58 eV. Compared to the Ti-gate HEMT, the Ir-gate HEMT shows higher threshold voltage and lower gate leakage current owing to its higher Schottky barrier height and higher melting point. Moreover, the Ir-gated HEMT also shows the manifest stability improvement of DC characteristics under hot carrier stress as the Ti and As diffusion is alleviated.