Simulating the dynamic electrothermal behavior of power electroniccircuits and systems

The simulator solves for the temperature distribution within the semiconductor devices, packages, and heat sinks (thermal network) as well as the currents and voltages within the electrical network. The thermal network is coupled to the electrical network through the electrothermal models for the semiconductor devices. The electrothermal semiconductor device models calculate the electrical characteristics based on the instantaneous value of the device silicon chip surface temperature and calculate the instantaneous power dissipated as heat within the device. The thermal network describes the flow of heat from the chip surface through the package and heat sink and thus determines the evolution of the chip surface temperature used by the semiconductor device models. The thermal component models for the device silicon chip, packages, and heat sinks are developed by discretizing the nonlinear heat diffusion equation and are represented in component form so that the thermal component models for various packages and heat sinks can be readily connected to one another to form the thermal network     

Voltage dependence of self-clamped inductive switching (SCIS)energy capability of IGBTs

Self-clamped inductive switching (SCIS) energy capability is the most important device parameter for insulated gate bipolar transistors (IGBTs) used in automotive ignition applications. We have experimentally characterized the dependence of IGBTs SCIS energy capability on the clamp voltage for an ambient temperature range of -50 to 175°C. It is found that the SCIS energy of an IGBT increases by nearly 70% when the clamp voltage is reduced from 400 to 100 V. Such a significant increase is attributed to the lower maximum junction temperature that is reached in an IGBT with a lower clamp voltage during the SCIS testing. Two-dimensional (2-D) electrothermal device simulations have been performed to analyze such phenomena. The results provide critical information for device design and product development     

Thermal component model for electrothermal analysis of IGBT modulesystems

The insulated gate bipolar transistor (IGBT) modules are getting more accepted and increasingly used in power electronic systems as high power and high voltage switching components. However, IGBT technology with high speed and greater packaging density leads to higher power densities on the chips and increases higher operating temperatures. These operating temperatures in turn lead to an increase of the failure rate and a reduction of the reliability. In this paper, the static and dynamic thermal behavior of IGBT module system mounted on a water-cooled heat sink is analyzed. Although three-dimensional finite element method (3-D FEM) delivers very accurate results, its usage is limited by an imposed computation time in arbitrary load cycles. Therefore, an RC component model (RCCM) is investigated to extract thermal resistances and time constants for a thermal network. The uniqueness of the RCCM is an introduction of the time constants based on the Elmore delay, which represents the propagation delay of the heat flux through the physical geometry of each layer. The dynamic behavior predicted by the thermal network is equivalent to numerical solutions of the 3-D FEM. The RCCM quickly offers insight into the physical layers of the components and provides useful information in a few minutes for the arbitrary or periodic power waveforms. This approach enables a system designer to couple the thermal prediction with a circuit simulator to analyze the electrothermal behavior of IGBT module system, simultaneously     

Transient temperature measurements and modeling of IGBT's undershort circuit

This paper discusses the estimation of possible device destruction inside power converters in order to predict failures by means of simulation. The study of insulated gate bipolar transistor (IGBT) thermal destruction under short circuits is investigated. An easy experimental method is presented to estimate the temperature decay in the device from the saturation current response at low gate-to-source voltage during the cooling phase. A comparison with other classical experimental methods is given. Three one-dimensional thermal models are also studied: the first is a thermal equivalent circuit represented by series of resistance-capacitance cells; the second treats the discretized heat-diffusion equation; and the third is an analytical model developed by building an internal approximation of the heat-diffusion problem. It is shown that the critical temperature of the device just before destruction is larger than the intrinsic temperature, which is the temperature at which the semiconductor becomes intrinsic. The estimated critical temperature is above 1050 K, so it is much higher than the intrinsic temperature (~550 K). The latter value is underestimated when multidimensional phenomena are not taken into account. The study is completed by results showing the threshold voltage and the saturation current degradation when the IGBT is submitted to a stress (repetitive short circuit)     

A study on the short-circuit capability of field-stop IGBTs

The short-circuit failure mechanism of 1200 V trench gate field-stop insulated gate bipolar transistor (IGBT) has been investigated in this paper. Experimental testing shows that most of the devices failed during the blocking state after a few hundred microseconds of the short-circuit turn-off condition. This unusual failure mode was analyzed both with experimental and numerical investigation. It has been determined that due to significantly large leakage current, thermal run-away can occur causing device failure after short circuit turn-off. Due to the smaller heat capacity of the FS-IGBT structure, the device temperature after the turn-off becomes so high that the local heating produced by the high temperature leakage current results in the thermal run-away.     

IGBT dynamics for clamped inductive switching

Clamped inductive switching performance of insulated gate bipolar transistors (IGBTs) have been studied in detail with the aid of extensive measurements and numerical simulations. Internal dynamics of a latch-up free punch-through IGBT during clamped inductive switching is studied using two-dimensional (2-D) mixed device and circuit simulations incorporating the self-heating mechanism. Failure of IGBT during inductive load turn-off is shown to occur due to thermally assisted carrier multiplication at the reverse biased p-base n-drift region junction under the emitter contact     

A study on IGBT junction temperature (Tj) online estimation using gate-emitter voltage (Vge) at turn-off

A novel method is presented for online estimation of the junction temperature (Tj) of semiconductor chips in IGBT modules, based on evaluating the gate-emitter voltage (Vge) during the IGBT switch off process. It is shown that the Miller plateau width (in the Vge waveform) depend linearly on the junction temperature of the IGBT chips. Hence, a method can be proposed for estimating the junction temperature even during converter operation – without the need of additional thermal sensors or complex Rth network models. A measurement circuit was implemented at gate level to measure the involved time duration and its functionality was demonstrated for different types of IGBT modules. A model has been proposed to extract Tj from Vge measurements. Finally, an IGBT module with semiconductor chips at two different temperatures has been measured using Vge method and this method was found to provide the average junction temperature of all the semiconductor chips.     

Noise-margin limitations on gallium-arsenide VLSI

Two factors which limit the complexity of GaAs MESFET VLSI circuits are considered. Power dissipation sets an upper complexity limit for a given logic circuit implementation and thermal design. Uniformity of device characteristics and the circuit configuration determines the electrical functional yield. Projection of VLSI complexity based on these factors indicates that logic chips of 15000 gates are feasible with the most promising static circuits if a maximum power dissipation of 5 W per chip is assumed. While lower power per gate and therefore more gates per chip can be obtained by using a popular E/D FET circuit, yields are shown to be small when practical device parameter tolerances are applied. Further improvements in materials, devices, and circuits will be needed to extend circuit complexity to the range currently dominated by silicon     

一种新型智能功率模块（IPM）

介绍一种新型智能功率模块的功能、工艺及应用。该功率模块将多块IGBT芯片与其栅极驱动电路、短路保护、过流（OC）保护、过温（0T）保护、欠压（UV）锁定电路等集成封装于一体,具有供电简单、开关速度高、死区时间小、驱动效率高的特点。在技术方面,对IGBT芯片、续流二极管芯片（FWD）、控制驱动电路及封装结构等方面采取了多种优化处理措施,从而使其具有很高的性能价格比。     

Electrothermal model for an SOI-based LIGBT

Several vertical insulated gate bipolar transistor (IGBT) electrothermal models are currently available on circuit simulators. However, no reliable electrothermal models have been proposed for the lateral IGBT (LIGBT). In this paper, for the first time, an electrothermal model for an LIGBT structure based on a novel concept recently reported by Udrea (IEDM, p. 451, 2004), and here termed silicon-on-membrane, is presented. The model relies on a systematic study of both the isothermal and self-heating behaviors of the device. The model is further implemented in the SPICE circuit simulator language and validated against extensive Medici numerical simulations and experimental data.     

Cool Chips: Opportunities and Implications for Power and Thermal Management

Alongside innovative device, circuit, and microarchitecture level techniques to alleviate power and thermal problems in nanoscale CMOS-based integrated circuits (ICs), chip cooling could be an effective knob for power and thermal management. This paper analyzes IC cooling while focusing on the practical temperature range of operation. Comprehensive analyses of chip cooling for various nanometer scale bulk-CMOS and silicon-on-insulator (SOI) technologies are presented. Unlike all previous works, this analysis employs a holistic approach (combines device, circuit and system level considerations) and also takes various electrothermal couplings between power dissipation, operating frequency and die temperature into account. While chip cooling always gives performance gain at the device and circuit level, it is shown that system level power defines a temperature limit beyond which cooling gives diminishing returns and an associated cost that may be prohibitive. A scaling analysis of this temperature limit is also presented. Furthermore, it is shown that on-chip thermal gradients cannot be mitigated by global chip cooling and that localized cooling can be more effective in removing hot-spots.     

TLM method for thermal investigation of IGBT modules in PWM mode

The insulated gate bipolar transistor (IGBT) is popularly used in high power, high frequency power-electronic applications such as motor control and inverters. These applications require well designed thermal management system to ensure the protection of IGBTs. Choice simulation tools for accurate prediction of device power dissipation and junction temperature become important in achieving optimised designs.In this paper, thermal analysis of a 1200 A, 3.3 kV IGBT module was investigated and analysed using the three-dimensional transmission line matrix (3D-TLM) method. The results show a three-dimensional visualisation of self-heating phenomena in the device. Since the comparison TLM results with the analytical solutions do not exist for this IGBT module, we use the MSC.NASTRAN tool to find the similar range of the temperatures. Results are compared.Typically, IGBT is used in a three-phase inverter leg where the control signals are generated via PWM scheme so, the prediction of the temperature rise is important in the pulse operation conditions for the IGBT device. A view of the dynamic thermal temperature rise is obtained with 100 W-step pulse dissipation applied at IGBT chips. The temperature rises are calculated using TLM method during the PWM load cycles. Simulations give clear indications of the importance of the spreader material and are helpful in selecting the proper one.TLM has been successful in modelling heat diffusion problems and has proven to be efficient in terms of stability and complex geometry. The three-dimensional results show that method has a considerable potential in power devices thermal analysis and design.     

Characterization of P-channel power trench MOSFETs with polycrystalline silicon germanium gate electrode for faster switching

Electrical switching characteristics using polycrystalline silicon–germanium (poly-Si_l?xGe_x) gate for P-channel power trench MOSFETs was investigated. Switching time reduction of over 22% was observed when the boron-doped poly-Si gate was replaced with a similarly boron-doped poly-SiGe gate on the P-channel power MOSFETs. The fall time (T_f) on MOSFETs with poly-SiGe gate, was found to be ～11 ns lesser than the poly-Si gate MOSFET which is ～60% improvement in switching performance. However, all the switching improvement was observed during the fall times (T_f). The reason could be the higher series resistance in the switching test circuit masking any reduction in the rise times (T_r). Faster switching is achieved due to a lower gate resistance (R_g) offered by the poly-SiGe gate electrode as compared to poly-silicon (pSi) material. The pSi gate resistance was found to be 6.25 Ω compared to 3.75 Ω on the poly-SiGe gate measured on the same device. Lower gate resistance (R_g) also means less power is lost during switching thereby less heat is generated in the device. A very uniform boron doping profile was achieved with-in the pSiGe gate electrode, which is critical for uniform die turn on and better thermal response for the power trench MOSFET. pSiGe thin film optimization, properties and device characteristics are discussed in details in the following sections.     

IGBT关断瞬态电压尖峰影响及抑制

绝缘栅双极晶体管(IGBT)是一种性能优良的全控型电力电子器件,由于线路和器件内部分布电感的存在,关断时集电极电流的快速变化会感应产生一个较大的电压尖峰从而引起过电压击穿。分析了栅极结电容放电时间常数和拖尾电流对电压尖峰的影响,通过改变栅极驱动电阻和温度可以抑制电压尖峰。分析了电压尖峰引起过压击穿的失效机理以及失效模式,表明IGBT过压击穿引起失效的本质仍然是结温过高引起的热击穿失效。     

IGBT的总剂量辐射效应及加固

本文研究一种“反程序”辐射加固工艺，将所有的高温处理过程放在栅氧化之前，并使栅氧化后续工艺低温化，在此基础上，采用“反程序”辐射加固工艺研制出的IGBT加固器件，其抗总剂量辐射性能远远优于采用常规工艺制造出的IGBT器件。对于栅氧化层厚度为70nm的加固器件，在VGS=十10V（直流和脉冲）、VGS=OV等不同栅偏量下，辐射剂量达到IX10~3（Gy（St))时，阈值电压的漂移量小于一1．OV，跨导变化小于10％。采用此工艺，预计抗总剂量辐射能力可达到10~4Gy（Si）以上。     

牵引用3 300 V平面栅IGBT栅极台面结构研究

针对机车牵引用3 300 V/1 500 A IGBT功率模块,采用TCAD仿真工具研究了不同栅极结构对器件静态和动态参数的影响。当平面栅IGBT采用栅极台面结构且台面厚度逐渐降低时,器件的静态阻断电压提高,开关损耗降低,但是器件的开关时间增加;此外,关断时过快的dv/dt会引起栅极电压振荡,开启时过快的di/dt会引起很大的电流过冲,导致器件应用的可靠性降低。在机车牵引的应用环境下,IGBT的栅极结构参数需要从电学参数和可靠性两个方面进行折中设计。     

压力对换流阀用压接型IGBT器件功率损耗的影响

功率损耗一直是功率半导体器件应用时备受关注的问题.压接型绝缘栅双极型晶体管(IGBT)器件靠外部压力使内部各个组件保持电气和机械连接,因此压力直接或间接地影响着压接型IGBT器件的功率损耗.将压接型IGBT器件工作时产生的结温作为耦合变量引入,基于此建立了IGBT器件应用于调制脉宽(PWM)换流设备时的功率损耗计算模型,并详细分析了影响功率损耗的各种因素,包括机械压力、开关频率等.以换流阀用3 300 V/1 500 A压接型IGBT器件为例,采用有限元法研究了压力对压接型IGBT器件功率损耗的影响,重点探讨了器件内部各芯片功率损耗的变化情况.结果表明,增加压力一定程度上可以降低压接型IGBT器件的功率损耗,改善器件内部芯片结温分布不均的问题.     

压接型IGBT器件单芯片子模组功率循环试验仿真

压接型绝缘栅双极型晶体管(IGBT)器件因具有双面散热、短路失效和易于串联等优点,正逐步应用到柔性直流输电等领域.但其在工作过程中的热学、力学特性与传统焊接式IGBT模块相比有很大差异,故存在不同的长期可靠性问题.基于有限元法建立了压接型IGBT器件单芯片子模组多物理场耦合仿真模型,研究了三种功率循环仿真条件下器件的热学和力学特性,并且在功率循环过程中利用金属弹塑性模型来模拟材料的瞬态特性.仿真结果表明,IGBT芯片发射极表面与发射极钼片相接触的边缘是应力集中区域,芯片发射极表面栅极缺口和四周边角处有明显的塑性变形.同时,将仿真结果与实际失效的IGBT芯片进行了对比,进一步验证了仿真模型的有效性和适用性.