Design of reliable universal QCA logic in the presence of cell deposition defect

The emergence of Quantum-dot Cellular Automata (QCA) has resulted in being identified as a promising alternative to the currently prevailing techniques of very large scale integration. QCA can provide low-power nanocircuit with high device density. Keeping aside the profound acceptance of QCA, the challenge that it is facing can be quoted as susceptibility to high error rate. The work produced in this article aims towards the design of a reliable universal logic gate (r-ULG) in QCA (r-ULG along with the single clock zone and r-ULG-II along with multiple clock zones). The design would include hybrid orientation of cells that would realise majority and minority, functions and high fault tolerance simultaneously. The characterisation of the defective behaviour of r-ULGs under different kinds of cell deposition defects is investigated. The outcomes of the investigation provide an indication that the proposed r-ULG provides a fault tolerance of 75% under single clock zone and a fault tolerance of 100% under dual clock zones. The high functional aspects of r-ULGs in the implementation of different logic functions successfully under cell deposition defects are affirmed by the experimental results. The high-level logic around the multiplexer is synthesised, which helps to extend the design capability to the higher-level circuit synthesis.     

Single-Bit Comparator in Quantum-Dot Cellular Automata (QCA) Technology Using Novel QCA-XNOR Gates

To fill the continuous needs for faster processing elements with less power consumption causes large pressure on the complementary metal oxide semiconductor (CMOS) technology developers. The scaling scenario is not an option nowadays and other technologies need to be investigated. The quantum-dot cellular automata (QCA) technology is one of the important emerging nanotechnologies that have attracted much researchers’ attention in recent years. This technology has many interesting features, such as high speed, low power consumption, and small size. These features make it an appropriate alternative to the CMOS technique. This paper suggests three novel structures of XNOR gates in the QCA technology. The presented structures do not follow the conventional approaches to the logic gates design but depend on the inherent capabilities of the new technology. The proposed structures are used as the main building blocks for a single-bit comparator. The resulted circuits are simulated for the verification purpose and then compared with existing counterparts in the literature. The comparison results are encouraging to append the proposed structures to the library of QCA gates.     

Design and evaluation of an ultra-area-efficient fault-tolerant QCA full adder

Quantum-dot cellular automata (QCA) has been studied extensively as a promising switching technology at nanoscale level. Despite several potential advantages of QCA-based designs over conventional CMOS logic, some deposition defects are probable to occur in QCA-based systems which have necessitated fault-tolerant structures. Whereas binary adders are among the most frequently-used components in digital systems, this work targets designing a highly-optimized robust full adder in a QCA framework. Results demonstrate the superiority of the proposed full adder in terms of latency, complexity and area with respect to previous full adder designs. Further, the functionality and the defect tolerance of the proposed full adder in the presence of QCA deposition faults are studied. The functionality and correctness of our design is confirmed using high-level synthesis, which is followed by delineating its normal and faulty behavior using a Probabilistic Transfer Matrix (PTM) method. The related waveforms which verify the robustness of the proposed designs are discussed via generation using the QCADesigner simulation tool.     

QCA电路的缺陷研究

针对量子元胞自动机电路中出现的元胞移位等元胞缺陷,介绍了基于QCADesigner的元胞缺陷分析,得出了特定结构的容错范围。对于制造过程出现的单电子故障,分析了不同输入时单电子故障对传输线和反相器的影响。对于制造过程中出现的漂移电荷缺陷,分析了这些缺陷对传输线的影响。通过改变元胞与传输线之间的距离,研究了QCA传输线之间的串扰问题,得出了其容错范围。最后对RS触发器中出现的元胞缺陷采用测试序列进行了分析研究,从而为进一步研究QCA电路的缺陷提供了依据和方向。     

A new design of QCA‐based nanoscale multiplexer and its usage in communications

Quantum‐dot cellular automata (QCA) is one of the proposed nanotechnologies in the electronics industry, which offers a new construction for scheming digital circuits with less energy consumption on the nanoscale and possibly can be an appropriate replacement of complementary metal‐oxide semiconductor (CMOS) technology. Nanocommunication in QCA has attracted a wide range of researcher's attention. However, there is still a broad scope to design QCA‐based architecture for nanocommunication. The multiplexer is hugely used in the telecommunication system and transmits multiple data at the same time. Therefore, in this paper, a useful structure to implement a 2 to 1 multiplexer based on the novel XOR gate is presented and is used as a module to implement the 4 to 1 and 8 to 1 multiplexers. Simulations using QCADesigner tool are done to check the performance of the suggested designs. The 2 to 1, 4 to 1, and 8 to 1 QCA multiplexer structures utilize 22, 92, and 260 cells and consume 0.03, 0.12, and 0.40 μm² of area, respectively. They have shown that the suggested designs have stable and applicable structures regarding area, cost, and complexity.     

Novel techniques for memristive multifunction logic design

We present novel techniques for realising reliable low overhead logic functions and more complex systems based on the switching characteristics of memristors. Firstly, we show that memristive circuits have inherent properties for realising multiple valued MIN-MAX operations over the post algebra. We then present an efficient hybrid 1T-4M logic architecture for dual XOR/AND and XNOR/OR functionality, which can be seamlessly integrated with the existing CMOS technology. Although memristors are usually considered to operate at lower frequencies, however, recent advances in technology show their potentiality at high frequencies. To this end, we also explore the effects of high frequencies on their performance and thereby propose reliable high frequency design techniques based on our 1T-4M architectures. Experimental results, based on the design of full adders and multipliers over GF, show that the proposed designs require significantly lower power and overhead while maintaining reliable performance at low as well as at high frequencies compared to the existing techniques.     

改进型QCA共面交叉电路的可靠性分析

针对量子元胞自动机(QCA)电路中电路单元复杂化能提高电路可靠性的假设,采用概率转移矩阵对一种改进后的QCA共面交叉电路单元及原始电路单元的可靠性进行对比分析,以检验复杂化设计能否提高电路可靠性,并利用四选一数据选择器进行深入研究以验证分析结果。仿真结果表明,该改进方案将共面交叉电路单元应用于单独运行及组合电路中分别使电路的可靠性降低了19.6%和0.84%。改进后的电路单元不但没有提高可靠性,反而由于电路结构的复杂化降低了其可靠性。     

Single-bit digital comparator circuit design using quantum-dot cellular automata nanotechnology

The large amount of secondary effects in complementary metal–oxide–semiconductor technology limits its application in the ultra-nanoscale region. Circuit designers explore a new technology for the ultra-nanoscale region, which is the quantum-dot cellular automata (QCA). Low-energy dissipation, high speed, and area efficiency are the key features of the QCA technology. This research proposes a novel, low-complexity, QCA-based one-bit digital comparator circuit for the ultra-nanoscale region. The performance of the proposed comparator circuit is presented in detail in this paper and compared with that of existing designs. The proposed QCA structure for the comparator circuit only consists of 19 QCA cells with two clock phases. QCA Designer-E and QCA Pro tools are applied to estimate the total energy dissipation. The proposed comparator saves 24.00% QCA cells, 25.00% cell area, 37.50% layout cost, and 78.11% energy dissipation compared with the best reported similar design.     

Modular Design of testable reversible ALU by QCA multiplexer with increase in programmability

The quantum-dot cellular automata have emerged as one of the potential computational fabrics for the emerging nanocomputing systems due to their ultra-high speed and integration density. On the other hand, reversible computing promises low power consuming circuits by nullifying the energy dissipation during the computation. This work targets the design of a reversible arithmetic logic unit (RALU) in the quantum-dot cellular automata (QCA) framework. The design is based on the reversible multiplexer (RM) synthesized by compact 2:1 QCA multiplexers introduced in this paper. The proposed reversible multiplexer is able to achieve 100% fault tolerance in the presence of single missing or additional cell defects in QCA layout. Furthermore, the advantage of modular design of reversible multiplexer is shown by its application in synthesizing the RALU with separate reversible arithmetic unit (RAU) and reversible logic unit (RLU). The RALU circuit can be tested for classical unidirectional stuck-at faults using the constant variable used in this design. The experimentation establishes that the proposed RALU outperforms the conventional reversible ALU in terms of programming flexibility and testability.     

Efficient design of parity preserving logic in quantum-dot cellular automata targeting enhanced scalability in testing

Design of parity preserving logic based on emerging nanotechnology is very limited due to present technological limitation in tackling its high error rate. In this work, Quantum-dot cellular automata (QCA), a potential alternative to CMOS, is investigated for designing easily testable logic circuit. A novel self-testable logic structure referred to as the testable-QCA (t-QCA), using parity preserving logic, is proposed. Design flexibility of t-QCA then evaluated through synthesis of standard functions. The programmability feature of t-QCA is utilized to implement an ALU, realizing six important functions. Although the parity preservation property of t-QCA enables concurrent detection of permanent as well as the transient faults, an augmented test logic circuit (TC) using QCA primitives has been introduced to cover the cell defects in nanotechnology. Experimental results establish the efficiency of the proposed design that outperforms the existing technologies in terms of design cost and test overhead. The achievement of 100% stuck-at fault coverage and the 100% fault coverage for single missing/additional cell defects in QCA layout of the t-QCA gate, address the reliability issues of QCA nano-circuit design.     

An efficient design of CORDIC in Quantum-dot cellular automata technology

Power dissipation of future-integrated systems, consisting of a numberless of devices, is a challenge that cannot be easily solved by classical technologies. Quantum-dot Cellular Automata (QCA) is a Field-Coupled Nanotechnology (FCN) and a potential alternative to traditional CMOS technologies. It offers various features like extremely low-power dissipation, very high operating frequency and nanoscale feature size. This study presents a novel design of CORDIC circuit based on QCA technology. The proposed circuit is based on several proposed QCA sub-modules as adder and Flip-Flop. To design and verify the proposed architecture, QCADesigner tool is employed and power consumption is estimated using QCAPro software. The proposed QCA CORDIC achieves about 69% reduction in power and area compared to previous existing designs. The outcome of this work can open up a new window of opportunity for the design of the CORDIC module and can be used in low-power signal and image processing systems.     

Adder design using 5-input majority gate in a novel “Multilayer Gate Design Paradigm” for Quantum Dot Cellular Automata Circuits

This paper proposes a novel design paradigm for circuits designed in quantum dot cellular automata (QCA) technology. Previously reported QCA circuits in the literature have generally been designed in a single layer which is the main logical block in which the inverter and majority gate are on the base layer, except for the parts where multilayer wire crossing was used. In this paper the concept of multilayer wire crossing has been extended to design logic gates in multilayers. Using a 5-input majority gate in a multilayer, a 1-bit and 2-bit adder have been designed in the proposed multilayer gate design paradigm. A comparison has been made with some adders reported previously in the literature and it has been shown that circuits designed in the proposed design paradigm are much more efficient in terms of area, the requirement of QCA cells in the design and the input-output delay of the circuit. Over all, the availability of one additional spatial dimension makes the design process much more flexible and there is scope for the customizability of logic gate designs to make the circuit compact.     

An enhanced high-speed multi-digit BCD adder using quantum-dot cellular automata

The advent of development of high-performance, low-power digital circuits is achieved by a suitable emerging nanodevice called quantum-dot cellular automata(QCA). Even though many efficient arithmetic circuits were designed using QCA, there is still a challenge to implement high-speed circuits in an optimized manner. Among these circuits, one of the essential structures is a parallel multi-digit decimal adder unit with significant speed which is very attractive for future environments. To achieve high speed, a new correction logic formulation method is proposed for single and multi-digit BCD adder. The proposed enhanced single-digit BCD adder(ESDBA) is 26% faster than the carry flow adder(CFA)-based BCD adder. The multi-digit operations are also performed using the proposed ESDBA, which is cascaded innovatively. The enhanced multi-digit BCD adder(EMDBA) performs two 4-digit and two 8-digit BCD addition 50% faster than the CFA-based BCD adder with the nominal overhead of the area. The EMDBA performs two 4-digit BCD addition 24% faster with 23% decrease in the area, similarly for 8-digit operation the EMDBA achieves 36% increase in speed with 21% less area compared to the existing carry look ahead(CLA)-based BCD adder design. The proposed multi-digit adder produces significantly less delay of(N-1)+3.5 clock cycles compared to the N*One digit BCD adder delay required by the conventional BCD adder method. It is observed that as per our knowledge this is the first innovative proposal for multi-digit BCD addition using QCA.     

基于交通故障报警系统的组合逻辑电路的设计

用数字信号完成对数字量进行算术运算和逻辑运算的电路称为数字电路,可以分为组合逻辑电路和时序逻辑电路两大类.其中,组合逻辑电路是由最基本的逻辑门电路组合而成.文章以交通故障报警系统为例介绍了三种设计方案,以便学生熟悉常见组合逻辑电路的特点及应用.     

Analytical method for cell displacement defect quantum-dot cellular automata primitive

Quantum-dot cellular automata (QCA) is an emerging computational paradigm which can overcome scaling limitations of the existing complementary metal oxide semiconductor (CMOS) technology. The existence of defects cannot be ignored, considering the fabrication of QCA devices at the molecular level where it could alter the functionality. Therefore, defects in QCA devices need to be analyzed. So far, the simulation-based displacement defect analysis has been presented in the literature, which results in an increased demand in the corresponding mathematical model. In this paper, the displacement defect analysis of the QCA main primitive, majority voter (MV), is presented and carried out both in simulation and mathematics, where the kink energy based mathematical model is applied. The results demonstrate that this model is valid for the displacement defect in QCA MV.     

QMOS digital logic circuit design

This paper presents results of work to explore the feasibility of using resonant tunnelling diodes (RTDs) and conventional MOSFETs for the development of digital logic circuits. Based on the use of RTDs and MOSFETs, two different logic design styles—fixed pull-down and fixed pull-up—are proposed and evaluated. Fixed pull-up gates perform better than their CMOS counterparts with similar device sizes. Since the proposed fixed pull-down style avoids the use of series MOSFETs, for large fan-in gates it yields significantly better performance than the corresponding CMOS gates.     

数字系统设计研究中的进化硬件电路及应用前景

以美国Genobyte公司的CBM为例，介绍了目前数字系统设计研究的热点，即进化硬件电路的应用研究价值、理论基础及实现的载体，并讨论了进化硬件电路有待发展的技术条件。     

基于MZI结构和级联SOA的宽相位容限全光异或门

传统使用半导体光放大器(SOA)中交叉相位调制( XPM)效应构成全光逻辑异或(XOR)门的方案,由 于受到单个SOA中XPM效应自身原理的限制,需要精确的相位控制。本文提出了一种基于马赫 -增德尔干 涉仪(MZI)和级联SOA中XPM效应实现全光逻辑异或门的新方案。本文方案使用对称的MZI结构 ,在两臂 上分别放置两个级联的SOA,通过对时钟光的相位调制,达到对两级输入信号光进行XOR运算 的目的。在 40Gbit/s下的仿真结果表明,本方案易于调节,只需要两束输入信 号光以相反比例分光,即可对其进行异或 逻辑运算,在放宽了分光比取值范围的同时,也降低了对XPM效应中相位控制的要求,实现 了宽相位容 限的全光逻辑XOR门。研究了时钟光功率和输入信号分光比对逻辑运算结果的影响,发 现输入信号分 光比的不同步变化对输出信号质量的影响较为明显。对提高方案速率的方法进行了讨 论。     

A CNFET-based hybrid multi-threshold 1-bit full adder design for energy efficient low power applications

In this article, a low-power and energy-efficient hybrid full adder circuit is proposed, which is implemented based on multi-threshold NAND and NOR gates and transmission gate multiplexers. In order to implement this circuit, carbon nano tube field effect transistors are utilised. For evaluating the proposed design, comprehensive simulations are performed with regard to the most important aspects power, delay and power-delay product. The results are presented and displayed the superiority of the proposed cell in different voltage levels, load conditions, temperatures and robustness against process variations.     

高效剩余数至二进制转换器设计

针对目前剩余数系统所处理数据动态范围较小。而且剩余数至二进制转换器的面积和延迟较大等方面的问题,基于新中国余数定理II提出了一个高效并行转换算法,同时给出相应的电路实现。该算法采用模集合（2^n-1,2^n＋1,2^2n,2^2n＋1,可同时处理4个模,处理数的动态范围达到6n＋l位。乘法逆元简单,电路完全由基本的加法器构成,硬件实现容易。分析实验结果表明,相比同类模集合反向转换器,文中提出的转换器的面积节省了39．4％,速度提高了47．4％。