A 16-Mb MRAM featuring bootstrapped write drivers

A 16-Mb magnetic random access memory (MRAM) is demonstrated in 0.18-/spl mu/m three-Cu-level CMOS with a three-level MRAM process adder. The chip, the highest density MRAM reported to date, utilizes a 1.42/spl mu/m/sup 2/ 1-transistor 1-magnetic tunnel junction (1T1MTJ) cell, measures 79 mm/sup 2/ and features a /spl times/16 asynchronous SRAM-like interface. The paper describes the cell, architecture, and circuit techniques unique to multi-Mb MRAM design, including a novel bootstrapped write driver circuit. Hardware results are presented.     

Magnetoresistive random access memory using magnetic tunnel junctions

Magnetoresistive random access memory (MRAM) technology combines a spintronic device with standard silicon-based microelectronics to obtain a combination of attributes not found in any other memory technology. Key attributes of MRAM technology are nonvolatility and unlimited read and write endurance. Magnetic tunnel junction (MTJ) devices have several advantages over other magnetoresistive devices for use in MRAM cells, such as a large signal for the read operation and a resistance that can be tailored to the circuit. Due to these attributes, MTJ MRAM can operate at high speed and is expected to have competitive densities when commercialized. In this paper, we review our recent progress in the development of MTJ-MRAM technology. We describe how the memory operates, including significant aspects of reading, writing, and integration of the magnetic material with CMOS, which enabled our recent demonstration of a 1-Mbit memory chip. Important memory attributes are compared between MRAM and other memory technologies.     

A 0.24-/spl mu/m 2.0-V 1T1MTJ 16-kb nonvolatile magnetoresistance RAM with self-reference sensing scheme

A nonvolatile 16-kb one-transistor one-magnetic-tunnel-junction (1T1MTJ) magnetoresistance random access memory with 0.24-/spl mu/m design rules was developed by using a self-reference sensing scheme for reliable sensing margin. This self-reference sensing scheme was achieved by first storing a voltage of the magnetic tunnel junction (MTJ), and then after a time interval storing a reference voltage of the same MTJ (self-reference). The effects of variation in tunneling oxide thickness can be eliminated by this self-reference sensing scheme. As a result, reliable sensing of MRAM devices with MTJ resistance of 2.5-11 k/spl Omega/ was achieved.     

MRAM Cell Technology for Over 500-MHz SoC

This paper describes newly developed magnetic random access memory (MRAM) cell technology suitable for high-speed memory macros embedded in next-generation system LSIs: a two-transistor one-magnetic tunneling junction (2T1MTJ) cell structure, a write-line-inserted MTJ, and a 5T2MTJ cell structure. The 2T1MTJ cell structure makes it possible to significantly improve the write margin and accelerate the operating speed to 200 MHz. Its high compatibility with SRAM specifications and its wide write margin were confirmed by measuring 2T1MTJ MRAM test chips. Although the cell structure requires a small-writing-current MTJ, the current can be reduced to 1mA using the newly developed write-line-inserted MTJ. Further development to reduce the current down to 0.5 mA is required to obtain a cell area of 1.9 mum², which is smaller than the SRAM cell area, in the 0.13-mum CMOS process. The 5T2MTJ cell structure also enables random-access operation over 500 MHz because the sensing signal is amplified in each cell. Random access time of less than 2 ns can be achieved with SPICE simulation when the magnetic resistance is 5 kOmega and the magnetoresistive (MR) ratio is more than 70%     

A high-speed 128-kb MRAM core for future universal memory applications

A 128-kb magnetic random access memory (MRAM) test chip has been fabricated utilizing, for the first time, a 0.18-/spl mu/m V/sub DD/=1.8 V logic process technology with Cu metallization. The presented design uses a 1.4-/spl mu/m/sup 2/ one-transistor/one-magnetic tunnel junction (1T1MTJ) cell and features a symmetrical high-speed sensing architecture using complementary reference cells and configurable load devices. Extrapolations from test chip measurements and circuit assessments predict a 5-ns random array read access time and random write operations with <5-ns write pulse width.     

Write Disturbance Modeling and Testing for MRAM

The magnetic random access memory (MRAM) is considered one of the potential candidates that will replace current on-chip memories (RAM, EEPROM, and flash memory) in the future. The MRAM is fast and does not need a high supply voltage for read/write operations, and is compatible with the CMOS technology. It can also endure almost unlimited read/write cycles. These combined advantages of RAM and flash memory make it a potential choice for SOC. In this paper, we present the write disturbance fault (WDF) model for MRAM, i.e., a fault that affects the data stored in the MRAM cells due to excessive magnetic field during the write operation. We also construct the SPICE macro model for the magnetic tunneling junction (MTJ) device of the toggle MRAM to obtain circuit simulation results. We then present an MRAM fault simulator called RAMSES-M, based on which we derive the shortest test for the proposed WDF model. The test is shown to be better and more robust as compared with the conventional March C-test algorithm. We also present a March 17 N diagnosis algorithm for identifying WDF. A 1 Mb MRAM chip has been designed and fabricated using a CMOS-based 0.18-mum technology. The proposed WDF model is justified by chip measurement results, with the march test results reported. Finally, specific MRAM fault behavior and test issues are discussed.     

A 16-Mb Toggle MRAM With Burst Modes

This paper describes a recently developed 16-Mb toggle magnetic random access memory (MRAM). It has 100-MHz burst modes that are compatible with a pseudo-SRAM even though the toggle cell requires reading and comparing sequences in write modes. To accelerate operating clock frequency, we propose a distributed-driver wide-swing current-mirror scheme, an interleaved and pipelined memory-array group activation scheme, and a noise-insulation switch scheme. These circuit schemes compensate the toggle cell timing overhead in write modes and maintain write-current precision that is essential for the wide operational margin of MRAMs. Because toggle cells are very resistant to write disturbance errors, we designed the 16-Mb MRAM to include a toggle MRAM cell. The MRAM was fabricated with 0.13-mum CMOS and 0.24-mum MRAM processes with five metal layers.     

MRAM空间粒子辐射效应关键技术研究

磁性随机存储器(MRAM)以其天然的抗辐射特性逐渐成为宇航电子系统的核心元器件之一.围绕MRAM空间粒子辐射效应关键技术,对MRAM辐射效应的研究背景、物理机制、研究方法等内容进行了论述.目前对MRAM的辐射效应研究主要集中在对商用MRAM芯片的辐射性能进行辐射实验评价,评价内容主要包括质子、中子、γ射线等空间粒子对芯...     

Study of total ionizing dose induced read bit errors in magneto-resistive random access memory

This paper presents the Co-60 irradiation results for a 16 Mb Magneto-resistive Random Access Memory (MRAM). Read bit errors were observed during Total Ionizing Dose (TID) testing. We have investigated their physical mechanisms and proposed a resistance drift model of the access transistor in 1M1T (a magnetic tunnel junction and a transistor) storage structure to understand the phenomenon. Read operations have been simulated by HSPICE simulator with the magnetic tunnel junction (MTJ) compact model. The simulation results reveal that the resistance shift of access transistors has a great impact on read bit errors in MRAM. The experimental data and analysis in this work can be used to harden MRAM designs targeting space-borne applications.     

Application and Improvement of Precise Resistance Tracing Technique for a Toggle Mode MRAM Evaluation

A precise evaluation technique was created for developing magnetoresistive random access memory (MRAM), especially memory that operates in a toggle-writing mode. This technique enables us to observe the detailed resistance transition of magnetic tunneling junction (MTJ) cells during complicated write operations. It was used to analyze incomplete operation and failed cells, and revealed that the MTJ characteristics in the third quadrant are significantly related to disturb robustness in megabit MRAM. To improve sensitivity to failed cells, we prepared 16-kbit MRAM test structures with a high-speed failed-cell check mode. We found our technique to be a powerful method of failure analysis and expect it to accelerate MRAM development.      

A 180 Kbit Embeddable MRAM Memory Module

A 180 Kbit magnetoresistive random access memory (MRAM) organized as 22 bits by 8 Kwords has been developed for embedding in a 0.28 micron CMOS process. The memory cell is based on a 1-transistor 1-magnetic tunnel junction (1T1MTJ) bit cell with a toggle MTJ. For reads, the memory is architected with word lines connecting a row of bits to bit lines with a pass transistor and two stages of columns selection transistors connecting bit lines to dual sense amplifiers. For writes, a read is first performed to determine the state of bits to be written followed by a toggle decision to enable bit line toggle drivers. Overlapping bit and word line currents toggle the selected bits. The new dual sense amplifier architecture separates the amplifier reference bits from the bias bits thereby improving sensitivity and reducing offset. The write driver uses a switched capacitor and charge sharing to improve ground bounce immunity and reduce area. Embedded test registers control internal memory timing, reference voltages, reference currents and access features enabling detailed characterization of the memory and optimization of the design. An example describing optimization of the write parameters is presented.      

Single event double node upset tolerance in MOS/spintronic sequential and combinational logic circuits

Spin-transfer torque random access memory (STT-RAM) is an emerging storage technology that is considered widely thanks to its attractive features such as low power consumption, nonvolatility, scalability and high density. STT-RAMs are comprised of a hybrid design of CMOS and spintronic units. Magnetic tunnel junction (MTJ) as the basic element of such hybrid technology is inherently robust against radiation induced faults. However, the peripheral CMOS component for sensing the resistance of the MTJs are prone to be affected by energetic particles. This paper proposes low power, nonvolatile and radiation hardened latch and lookup table circuits based on hybrid CMOS/MTJ technology for the next generation integrated circuit devices. Simulation results revealed that, the proposed circuits are fully robust against single event upsets (SEU) and also single event double node upsets (SEDU) that are of the main reliability challenging issues in current sub-nanometer CMOS technologies.     

Magnetically engineered spintronic sensors and memory

The discovery of enhanced magnetoresistance and oscillatory interlayer exchange coupling in transition metal multilayers just over a decade ago has enabled the development of new classes of magnetically engineered magnetic thin-film materials suitable for advanced magnetic sensors and magnetic random access memories. Magnetic sensors based on spin-valve giant magnetoresistive (GMR) sandwiches with artificial antiferromagnetic reference layers have resulted in enormous increases in the storage capacity of magnetic hard disk drives. The unique properties of magnetic tunnel junction (MTJ) devices has led to the development of an advanced high performance nonvolatile magnet random access memory with density approaching that of dynamic random-access memory (RAM) and read-write speeds comparable to static RAM. Both GMR and MTJ devices are examples of spintronic materials in which the flow of spin-polarized electrons is manipulated by controlling, via magnetic fields, the orientation of magnetic moments in inhomogeneous magnetic thin film systems. More complex devices, including three-terminal hot electron magnetic tunnel transistors, suggest that there are many other applications of spintronic materials.     

A 1-Mbit BiCMOS DRAM using temperature-compensation circuittechniques

A temperature-compensation circuit technique for a dynamic random-access memory (DRAM) with an on-chip voltage limiter is evaluated using a 1-Mb BiCMOS DRAM. It was found that a BiCMOS bandgap reference generator scheme yields an internal voltage immune from temperature and V_cc variation. Also, bipolar-transistor-oriented memory circuits, such as a static BiCMOS word driver, improve delay time at high temperatures. Furthermore, the BiCMOS driver proves to have better temperature characteristics than the CMOS driver. Finally, a 1-Mb BiCMOS DRAM using the proposed technique was found to have better temperature characteristics than the 1-Mb CMOS DRAM which uses similar techniques, as was expected. Thus, BiCMOS DRAMs have improved access time at high temperatures compared with CMOS DRAMs     

Compact model of magnetic tunnel junction with stochastic spin transfer torque switching for reliability analyses

Spin transfer torque magnetic tunnel junction (STT MTJ) is considered as a promising candidate for non-volatile memories thanks to its low power, high speed and easy integration with CMOS process. However, it has been demonstrated intrinsically stochastic. This phenomenon leads to the frequent occurrence of switching errors, which results in considerable reliability issues of hybrid CMOS/MTJ circuits. This paper proposes a compact model of MTJ with STT stochastic behavior, in which technical variations and temperature evaluation are properly integrated. Moreover, the phenomenon of dielectric breakdown of MgO barrier which determines the lifetime of MTJ is also taken into consideration. Its accurate performances allow a more realistic reliability analysis involving the influences of ambient environment and technical process.     

Spin-transfer torque RAM technology: Review and prospect

Non-volatile RAM (NV-RAM) enables instant-on/off computing, which drastically reduces power consumption. One of the most promising candidates for NV-RAM technology is the spin-transfer torque RAM (SPRAM) based on magnetic tunnel junction (MTJ) device technology. This paper reviews the development of MTJ device technology and formulates considerations regarding its memory application, including SPRAM memory cell structure and operation, write voltage limitation, and thermal stability. At the circuit level, a disruptive read operation for future large integration scale is described. A 4F² memory cell and a multi-bit cell approach are also presented. Finally, the potential value of instant-on/off computing through NV-RAM and its impact are explored.     

Noise-shaping sense amplifier for MRAM cross-point arrays

A sensing technique using a voltage-mode architecture, noise-shaping modulator, and digital filter (a counter) is presented for use with cross-point MRAM arrays and magnetic tunnel junction memory cells. The presented technique eliminates the need for precision components, the use of calibrations, and reduces the effects of power supply noise. To obviate the effects of cell-to-cell variations in the array, a digital self-referencing scheme using the counter is presented. Measured experimental results in a 180-nm CMOS process indicate an RMS sensing noise of 20 /spl mu/V for a 5-/spl mu/s sense time. Further increases in sense time are shown to increase the signal-to-noise ratio. The current used by the sense amplifier and counter was measured as 10 /spl mu/A when running at 100 MHz or 10 mA when 1000 sense amplifiers are used with a memory subarray having 1000 bitlines.     

A 60-ns 16-Mbit CMOS DRAM with a transposed data-line structure

Low-noise, high-speed circuit techniques for high-density DRAMs (dynamic random-access memories), as well as their application to a single 5-V 16-Mb CMOS DRAM with a 3.3-V internal operating voltage for a memory array, are described. It was found that data-line interference noise becomes unacceptably high (more than 25% of the signal) and causes a serious problem in 16-Mb DRAM memory arrays. A transposed data-line structure is proposed to eliminate the noise. Noise suppression below 5% is confirmed using this transposed data-line structure. A current sense amplifier is also proposed to maintain the data-transmission speed in common I/O lines, in spite of a reduced operating voltage and increased parasitic capacitance loading in the memory array. A speed improvement of 10 ns is achieved. Using these circuit techniques, a 16-Mb CMOS DRAM with a typical RAS access time of 60 ns was realized     

Magnetoresistive Memory with Ultralow Critical Current for Magnetization Switching

The data writing and thermal stability of information storage are studied theoretically for a magnetic random access memory (MRAM) composed of a magnetic tunnel junction or multilayer exhibiting giant magnetoresistance. The theoretical analysis focuses on the magnetization switching in the “free” layer of a MRAM cell, which is induced by a spin‐polarized current imposing a spin‐transfer torque (STT) on the magnetization. It is shown that the writing current in such an STT‐MRAM reduces dramatically near a spin reorientation transition (SRT) driven by lattice strains and/or surface magnetic anisotropy and even tends to zero under certain conditions. In particular, at the size‐driven SRT in the perpendicular‐anisotropy CoFeB‐MgO tunnel junctions, the critical current densities for magnetization reorientations between the parallel and antiparallel states are expected to fall to low values of about 1.3 × 10⁵ and ?3.3 × 10⁴ A cm^?2. Remarkably, STT‐MRAMs may combine low writing current with very high thermal stability of information storage (retention over 10 years) even at a high density ≈500 Gbit inch^?2.     

An 18-ns 1-Mbit CMOS SRAM

A 1-Mb (256 K×4 b) CMOS static random-access memory with a high-resistivity load cell was developed with 0.7-μm CMOS process technology. This SRAM achieved a high-speed access of 18 ns. The SRAM uses a three-phase back-bias generator, a bus level-equalizing circuit and a four-stage sense amplifier. A small 4.8×8.5-μm² cell was realized by the use of a triple-polysilicon structure. The grounded second-polysilicon layer increases cell capacitance and suppresses α-particle-induced soft errors. The chip size measures 7.5×12 mm²