基于FPGA的软硬件协同测试的设计与实现

在软硬件的开发阶段中,测试结果直接关系到这个软硬件能否顺利进行调试应用。其中,硬件的测试往往容易受外界因素的影响,如环境、计算机设备等,可以通过一些仿真软件来避免外界环境的影响,但是其测试速度比较慢,不利于硬件的开发进度。面对这一难题,文章从FPGA的软硬件协同测试角度出发,利用PC机和测试硬件设备的特点,进行FPGA的软硬件协同测试的设计,努力实现FPGA的软硬件协调测试系统在软硬件的测试和分析中的应用。     

采用软硬件协同设计的SoftMax函数的FPGA实现

人工神经网络中,需要对大量数据进行非线性函数计算。低功耗实现和非线性函数的加速运算成为急需解决的需求。论文基于ZYNQ硬件平台和ARM处理器,进行了软硬件协同设计和FPGA硬件加速器IP的设计,实现了非线性激活函数SoftMax,功耗和误差分布达到设计预期。     

基于FPGA的USB圭控芯片软硬件协同设计与验证

设计了一款采用PowerPC架构的USB1．1主机控制器芯片,并对该芯片进行软硬件协同验证。通过内嵌PowerPC和USB主机IP核的FPGA系统,辅以外部收发器电路、驱动、应用程序和文件系统,完成了对U-Disk和HID两类典型USB应用的测试,验证结果表明该USB主机芯片设计可以符合USB技术规范,并能和其他厂家的设备兼容。     

基于Altera FPGA的软硬件协同仿真

简要介绍了软硬件协同仿真技术,指出了在大规模FPGA开发中软硬件协同仿真的重要性和必要性,给出基于A1tera FPGA的门级软硬件协同仿真实例。     

一种基于SystemC的软硬件协同设计方法

随着集成电路工艺的飞速发展,传统的设计方法已不能满足设计高集成度的复杂数字系统的要求。软硬件协同设计成为嵌入式系统设计的新方法。SystemC是一种兼容C++的系统建模语言,它同时支持RTL级、行为级和系统级描述,使其成为软硬件协同设计平台的基础。     

基于FPGA的软硬件协同仿真加速技术

在系统设计中,硬件复杂电路设计的调试与仿真工作对于设计者来说十分困难。为了降低仿真复杂度,加快仿真速度,本文提出利用FPGA加速的思想,实现软硬件协同加速仿真。经过实验,相对于纯软件仿真,利用软硬件协同加速仿真技术,仿真速度提高近30倍,大大缩短了仿真时间。     

基于SoC设计的软硬件协同验证方法学

文章介绍了软硬件协同验证方法学及其验证流程。在软件方面，采用了一套完整的软件编译调试仿真工具链，它包括处理器的仿真虚拟原型和基本的汇编、链接、调试器；在硬件方面，对软件调试好的应用程序进行RTL仿真、综合，并最终在SoC设计的硬件映像加速器（FPGA）上实现并验证。     

基于遗传算法的软硬件协同设计探索

软硬件协同设计的目标结构包括一个CPU和多个ASIC,它们通过一条总线进行通信.本文介绍一种用于多目标、多模式系统综合的协同设计的新方法.各个工作模式具有不同的运行概率.在满足设计约束的条件下,我们应用遗传算法对系统的速度和功耗两个目标进行优化.遗传算法是全局算法,它能避免陷入局部最小.     

基于SOC的USB主设备的软硬件协同验证

本文首先介绍了SOC软硬件协同验证方法及其平台SeamlessCVE的工作原理和流程,进而在此基础上搭建一个高效的USBA-device验证平台,以实现USB高速A-device软硬件的并行设计,并详细介绍了USBA-device的工作原理和验证流程。     

基于JTAG的SoC软硬件协同验证平台设计

基于JTAG接口,提出了一种以FPGA为基础的SoC软硬件协同验证平台.在验证平台的硬件基础上,开发了调试验证软件,能够完成SRAM的读写、CF卡的读写、串口的收发、程序的下载、及程序复位等功能.利用验证平台的软硬件完成了SoC的IP模块的调试验证及操作系统μClinux的调试验证.实践表明,该验证平台有益于SoC的设计和调试,降低SoC应用系统的开发成本.     

USB2．0主控器软硬件协同仿真系统设计

为了能够充分、快速验证USB2．0主控器的功能,设计了一个软硬件协同仿真平台。其中,CPU模型部分采用一种高效的SystemC模型,而不使用基于指令集的复杂CPU模型。测试用例采用抽象层次更高的C语言编写,通过调用仿真平台对外提供的API完成激励生成与响应检查。结果表明,该方式能够有效降低对仿真资源的占用,减少仿真时间;同时使软件人员能在IP的硬件验证阶段就能完成软件的设计测试工作,缩短软硬件接口整合时间,加快开发进度。     

复杂SOC的软硬件协同验证解决方案

为了提高产品的验证覆盖率和产品的首次成功率,验证工程师越来越多的使用固件、硬件诊断程序和其它软件部分作为实际嵌入式处理器的SoC验证的激励,以保证RTL设计与最终设计实现的的应用环境相同,并覆盖更为复杂的场景,但该RTL验证环境对软件调试的可视性比较有限。Mentor公司的Questa Codelink提供了独特的软硬件协同验证的技术可以让验证人员同时看到软件的执行情况和与软件同步的硬件波形,其回放模式减少了仿真等待的时间,可以快速追踪并定位到程序出错的地方。Codelink也提供了多核调试的技术,可同时看到软件在不同处理器的执行情况,极大地提高了多核验证的效率。     

基于软硬协同设计的HE-AAC V1解码器设计

介绍了一种基于软硬协同设计方法的HE-AAC解码器设计,重点阐述了软硬件协同机制设计,AQMF和SQMF硬件模块设计.在仿真环境下,45 MHz左右可以实时解44.1 kHz采样率、码率为48 Kb/s的双声道歌曲.     

A HW/SW Partitioner for Multi-Mode Multi-Task Embedded Applications

An embedded system is called a multi-mode embedded system if it performs multiple applications by dynamically reconfiguring the system functionality. Further, the embedded system is called a multi-mode multi-task embedded system if it additionally supports multiple tasks to be executed in a mode. In this paper, we address an important HW/SW partitioning problem, that is, HW/SW partitioning of multi-mode multi-task embedded applications with timing constraints of tasks. The objective of the optimization problem is to find a minimal total system cost of allocation/mapping of processing resources to functional modules in tasks together with a schedule that satisfies the timing constraints. The key success of solving the problem is closely related to the degree of the amount of utilization of the potential parallelism among the executions of modules. However, due to an inherently excessively large search space of the parallelism, and to make the task of schedulability analysis easy, the prior HW/SW partitioning methods have not been able to fully exploit the potential parallel execution of modules. To overcome the limitation, we propose a set of comprehensive HW/SW partitioning techniques which solve the three subproblems of the partitioning problem simultaneously: (1) allocation of processing resources, (2) mapping the processing resources to the modules in tasks, and (3) determining an execution schedule of modules. Specifically, based on a precise measurement on the parallel execution and schedulability of modules, we develop a stepwise refinement partitioning technique for single-mode multi-task applications, which aims to solve the subproblems 1, 2 and 3 effectively in an integrated fashion. The proposed techniques is then extended to solve the HW/SW partitioning problem of multi-mode multi-task applications (i.e., to find a globally optimized allocation/mapping of processing resources with feasible execution schedule of modules). From experiments with a set of real-life applications, it is shown that the proposed techniques are able to reduce the implementation cost by 19.0 and 17.0% for single- and multi-mode multi-task applications over that by the conventional method, respectively.     

An FPGA implementation of HW/SW codesign architecture for H.263 video coding

In this paper, we present an efficient HW/SW codesign architecture for H.263 video encoder and its FPGA implementation. Each module of the encoder is investigated to find which approach between HW and SW is better to achieve real-time processing speed as well as flexibility. The hardware portions include the Discrete Cosine Transform (DCT), inverse DCT (IDCT), quantization (Q) and inverse quantization (IQ). Remaining parts were realized in software executed by the NIOS II softcore processor. This paper also introduces efficient design methods for HW and SW modules. In hardware, an efficient architecture for the 2-D DCT/IDCT is suggested to reduce the chip size. A NIOS II Custom instruction logic is used to implement Q/IQ. Software optimization technique is also explored by using the fast block-matching algorithm for motion estimation (ME). The whole design is described in VHDL language, verified in simulations and implemented in Stratix II EP2S60 FPGA. Finally, the encoder has been tested on the Altera NIOS II development board and can work up to 120 MHz. Implementation results show that when HW/SW codesign is used, a 15.8-16.5 times improvement in coding speed is obtained compared to the software based solution.     

SOC软硬件协同仿效系统的通讯协议设计

通过对EDA软件仿真器与硬件加速平台的数据传输和信息交换方式的研究,提出并实现了SOC软硬件协同仿效系统的通讯协议。该协议实现了逻辑通道复用技术及端口号寻址的数据传输功能。对基于该协议的SOC软硬件协同仿效系统进行测试试验,结果表明,该协议实现了EDA软件仿真器与硬件加速平台之间数据实时、准确的交换,达到了EDA软件仿真器与硬件加速平台协同仿效的目的。     

软件导引的模拟退火算法在硬软件划分中的应用

对系统级设计中的硬软件分割问题建立数学模型．将系统级设计工具提供的性能分析功能与模拟退火算法相结合，设计了一种软件导引的模拟退火算法。该实现中将嵌入式系统性能指标（任务的执行时间）作为约束，将实现代价以及功耗作为硬软件分割方法优化的目标。在保证系统的设计目标（任务执行时间）满足要求的基础上。通过选择系统中各模块实现代价和功耗较小的实现方法．进而优化整个系统的实现代价和功耗．彻底改变了以往航天应用的嵌入式系统设计中依赖人工经验进行硬软件划分下现状。     

全定制软/硬件协同设计中的硬件优化技术

提出了基于单相似系统生成的软/硬件协同设计中的硬件优化技术.介绍了一种基于子图匹配软/硬件协同设计技术的大致框架,引进通用子图群合并算法,并着重讨论了基于节点压缩优化技术的高效子图群合并算法.实验结果很好地证明了所有上述理论的正确性以及算法的有效性.     

Optimized RTL Code Generation from Coarse-Grain Dataflow Specification for Fast HW/SW Cosynthesis

This paper presents a new methodology of automatic RTL code generation from coarse-grain dataflow specification for fast HW/SW cosynthesis. A node in a coarse-grain dataflow specification represents a functional block such as FIR and DCT and an arc may deliver multiple data samples per block invocation, which complicates the problem and distinguishes it from behavioral synthesis problem. Given optimized HW library blocks for dataflow nodes, we aim to generate the RTL codes for the entire hardware system including glue logics such as buffer and MUX, and the central controller. In the proposed design methodology, a dataflow graph can be mapped to various hardware structures by changing the resource allocation and schedule information. It simplifies the management of the area/performance tradeoff in hardware design and widens the design space of hardware implementation of a dataflow graph. We also support Fractional Rate Dataflow (FRDF) specification for more efficient hardware implementation. To overcome the additional hardware area overhead in the synthesized architecture, we propose two techniques reducing buffer overhead. Through experiments with some real examples, the usefulness of the proposed technique is demonstrated.

全定制软/硬件协同设计中的硬件优化技术

提出了基于单相似系统生成的软/硬件协同设计中的硬件优化技术.介绍了一种基于子图匹配软/硬件协同设计技术的大致框架,引进通用子图群合并算法,并着重讨论了基于节点压缩优化技术的高效子图群合并算法.实验结果很好地证明了所有上述理论的正确性以及算法的有效性.