Microelectromechanical resonator manufactured using CMOS-MEMS technique

The fabrication of a microelectromechanical resonator using the commercial 0.35 μm complementary metal oxide semiconductor (CMOS) process and a post-process has been implemented. The resonator requires only one wet etching post-process. The suspended structures in the resonator consist of a membrane and four beams. The post-process utilizes an etchant to etch the sacrificial layer, and to release the suspended structures. Easy execution and low cost are the advantages of the post-process. The resonator comprises a driving part and a sensing part. The sensing part produces a change in capacitance when applying a driving voltage to the driving part in the resonator. A circuitry is used to convert the capacitance variation of the sensing part into the voltage output. Experimental results show that the resonant frequency of the resonator is about 39.5 MHz and the quality factor is 806.     

Modeling and fabrication of a microelectromechanical microwave switch

A microelectromechanical microwave switch manufactured by using a complementary metal oxide semiconductor (CMOS) post-process has been implemented. An equivalent circuit model is proposed to analyze the performance of the microwave switch. The components of the microwave switch consist of a coplanar waveguide (CPW), a suspended membrane and supported springs. The post-process requires only one wet etching to etch the sacrificial layer, and to release the suspended structures. Experimental results show that the switch has an insertion loss of −2 dB at 50 GHz and an isolation of −15 dB at 50 GHz. The driving voltage of the switch approximates to 19 V.     

Fabrication and characterization of a microelectromechanical tunable capacitor

A micromechanical tunable capacitor fabricated using the commercial 0.35 μm complementary metal oxide semiconductor (CMOS) process and the post-process has been investigated in this study. The structure of the tunable capacitor consists of a membrane, supported beams, driving and sensing electrodes. The membrane is sustained by the supported beams. The tunable capacitor requires only one wet etching post-process to release the suspended structures. The post-process has the advantages of easy execution and low cost. The tunable capacitor contains a driving part and a sensing part. The sensing part generates a change in capacitance when applying a driving voltage to the driving part. Experimental results show that the tunable capacitor has a capacitance of 1.38 pF, a tuning range of 85% and a Q-factor of 40 at 100 MHz.     

0.4-V bulk-driven differential-difference amplifier

A new solution for an ultra-low-voltage, low-power, bulk-driven fully differential-difference amplifier (FDDA) is presented in the paper. Simulated performance of the overall FDDA for a 50 nm CMOS process and supply voltage of 0.4 V, shows dissipation power of 31.8 μW, the open loop voltage gain of 58.6 dB and the gain-bandwidth product (GBW) of 2.3 MHz for a 20 pF load capacitance. Despite the very low supply voltage, the FDDA exhibits rail-to-rail input/output swing. The circuit performance has also been tested in two applications; the differential voltage follower and the second-order band-pass filter, showing satisfactory accuracy and dynamic range.     

A cascade energy band structure enhances the carrier energy in organic vertical-type triodes

Organic vertical-type triodes (OVTs) based on the cascade energy band structure as emitter layer are studied. The electric characteristics were dramatically enhanced while incorporating the cascade energy under current driving and voltage driving modes. The improvement is attributed to that injection carriers can obtain higher energy through a stepwise energy level. When the device has a layered structure of F₁₆CuPC (10 nm)/PTCDI (10 nm)/pentacene (100 nm) in emitter, it exhibits a common-base transport factor of 0.99 and a common-emitter current gain of 225 under current driving mode and exhibits a high current modulation-exceeding ?520 μA for a low collector voltage of ?5 V and a base voltage of ?5 V and the current on/off ratio of 10³ under voltage driving mode. Furthermore, we realized first organic current mirror that exhibited out/in current ratio of 0.75 and output resistance of 10⁵ Ω by using the OVTs.     

Anodic Ta2O5 for CMOS compatible low voltage electrowetting-on-dielectric device fabrication

This paper reports a CMOS compatible fabrication procedure that enables electrowetting-on-dielectric (EWOD) technology to be post-processed on foundry CMOS technology. With driving voltages less than 15 V it is believed to be the lowest reported driving voltage for any material system compatible with post-processing on completed integrated circuits wafers. The process architecture uses anodically grown tantalum pentoxide as a pinhole free high dielectric constant insulator with an overlying 16 nm layer of Teflon-AF^®, which provides the hydrophobic surface for droplets manipulation. This stack provides a very robust dielectric, which maintains a sufficiently high capacitance per unit area for effective operation at a reduced voltage (15 V) which is more compatible with standard CMOS technology. The paper demonstrates that the sputtered tantalum layer used for the electrodes and the formation of the insulating dielectric can readily be integrated with both aluminium and copper interconnect used in foundry CMOS.     

Sub 0.5-V bulk-driven LTA in 0.18 μm CMOS

The paper deals with a new solution for an ultra-low-voltage loser take all (LTA) circuit, capable to operate from supply voltages ranging from 0.3 to 0.5 V. The proposed circuit exploit the idea of multiple voltage buffers with a common output. In order to obtain a compact and precise LTA, a new kind of an ultra-low-voltage buffer has been developed. Owing to the fact that for such a low supply voltage the available voltage swing is highly reduced, the impact of transistor mismatches and speed-accuracy-power tradeoffs have extensively been discussed in the paper. While implemented in a standard 0.18 μm CMOS process, the proposed LTA circuit in a two-input version consumes 3.0 μW from a 0.5 V supply and provides 10 μs crossover recovery time for a 1 pF load capacitance.     

Silicon-on-insulator power integrated circuits

A power integrated circuit process has been developed, based on silicon-on-insulator, which allows intelligent CMOS control circuitry to be placed alongside integrated high-voltage power devices. A breakdown voltage of 335 V has been obtained by using a silicon layer of 4 μm thickness together with a buried oxide layer of 3 μm thickness. The respective LDMOS specific on-resistance and LIGBT on-state voltage for this breakdown voltage were 148 mΩ cm² and 3.9 V, respectively.     

Capacitance characterization of tapered through-silicon-via considering MOS effect

In this paper, closed-form expression for the parasitic capacitance of tapered TSV (T-TSV) considering metal–oxide–semiconductor (MOS) effect is proposed by solving two-dimensional (2D) Poisson's equation. ANSYS Q3D Extractor is employed to verify the proposed model for the slope wall angle of 75°, 80°, 85° and 90°. It is shown that error is less than ~5%. The capacitance characterization of copper T-TSV is studied in detail, by taking slope wall angle of 80° for instance. The results show that the capacitance of T-TSV acts as that of MOS device in changing the bias voltage; the increases of the bottom radius of T-TSV (from 1 to 5 μm), dielectric liner thickness (from 0.1 to 0.5 μm), liner dielectric constant (from 1 to 5), T-TSV height (from 10 to 50 μm) and acceptor concentration (from 1×10¹⁵ to 5×10¹⁵ cm⁻³) cause increase of T-TSV capacitance by about 25 fF, −12 fF, 12 fF, 210 fF and 12 fF, respectively. Finally, the condition for T-TSV simplified to cylindrical TSV is obtained.     

Fabrication of high-speed InP/InGaAs/InP DHBT with a new self-aligned metallization technique for reduced base resistance

A new self-aligned emitter–base metallization (SAEBM) technique with wet etch is developed for high-speed heterojunction bipolar transistors (HBTs) by reducing extrinsic base resistance. After mesa etch of the base layer using a photo-resist mask, the base and emitter metals are evaporated simultaneously to reduce the emitter–base gap (S_EB) and base gap resistance (R_GAP). The InP/InGaAs/InP double heterojunction bipolar transistor (DHBT) fabricated using the technique has a reduced R_GAP, from 16.48 Ω to 4.62 Ω comparing with the DHBT fabricated by conventional self-aligned base metallization (SABM) process. Furthermore, we adopt a novel collector undercut technique using selective etching nature of InP and InGaAs to reduce collector–base capacitance (C_CB). Due to the reduced R_GAP, the maximum oscillation frequency (f_max) for a 0.5 μm-emitter HBT is improved from 205 GHz to 295 GHz, while the cutoff frequency (f_T) is maintained at around 300 GHz.     

Self-aligned flexible organic thin-film transistors with gates patterned by nano-imprint lithography

Many applications that rely on organic electronic circuits still suffer from the limited switching speed of their basic elements – the organic thin film transistor (OTFT). For a given set of materials the OTFT speed scales inversely with the square of the channel length, the parasitic gate overlap capacitance, and the contact resistance. For maximising speed we pattern transistor channels with lengths from 10 μm down to the sub-micrometre regime by industrially scalable UV-nanoimprint lithography. The reduction of the overlap capacitance is achieved by minimising the source–drain to gate overlap lengths to values as low as 0.2 μm by self-aligned electrode definition using substrate reverse side exposure. Pentacene based organic thin film transistors with an exceptionally low line edge roughness <20 nm of the channels, a mobility of 0.1 cm²/Vs, and an on–off ratio of 10⁴, are fabricated on 4″ × 4″ flexible substrates in a carrier-free process scheme. The stability and spatial distribution of the transistor channel lengths are assessed in detail with standard deviations of L ranging from 185 to 28 nm. Such high-performing self-aligned organic thin film transistors enabled a ring-oscillator circuit with an average stage delay below 4 μs at an operation voltage of 7.5 V.     

High-speed organic single-crystal transistors gated with short-channel air gaps: Efficient hole and electron injection in organic semiconductor crystals

Short-channel, high-mobility organic filed-effect transistors (OFETs) are developed based on single crystals gated with short-channel air gaps. The high hole mobility of 10 cm²/Vs for rubrene, and high electron mobility of 4 cm²/Vs for PDIF-CN₂ crystals are demonstrated even with a short channel length of 6 μm. Such performance is due to low contact resistance in these devices estimated to be as low as ～0.5 kΩ cm at gate voltage of ?4 V for rubrene. With the benefit of the short channel length of 4.5 μm in a new device architecture with less parasitic capacitance, the cutoff frequency of the rubrene air–gap device was estimated to be as high as 25 MHz for drain voltage of ?15 V, which is the fastest reported for p-type OFETs, operating in ambient conditions.     

High-speed organic transistors with three-dimensional organic channels and organic rectifiers based on them operating above 20 MHz

Three-dimensional organic transistors (3D-OFETs) comprising vertical short channels are developed to raise the operational speed of organic transistors. The devices with a short-channel length of 0.8 μm and reduced parasitic capacitance operate at up to 20 MHz with an applied drain voltage of −15 V. Organic rectifiers based on the diode-connected 3D-OFETs are also demonstrated to operate at above 20 MHz, even with an applied effective voltage of about 4 V, which is higher than the speed of radio frequency identification tags of 13.56 MHz required in near field communication. These techniques boost the performance of organic transistors and can help to realize the breakthrough for practical applications of organic logic circuits used as key components in various flexible or plastic devices.     

An investigation on capacitance-trigger ESD protection devices for high voltage integrated circuits

A novel cascaded complementary dual-directional silicon controlled rectifier (CCDSCR) structure has been proposed and implemented in a 0.5 μm 20 V Bipolar/CMOS/DMOS process as an ESD (electrostatic discharge) protection device. The ESD characteristics of the capacitance-trigger CCDSCR has been investigated by transmission line pulse (TLP) testing. Compared with the substrate-trigger insulated gate bipolar transistor with the enhanced substrate parasitic capacitance, the gate-driven trigger insulated gate bipolar transistor with the gate coupling capacitance and the normal dual-directional silicon controlled rectifier, the CCDSCR has the highest holding voltage of about 25.4 V and the best current conduction uniformity. In addition, it has the best figure of merit (FOM) with the value of about 0.64 mA/μm². The good current conduction uniformity in CCDSCR due to the enhanced substrate parasitic capacitance-trigger effect is finally confirmed by Sentaurus simulations.     

In situ modification of low-cost Cu electrodes for high-performance low-voltage pentacene thin film transistors (TFTs)

We demonstrate low-voltage pentacene thin film transistors (TFTs) using in situ modified low-cost Cu (M-Cu) as source–drain (S/D) electrodes and solution-processed high capacitance (200 nF/cm²) gate dielectrics. Under a gate voltage of ?3 V, the device with M-Cu electrodes shows a much higher apparent mobility (1.0 cm²/V s), a positively shifted threshold voltage (?0.62 V), a lower contact resistance (0.11 MΩ) and a larger transconductance (12 μS) as compared to the device with conventional Au electrodes (corresponding parameters are 0.71 cm²/V s, ?1.44 V, 0.41 MΩ, and 5.7 μS, respectively). The enhancement in the device performance is attributed to the optimized interface properties between S/D electrodes and pentacene. Moreover, after encapsulation the M-Cu electrodes with a thin layer of Au in the aim of suppressing unfavorable surface oxidation, the electronic characteristics of the device are further improved, and highly enhanced apparent mobility (2.3 cm²/V s) and transconductance (19 μS) can be achieved arising from the increased conductivity of the electrode itself. Our study provides a simple and feasible approach to achieve high performance low-voltage OTFTs with low-cost S/D electrodes, which is desirable for large area applications.     

Electrical and optical characteristics of phosphorescent organic light-emitting device with thin-codoped layer insertion

In this paper, we demonstrated the changes of electrical and optical characteristics of a phosphorescent organic light-emitting device (OLED) with tris(phenylpyridine)iridium Ir(ppy)₃ thin layer (4 nm) slightly codoped (1%) inside the emitting layer (EML) close to the cathode side. Such a thin layer helped for electron injection and transport from the electron transporting layer into the EML, which reduced the driving voltage (0.40 V at 100 mA/cm²). Electroluminescence (EL) spectral shift at different driving voltage was observed in our blue OLED with [(4,6-di-fluoropheny)-pyridinato-N,C^2′]picolinate (FIrpic) emitter, which came from the recombination zone shift. With the incorporation of thin-codoped Ir(ppy)₃, such EL spectral shift was almost undetectable (color coordinate shift (0.000, 0.001) from 100 to 10,000 cd/m²), due to the compensation of Ir(ppy)₃ emission at low driving voltage. Such a methodology can be applied to a white OLED which stabilized the EL spectrum and the color coordinates ((0.012, 0.002) from 100 to 10,000 cd/m²).     

Reliability challenges for barrier/liner system in high aspect ratio through silicon vias

The reliability results for barrier/liner systems in different high aspect ratio (5 × 50 μm) through silicon vias (TSV) are presented. Quite a few factors can influence the TSV barrier/liner reliability performance, including the TSV trench etch process, the oxide liner material/thickness, etc. The challenges for more advanced TSV technology nodes (e.g. 3 × 40 μm) are also discussed and possible solutions are proposed.     

Realizing high breakdown voltage for a novel interface charges islands structure based on partial-SOI substrate

A novel interface charge islands partial-SOI (ICI PSOI) high voltage device with a silicon window under the source and its mechanism are studied in this paper. ICI PSOI is characterized by a series of equidistant high concentration n⁺-regions on the bottom interface of top silicon layer. On the condition of high-voltage blocking state, inversion holes located in the spacing of two n⁺-regions effectively enhance the electric field of the buried oxide layer (E_I) and reduce the electric field of the silicon layer (E_S), resulting in a high breakdown voltage (V_B). It is shown by the simulations that the enhanced field ΔE_I and reduced field ΔE_S by the accumulated holes reach to 449 V/μm and 24 V/μm, respectively, which makes V_B of ICI PSOI increase to 663 V from 266 V of the conventional PSOI on 5 μm silicon layer and 1 μm buried oxide layer with the same silicon window length. On-resistance of ICI PSOI is lower than that of the conventional PSOI. Moreover, self-heating-effect is alleviated by the silicon window in comparison with the conventional SOI at the same power of 1 mW/μm.     

A wide output range voltage-mode buck converter with fast voltage–Tracking speed for RF power amplifiers

A high switching frequency voltage-mode buck converter with fast voltage-tracking speed, wide output range and PWM/PSM control strategy for radio frequency (RF) power amplifiers (PAs) has been proposed. To achieve the fast voltage-tracking speed, the maximum charging and discharging current control method has been used, and the filter inductor and capacitor values are reduced. A novel compensated error amplifier (EA) is presented to realize the wide output range. The investigated converter has been fabricated with GF 0.35 μm CMOS process and can operate at 5 MHz with the output voltage range from 0.6 V to 3.4 V. The experimental results show that the voltage-tracking speed can achieve 8.8 μs/V for up-tracking and 6 μs/V for down-tracking. Besides, the recovery time is less than 8 μs when the load change step is 400 mA.     

Pseudo-V2 control with adaptive compensation for fast-transient current-mode buck converter

A type of pseudo-V² control, with on-chip adaptive compensation to achieve fast transient (FT) response for current mode DC–DC buck converter, has been proposed and simulated using 0.18 μm CMOS technology in this paper. Based on a new on-chip capacitor multiplier, adaptive compensation is achieved by making the compensation capacitance to track the load current. The proposed pseudo-V² control utilizes the output ripple to determine the duty cycle during load transient. Thus the overshoot/undershoot voltage and the transient recovery time are effectively reduced. Simulation results demonstrate the transient ripple is smaller than 50 mV and the transient recovery time is shorter than 10 μs for a 450 mA load current step. The maximum power conversion efficiency is 94.6% at 1 MHz switching frequency when input and output voltages are 5 V and 1.8 V, respectively.