Reducing Test Time in the High-Volume Production of Analog Circuits using Efficient Test-Vector Generation and Interpolation Techniques

Test cost is one of the main factors determining the profit margin of a device in production. Current test strategies require hundreds of measurements to determine the specifications of a parameter. In this paper, we present an automatic test-vector generation technique that is based on transfer function manipulation and requires only one circuit simulation. The proposed method consists of generating the first set of vectors by applying a derivation technique to the golden transfer function of the circuit under test (CUT). An interpolation technique allows a new transfer function to be constructed based on the first set of test vectors. The difference between the reconstructed transfer function and the golden transfer function is used to select the second set of test vectors. These new test vectors are selected to achieve the best possible fit. Our technique reduces the test vector size to values that at present can be achieved only by using powerful and time-consuming fault simulation tools. As an example, we apply the method to state variable and Chebyshev filters. We also compute the fault coverage in order to demonstrate the effectiveness of this new technique.     

基于闭环集成运放的模拟电路模块级软故障诊断

基于斜率故障模型,提出了一种诊断模拟电路中基于闭环集成运算放大器的模块级软故障的字典法.在由闭环运放组成的模拟电路中,通过对电路以闭环运放及与其输入直接相连的元件看作一个整体划分模块,对各个模块中的任一元件或进行宏模型替代之后的运放等效电路,利用电路中的两节点电压增量计算出的斜率作为统一故障特征,建立故障字典,实现电路中相应模块包含的运放和所有元件的软故障诊断.给出了运放的等效宏模型和模块级软故障的诊断步骤,并用仿真实例证明了该诊断方法的有效性.     

A test and calibration strategy for adjustable RF circuits

A test and calibration strategy suitable for adjustable RF circuits is presented in this paper. Certain performance-affecting circuit elements are designed to be digitally controllable, providing the capability to adjust the performance characteristics of a circuit’s instance around their post-fabrication values, throughout a set of discrete states of operation. The alternate test methodology is adopted for test and calibration and a set of optimally selected test observables is used to develop regression models for the prediction of the circuit’s performance characteristics in every state of operation. In the test phase, measurements of the test observables are obtained from a subset of the circuit’s states. The processing of these observables provides accurate prediction of the RF circuit’s performance characteristics in all available states and enables the discrimination of defect-free from defective circuits. The latter is further accomplished by the exploitation of an extended superset of the test observables, the use of which intends to maximize fault coverage. Moreover, the predicted performance characteristics are also used to examine compliance with the specifications and to allow calibration of the RF circuit by identifying the appropriate state of operation at which all specifications are met and, consequently, by forcing the circuit to operate in this specific state. The efficiency of the proposed technique has been validated by its application to a typical differential RF Mixer designed in a 0.18 μm CMOS technology. Simulation results have been obtained and assessed.     

开关电容积分器的瞬态行为模型

对电路进行行为级模拟的关键是建立电子子模块的行为模型，用以描述电路模块的功能以及电路非理想效应的影响。本文采用瞬态分析方法，建立了基本模拟单元电路开关电容积分 的行为模型。由于对积分器中的运算放大器采用了单极点跨导运放模型，考虑了其有限增益、带宽、转换速率和输出阻抗的影响，提高了开关电容积分器行为模型的精度。电路模拟的结果表明，模型的误差在３％以内。     

Techniques for estimating test length under random test

When a circuit is tested using random or pseudorandom patterns, it is essential to determine the amount of time (test length) required to test it adequately. We present a methodology for predicting different statistics of random pattern test length. While earlier methods allowed estimation only of upper bounds of test length and only for exhaustive fault coverage, the technique presented here is capable of providing estimates of all statistics of interest (including expected value and variance) for all coverage specifications.Our methodology is based on sampling models developed for fault coverage estimation [1]. Test length is viewed as awaiting time on fault coverage. Based on this relation we derive the distribution of test length as a function of fault coverage. Methods of approximating expected value and variance of test length are presented. Accuracy of these approximations can be controlled by the user. A practical technique for predicting expected test length is developed. This technique is based on clustering faults into equal detectability subsets. A simple and effective algorithm for fault clustering is also presented. The sampling model is applied to each cluster independently and the results are then aggregated to yield test lengths for the whole circuit. Results of experiments with several circuits (both ISCAS '85 benchmarks and other practical circuits) are also provided.This work was done while the author was with the Department of Electrical Engineering, Southern Illinois University, Carbondale, IL 62901.     

Test Generation and Fault Simulation for Cell Fault Model using Stuck-at Fault Model based Test Tools

Cell Fault Model (CFM) is a well-adopted functional fault model used for cell-based circuits. Despite of the wide adoption of CFM, no test tool is available for the estimation of CFM testability. The vast majority of test tools are based on the single stuck-at fault model.In this paper we introduce a method to calculate the CFM testability of a cell-based circuit using any single stuck-at fault based test tool. Cells are substituted by equivalent cells and Test Generation and Fault Simulation for CFM are emulated by Test Generation and Fault Simulation for a set of single stuck-at faults of the equivalent cells. The equivalent cell is constructed from the original cell with a simple procedure, with no need of knowledge of gate-level implementation, or its function. With the proposed methodology, the maturity and effectiveness of stuck-at fault based tools is used in testing of digital circuits, with respect to Cell Fault Model, without developing new tools.     

低电压SRAM测试电路设计与实现

本文基于SMIC 40nm LL CMOS工艺对一款256Kb的低电压8T SRAM芯片进行测试电路设计与实现,重点研究低电压SRAM的故障模型和测试算法,并完成仿真验证与分析。电路主要包括DFT电路和内建自测试电路两部分,前者针对稳定性故障有着良好的覆盖率,后者在传统March C+算法基础上,提出了一种新的测试算法,March-Like算法,该算法能够实现更高的故障覆盖率。仿真结果表明,本文设计的DFT电路能够减小稳定性故障的最小可检测电阻,提高了稳定性故障的测试灵敏度;March-Like算法可以检测到低电压SRAM阵列中的写破坏耦合故障、读破坏耦合故障和写干扰故障。     

Fault Detection and Automated Fault Diagnosis for Embedded Integrated Electrical Passives

In this paper, we propose a novel test technique for fault detection and automated fault diagnosis using pole/zero analysis of embedded integrated passives. For performing pole/zero analysis, an ensemble of circuits obtained by perturbing the circuit under test parameters using their known statistical distributions is generated. From knowledge of the passive circuit specifications, the poles and zeros of every such circuit are extracted and pass and fail regions for the critical poles and zeros are computed in the real-imaginary plane. The proposed test technique uses a region-matching algorithm to detect faults and perform automated diagnosis of catastrophic and parametric faults using frequency domain 2-port measurements. A practical example is presented in order to verify the proposed pole/zero analysis using the fabricated embedded RC device.     

Test‐Generation‐Based Fault Detection in Analog VLSI Circuits Using Neural Networks

In this paper, we propose a novel test methodology for the detection of catastrophic and parametric faults present in analog very large scale integration circuits. An automatic test pattern generation algorithm is proposed to generate piece‐wise linear (PWL) stimulus using wavelets and a genetic algorithm. The PWL stimulus generated by the test algorithm is used as a test stimulus to the circuit under test. Faults are injected to the circuit under test and the wavelet coefficients obtained from the output response of the circuit. These coefficients are used to train the neural network for fault detection. The proposed method is validated with two IEEE benchmark circuits, namely, an operational amplifier and a state variable filter. This method gives 100% fault coverage for both catastrophic and parametric faults in these circuits.     

Delay fault testing using partial multiple scan chains

Delay test patterns can be generated at the functional level of the circuit using a software prototype model, when the primary inputs, the primary outputs and the state variables are available only. Functional delay test can be constructed for scan and non-scan sequential circuits. Functional delay test constructed using software prototype model can detect transition faults at the structural level quite well. Therefore, we propose a new iterative functional test generation approach. The proposed approach involves a partial multiple scan chain construction using the results of functional delay test generation at a high level of abstraction. The iterativeness of the method allows finding the compromise between the test coverage, hardware overhead and test length. Furthermore, using the partial multiple scan chains requires less hardware overhead resulting in shorter test application times. The experimental results are provided for the ITC’99 benchmark circuits. Experiments showed that the obtained transition fault coverage is on average 2% higher than using full scan and commercial automatic test pattern generator for transition faults.     

模拟电路故障诊断的结点电压灵敏度比值法

在证明线性电路中结点电压变化量比值等于结点电压灵敏度比值的基础上,提出了结点电压灵敏度比值法,通过结点电压变化量比值和结点电压灵敏度比值的比对确定电路的故障元件。理论分析和实验结果表明,该方法算法简单、诊断速度快,在可测点受限条件下具有较高的诊断精度,特别适合大规模线性模拟电路的故障诊断和测试。     

针对容性负载的线性功率放大电路的稳定性设计

针对容性负载,从线性功率放大电路稳定性设计的角度,以某压电执行器为研究对象,通过分析相关的设计指标,选择出适用的功率运算放大器;运用噪声增益和反馈零点这两种相位补法,提高了电路的稳定性,避免了超调和振荡,通过理论计算、模型仿真、实物检测相结合的方式,逐步地验证了所做的稳定性设计是有效的、可行的。     

Adaptive Modeling of Analog/RF Circuits for Efficient Fault Response Evaluation

In this paper, we propose a methodology for adaptive modeling of analog/RF circuits. This modeling technique is specifically geared towards evaluating the response of a faulty circuit in terms of its specifications and/or measurements. The goal of this modeling approach is to compute important test metrics, such as fail probability, fault coverage, and/or yield coverage of a given measurement under process variations. Once the models for the faulty and fault-free circuit are generated, we can simply use Monte-Carlo sampling (as opposed to Monte-Carlo simulations) to compute these statistical parameters with high accuracy. We use the error budget that is defined in terms of computing the statistical metrics and the position of the threshold(s) to decide how precisely we need to extract the necessary models. Experiments on LNA and Mixer confirm that the proposed techniques can reduce the number of necessary simulations by factor of 7 respectively, in the computation of the fail probability.     

Application of Rollout Strategy to Test Points Selection for Integer-Coded Fault Wise Table

Test points selection for integer-coded fault wise table is a discrete optimization problem. The global minimum set of test points can only be guaranteed by an exhaustive search which is eompurationally expensive. In this paper, this problem is formulated as a heuristic depth-first graph search problem at first. The graph node expanding method and rules are given. Then, rollout strategies are applied, which can be combined with the heuristic graph search algorithms, in a computationally more efficient manner than the optimal strategies, to obtain solutions superior to those using the greedy heuristic algorithms. The proposed rollout-based test points selection algorithm is illustrated and tested using an analog circuit and a set of simulated integer-coded fault wise tables. Computa- tional results are shown, which suggest that the rollout strategy policies are significantly better than other strategies.     

A hierarchical test generation methodology for digital circuits

A new hierarchical modeling and test generation technique for digital circuits is presented. First, a high-level circuit model and a bus fault model are introduced—these generalize the classical gate-level circuit model and the single-stuck-line (SSL) fault model. Faults are represented by vectors allowing many faults to be implicitly tested in parallel. This is illustrated in detail for the special case of array circuits using a new high-level representation, called the modified pseudo-sequential model, which allows simultaneous test generation for faults on individual lines of a multiline bus. A test generation algorithm called VPODEM is then developed to generate tests for bus faults in high-level models of arbitrary combinational circuits. VPODEM reduces to standard PODEM if gate-level circuit and fault models are used. This method can be used to generate tests for general circuits in a hierarchical fashion, with both high- and low-level fault types, yielding 100 percent SSL fault coverage with significantly fewer test patterns and less test generation effort than conventional one-level approaches. Experimental results are presented for representative circuits to compare VPODEM to standard PODEM and to random test generation techniques, demonstrating the advantages of the proposed hierarchical approach.     

基于BP网络的数字电路多故障诊断研究

为了更有效地对数字电路进行多故障诊断,提出了一种利用电路的故障真值表来表征电路在有故障和无故障状态下的特征信息来对电路进行故障诊断的新方法。该方法使用BP型神经网络,运用误差反向传播算法,把从电路中提取的有效特征信息作为样本对网络反复训练,从而实现用单故障对多故障进行诊断的目的。实验表明该方法可以有效、方便地实现电路的故障检测和定位,为多故障诊断的研究提供了一种新思路。     

OBIST methodology incorporating modified sensitivity of pulses for active analogue filter components

In this paper, oscillation-based built-in self-test method is used to diagnose catastrophic and parametric faults in integrated circuits. Sallen–Key low pass filter and high pass filter circuits with different gains are used to investigate defects. Variation in seven parameters of operational amplifier (OP-AMP) like gain, input impedance, output impedance, slew rate, input bias current, input offset current, input offset voltage and catastrophic as well as parametric defects in components outside OP-AMP are introduced in the circuit and simulation results are analysed. Oscillator output signal is converted to pulses which are used to generate a signature of the circuit. The signature and pulse count changes with the type of fault present in the circuit under test (CUT). The change in oscillation frequency is observed for fault detection. Designer has flexibility to predefine tolerance band of cut-off frequency and range of pulses for which circuit should be accepted. The fault coverage depends upon the required tolerance band of the CUT. We propose a modification of sensitivity of parameter (pulses) to avoid test escape and enhance yield. Result shows that the method provides 100% fault coverage for catastrophic faults.     

A new swarm-SVM-based fault diagnosis approach for switched current circuit by using kurtosis and entropy as a preprocessor

This paper presents a new fault diagnosis method for switched current (SI) circuits. The kurtoses and entropies of the signals are calculated by extracting the original signals from the output terminals of the circuit. Support vector machine (SVM) is introduced for fault diagnosis using the entropies and kurtoses as inputs. In this technique, a particle swarm optimization is proposed to optimize the SVM to diagnose switched current circuits. The proposed method can identify faulty components in switched current circuit. A low-pass SI filter circuit has been used as test beached to verify the effectiveness of the proposed method. The accuracy of fault recognition achieved is about 97 % although there are some overlapping data when tolerance is considered. A comparison of our work with Long et al. (Analog Integr Circuit Signal Process 66:93–102, 2011), which only used entropy as a preprocessor, reveals that our method performs well in the part of fault diagnostic accuracy.     

An efficient structural approach to board interconnect diagnosis

In this paper we present an efficient structural approach for diagnosing board interconnects using boundary-scan. Whereas existing diagnosis approaches assume only wired-AND or wired-OR bridging fault model, we consider a more complex bridging short fault model in a CMOS circuit environment. The diagnostic test set is generated on the basis of graph theoretic technique and the adjacency fault model is adopted. By using the structural information of the wiring layout, the test length can be reduced. Both one-step and two-step diagnosis algorithms are given. They guarantee the complete diagnosis of multiple interconnect faults with no aliasing or confounding. The algorithms have been evaluated by simulation on several benchmark layouts and randomly generated layouts. Simulation results show that more than 50% reduction in the number of tests can be achieved for two-step diagnosis when the fault rate is very small, such as in a matured product line. This can significantly save the diagnosis cost for boundary-scan testing.