Gate charge behaviors in N-channel power VDMOSFETs during HEF and PBT stresses

This paper reports the effects of high electric field stress (HEFS) and positive bias temperature instability (PBTI) in threshold voltage, input and Miller capacitances of N⁻channel power VDMOSFETs. The procedure used for this study is based on the analysis of the gate charge characteristics, the two-dimensional simulation of the structure, and the physical properties of the device. The gate charge characteristics investigated during and up to 500 h of HEFS and PBTI show some degradation of physical device properties. The results are analysed and parameters responsible of these degradations are extracted. It is shown that the main degradation issues in the Si power VDMOSFETs are the charge trapping and the trap creation at the interface of the gate dielectric, induced by energetic free carriers which have sufficient energy to cross the SiO₂/Si barrier.     

MOSFET parameter degradation after Fowler–Nordheim injection stress

We have investigated the degradation of tunnel oxides due to Fowler–Nordheim electron injection from polysilicon gate. Tested devices are n-MOSFET normally used for Flash EPROM applications with four different technologies for the tunnel oxide layer. Stresses have been performed at different source and drain bias conditions for a total injected charge up to 1 C/cm². The oxide characteristics and degradation have been determined comparing the MOSFET threshold voltage and transconductance peak for as received devices and after each stress step.     

Stress immunity enhancement of the SiN uniaxial strained n-channel metal–oxide–semiconductor field-effect-transistor by channel fluorine implantation

Channel fluorine implantation (CFI) has been successfully integrated with silicon nitride contact etch stop layer (SiN CESL) to investigate electrical characteristics and stress reliabilities of the n-channel metal–oxide–semiconductor field-effect-transistor (nMOSFET) with HfO₂/SiON gate dielectric. Although fluorine incorporation had been used widely to improve device characteristics, however, nearly identical transconductance, subthreshold swing and drain current of the SiN CESL strained nMOSFET combining the CFI process clearly indicates that stress-induced electron mobility enhancement does not affect by the fluorine incorporation. On the other hand, the SiN CESL strained nMOSFET with fluorine incorporation obviously exhibits superior stress reliabilities due to stronger Si–F/Hf–F bonds formation. The channel hot electron stress and constant voltage stress induced threshold voltage shift can be significantly suppressed larger than 26% and 15%, respectively. The results clearly demonstrate that combining the SiN CESL strained nMOSFET with fluorinated gate dielectric using CFI process becomes a suitable technology to further enhance stress immunity.     

Simulation of hot-electron trapping and aging of nMOSFETs

An analysis of the degradation of 1-μm-gate-length nMOSFET operating under normal biasing conditions at room temperature is reported. A physical model of hot-electron trapping in SiO₂ is developed and is used with a two-dimensional device simulator (PISCES) to simulate the aging of the device under normal biasing conditions. The initial degradation takes place near the high-field drain region and spreads over a long time toward the source. The degraded I-V characteristics of the MOSFET exhibit a shift of the pinchoff voltage and a compression of the transconductance, for forward and reverse operation, respectively. The simulated degradation qualitatively agrees with reported experimental data. Large shifts of the MOSFET threshold voltage for small drain voltages result as the degradation is spreading toward the source. An inflection point arises for low gate and drain voltages in the drain I-V characteristics of the MOSFET. This inflection point originates when the pinchoff of the channel-induced trapped-electron charge is overcome by the drain voltage; the drain acts as a second gate (short-channel effect). The estimation of the device's lifetime by simulated aging is proposed     

Investigation of degradation mechanisms in low-voltage p-channel power MOSFETs under High Temperature Gate Bias stress

In this work we investigate the degradation mechanisms occurring in a p-channel trench-gate power MOSFET under High Temperature Gate Bias (HTGB) stress. The impact of negative bias temperature stress is analysed by evaluating relevant figures of merit for the considered device: threshold voltage, transconductance and on-resistance. Temperatures and gate voltages as large as 175 °C and −24 V, respectively, are adopted to accelerate the degradation in the device. Moreover, in order to investigate the origin of degradation mechanisms we analyse the interface states generation and the charge trapping processes, the impact of a switching gate voltage during the stress phase and the recovery phase after HTGB stress.     

Electrical instability in short channel organic thin-film transistors induced by lucky-polaron mechanism

In this work we study the electrical stability under both gate bias stress and gate and drain bias stress of short channel (L = 5 μm) bottom contact/top gate OTFTs made on flexible substrate with solution-processed organic semiconductor and fluoropolymer gate dielectric. These devices show high field-effect mobility (μ_FE> 1 cm²V⁻¹s⁻¹) and excellent stability under gate bias stress (bias stress V_ds = 0V). However, after prolonged bias stress performed at high drain voltage, V_ds, the transfer characteristics show a decreased threshold voltage, degradation of the subthreshold slope and an apparent increase in the field effect mobility. Furthermore, the output characteristics show an asymmetry when measured in forward and reverse mode. These experimental results can be explained considering that the bias stress induces the damage of a small part of the device channel, localized close to the source contact. The analysis of the experimental data through 2D numerical simulations supports this explanation showing that the electrical characteristics after bias stress at high V_ds can be reproduced considering the creation of donor-like interface states and trapping of positive charge into the gate dielectric at the source end of the device channel. In order to explain this degradation mechanism, we suggest a new physical model that, assuming holes injection from the source contact into the channel in bounded polarons, envisages the defect creation at the interface near the source end of the channel induced by injection of holes that gained energy from both the high longitudinal electric fields and the polaron dissolution.     

Some aspects of hot-electron aging in MOSFET's

The injection of hot carriers from Si into SiO_{2} in various MOSFET structures is characterized via direct measurements of gate current. A method of mapping gate currents as a function of both gate and drain bias potentials is described. The deterioration of device parameters with hot-electron injection is also characterized, and it is proposed that the rate of aging is a function not only of the injection and trapping efficiencies, but also of the physical location of the trapped charge.     

Comparative analysis of the DC performance of DG MOSFETs on highly-doped and near-intrinsic silicon layers

A comparison of dc characteristics of fully depleted double-gate (DG) MOSFETs with respect to low-power circuit applications and device scaling has been performed by two-dimensional device simulation. Three different DG MOSFET structures including a conventional N⁺ polysilicon gate device with highly doped Si layer, an asymmetrical P⁺/N⁺ polysilicon gate device with low doped Si layer and a mid-gap metal gate device with low doped Si layer have been analysed. It was found that DG MOSFET with mid-gap metal gates yields the best dc parameters for given off-state drain leakage current and highest immunity to the variation of technology parameters (gate length, gate oxide thickness and Si layer thickness). It is also found that an asymmetrical P⁺/N⁺ polysilicon gate DG MOSFET design offers comparable dc characteristics, but better parameter immunity to technology tolerances than a conventional DG MOSFET.     

SiC JBS二极管和SiC MOSFET的空间辐照效应及机理

基于第六代650 V碳化硅结型肖特基二极管(SiC JBS Diode)和第三代900 V碳化硅场效应晶体管(SiC MOSFET),开展SiC功率器件的单粒子效应、总剂量效应和位移损伤效应研究。20～80 MeV质子单粒子效应实验中,SiC功率器件发生单粒子烧毁(SEB)时伴随着波浪形脉冲电流的产生,辐照后SEB器件的击穿特性完全丧失。SiC功率器件发生SEB时的累积质子注量随偏置电压的增大而减小。利用计算机辅助设计工具(TCAD)开展SiC MOSFET的单粒子效应仿真,结果表明,重离子从源极入射器件时,具有更短的SEB发生时间和更低的SEB阈值电压。栅-源拐角和衬底-外延层交界处为SiC MOSFET的SEB敏感区域,强电场强度和高电流密度的同时存在导致敏感区域产生过高的晶格温度。SiC MOSFET在栅压偏置(U_GS=3 V,U_DS=0 V)下开展钴源总剂量效应实验,相比于漏压偏置(U_GS=0 V,U_DS=300 V)和零压偏置(U_GS=U_DS=0...     

Effects of gamma irradiation on the insulated-gate bipolar transistor

The effects of gamma irradiation on the International Rectifier IRGBC20 insulated-gate bipolar transistor (IGBT) was investigated. These devices were found to be sensitive to gamma irradiation due to their metal-oxide-semiconductor field-effect-transistor (MOSFET) input drive. Total doses as small as 50 Krads(Si) increased the saturated collector current (I_c) by an order of magnitude when the irradiation was performed with zero gate bias. For a constant (V_g − V_th) of 0.5 V, I_c decreased to about half its pre-irradiation value after irradiation to 40 Krads(Si). The threshold voltage of the MOSFET shifted in the negative direction with the largest and smallest shifts occurring for a positive and negative gate bias applied during the irradiation, respectively. The shift in threshold voltage saturated at the cut-in voltage of the P-i-N diode portion of the device, indicating that gamma irradiation does not affect the P-i-N diode. The reverse blocking leakage current of the device is not very sensitive to radiation below a total dose of 400 Krads(Si), but increases sharply for larger doses. All of these radiation-degraded characteristics of the IGBT are primarily the result of increasing interface-state and oxide-trapped charge densities with total radiation dose, which decreases the carrier channel mobility by increased carrier scattering. Both room temperature and 150°C annealing were observed to partially recover all of the device characteristics by reducing the radiation-induced oxide-trapped charges.     

Modeling and simulation of enhancement mode p-GaN Gate AlGaN/GaN HEMT for RF circuit switch applications

An enhancement mode p-GaN gate AlGaN/GaN HEMT is proposed and a physics based virtual source charge model with Landauer approach for electron transport has been developed using Verilog-A and simulated using Cadence Spectre, in order to predict device characteristics such as threshold voltage, drain current and gate capacitance. The drain current model incorporates important physical effects such as velocity saturation, short channel effects like DIBL (drain induced barrier lowering), channel length modulation (CLM), and mobility degradation due to self-heating. The predicted I_d-V_ds, I_d-V_gs, and C-V characteristics show an excellent agreement with the experimental data for both drain current and capacitance which validate the model. The developed model was then utilized to design and simulate a single-pole single-throw (SPST) RF switch.     

Capacitance analysis of devices with electrically floating regions

Operation mechanisms of devices with electrically floating regions have been analyzed by device simulations. An insulator has been modeled as a wide-gap semiconductor and the device simulation has been carried out in the whole region including insulator and floating regions. By using this approach, we have evaluated electrical properties of the capacitances used to represent such devices; i.e., the capacitance of interconnect structures with metal-fill and the drain capacitance of an advanced SOI–MOSFET with an electrically floating interlayer.

When one-fourth of an insulating area between parallel interconnect-lines is occupied by a squared fill, the capacitance between the lines was found to increase by three-fourths, over the value for a parallel plate capacitance without dummy fills. Also, the drain capacitance of an advanced SOI–MOSFET structure, i.e., a Si/oxide/poly-Si/oxide/Si-substrate, was analyzed. When the doping concentration of the electrically floating poly-Si interlayer is not so high, the interlayer is partially depleted and a depletion capacitor is formed. The floating potential varies non-linearly with the applied bias and is smaller than the bias. The total capacitance of a multi-oxide-layered SOI–MOSFET structure is much lower than the MOS capacitance estimated from the oxide thickness. Floating elements have great advantages in terms of decreasing capacitance values.     

Hot-electron-induced interface state generation in n-channel MOSFET's at 77 K

Hot-electron-induced degradation in n-channel Si MOSFET's as a result of stress voltages applied at 77 K was studied. The devices were stressed at 77 K for 48 h with a drain voltage of 5 V and a gate voltage corresponding to that at which maximum substrate current was measured. Comparison of pre-stress and post-stress electrical characteristics for forward and for inverse mode operation at room temperature and at 77 K indicate that the observed degradation was due to the generation of hot-electron-induced acceptor interface states at the drain end of the device approximately 0.09 eV below the Si conduction band edge. No trapped charge resulting from hot-electron injection into the gate oxide was observed. The charge associated with the filled interface states had no observable effect on effective channel electron mobility at room temperature, and reduced that at 77 K by no more than 25 percent of the pre-stress value. Operation of CMOS inverters in either logic state (OFF, ON) resulted in no degradation of either device. Operation in a switching mode at 77 K did result in degradation of the n-channel device but not the p-channel FET. The observed degradation is thought to be correlated with the substrate current generated during the switching transient.     

A new symmetrical double gate nanoscale MOSFET with asymmetrical side gates for electrically induced source/drain

In this paper, we present the unique features exhibited by a novel double gate MOSFET in which the front gate consists of two side gates as an extension of the source/drain. The asymmetrical side gates are used to induce extremely shallow source/drain regions on either side of the main gate. Using two-dimensional and two-carrier device simulation, we have investigated the improvement in device performance focusing on the threshold voltage roll-off, the drain induced barrier lowering, the subthreshold swing and the hot carrier effect. Based on our simulation results, we demonstrate that the proposed symmetrical double gate SOI MOSFET with asymmetrical side gates for the induced source/drain is far superior in terms of controlling the short-channel effects when compared to the conventional symmetrical double gate SOI MOSFET. We show that when the side gate length is equal to the main gate length, the device can be operated in an optimal condition in terms of threshold voltage roll-off and hot carrier effect. We further show that in the proposed structure the threshold voltage of the device is nearly independent of the side gate bias variation.     

Comparison of radio frequency physical vapor deposition target material used for LaOx cap layer deposition in 32 nm NMOSFETs

The MOSFET gate length reduction down to 32 nm requires the introduction of a metal gate and a high-K dielectric as gate stack, both stable at high temperature. Here we use a nanometric layer of Lanthanum to shift the device threshold voltage from 500 mV. Because this layer plays a key role in the device performance and strongly depends on its deposition process, we have compared two LaO_x deposition methods in terms of physical properties and influence on electrical NMOS device parameters. Chemical characterizations have shown a different oxidization state according to Lanthanum thickness deposited. It has been related to threshold voltage shift and gate leakage current variations on NMOS transistors. Furthermore mobility extractions have shown that Lanthanum is a cause of mobility degradation.     

An analytic and accurate model for the threshold voltage of short channel MOSFETs in VLSI

Based on the two-dimensional Poisson equation, the surface potential distribution along the surface channel of a MOSFET has been analytically derived by assuming negligible source and drain junction depths and its minimum potential is then used to determine the threshold voltage. The existence of a minimum surface potential point along the channel of a MOSFET under an applied drain bias is consistent with the numerical results of the two-dimensional analysis. The effects of finite source and drain junction depths have been elegantly included by modifying the depletion capacitance under the gate and the resulted threshold voltage model has been compared to the results of the two-dimensional numerical analysis. It has been shown that excellent agreement between these results has been obtained for wide ranges of substrate doping, gate oxide thickness, channel length (< 1 μm), substrate bias, and drain voltage. Moreover, comparisons between the developed model and the existing experimental data have been made and good agreement has been obtained. The major advantages of the developed model are that no iterations and no adjustable fitting parameters are required. Therefore, this simple and accurate threshold voltage model will become a useful design tool for ultra short channel MOSFETs in future VLSI implementation.     

Quasi-saturation capacitance behavior of a DMOS device

This paper reports a simulation study on the capacitance characteristics of a double-diffused metal-oxide semiconductor (DMOS) device operating in the quasi-saturation region. From the analysis, the capacitance effect of the gate oxide upon the drift region cannot be modeled as an overlap capacitance, because the drain-gate/source-gate capacitances of the DMOS device may exceed the gate-oxide capacitance due to the larger voltage drop over the gate oxide than the change in the imposed gate bias when entering the quasi-saturation region. This effect can be the explanation for the plateau behavior in the gate charge plot during turn-on and turn-off of the DMOS device. Based on the small-signal equivalent capacitance model, the accumulated charge in the drift region below the gate oxide may thoroughly associate with the drain terminal in the prequasi-saturation region and with the source terminal in the quasi-saturation region     

Performance analysis of long Ge channel double gate (DG) p MOSFETs with high-k gate dielectrics based on carrier concentration formulation

In this paper, electrical behavior of symmetric double gate Ge channel MOSFETs with high-k dielectrics is reported on the basis of carrier concentration formalism. The model relies on the solution of Poisson-Boltzmann equations subject to suitable boundary conditions taking into account the effect of interface trap charge density (D_it) and the Pao-Sah’s current formulation considering field dependent hole mobility. It is continuous as it holds good for sub-threshold, weak and strong inversion regions of device operation. The proposed model has been employed to calculate the drain current of DG MOSFETs for different values of gate voltage and drain voltage along with various important device parameters such as transconductance, output conductance, and transconductance per unit drain current for a wide range of interface trap charge density, equivalent oxide thickness (EOT) and bias conditions. Moreover, most of the important device parameters are compared with their corresponding Si counter parts. Accuracy of the model has been verified by comparing analytical results with the numerical simulation data. A notable improvement of the drive current and transconductance for Ge devices is observed with reference to Si devices, particularly when D_it is small.