双极电路欧姆接触问题的工艺分析与解决方案

为解决一种双极集成电路在生产中欧姆接触电阻过大的问题,针对关键工艺进行了统计分析和专项实验,找到了问题的原因和解决方法,对提高大规模集成电路的工艺制造稳定性具有非常重要的意义。     

单块用户接口集成电路其高压功能的实现

本文对介质绝缘和结式绝缘两种双极工艺进行了比较分析，讨论了用介质绝缘工艺双极工艺来实现程控数字交换机单块用户接口集成电路高压功能的优越性。指出介质绝缘双极工艺是实现既经济又优良的电信通信用集成电路的主要工艺。     

双极型器件制做工艺的发展综述

本文通过对双极型器件缩小规则的讨论,总述了双极型器件纵向、横向尺寸缩小所引起的工艺发展,并着重介绍了隔离、多晶发射极和自对准这三方面工艺的演变,从而引出Si高速双极型器件的发展趋势。此外,本文还简述了Si异质结双极型器件的优点。     

高性能模拟集成电路工艺技术

介绍了模拟集成电路工艺的发展过程和现状，讨论了国内的BiCMOS工艺、互补双极工艺(CB)、和SOI双极工艺的最新进展。重点介绍了BiCMOS工艺的研完与开发，指出了模拟集成电路工艺的发展趋势。     

双极器件的可能性和限制

评述了传统的双极正艺所面临的问题,并讨论了先进的“双-多晶硅”自对准双极工艺的潜力和限制。还讨论了缩小这些使用于高性能ECL 和低功率 VLSI 电路中的先进双极晶体管的工艺影响。     

双极数字／模拟电路的相容工艺探讨

实验研究了具有代表性的几种双极相容工艺,认为注磷调整法与现行双极工艺相容性好,在3种电路中应用获得成功,本文叙述了这一工艺方法和实验结果。     

iPOLAR^TM在双极型器件中的应用

美国模拟器件公司(简称ADI)的iPOLAR^TM制造工艺的推出，代表了近20年来．业界对36V双极型工艺进行的最重大的再设计。这种新的iPOLAR工艺适合于需要耐高压双极型模拟器件的工业应用，采用iPOLAR工艺的芯片面积比老的双极型减小。     

Bi-CMOS双极型晶体管的研制

本文论述了在常规CMOS工艺下制作Bi-CMOS双极型晶体管的设计方法及制造工艺.首先通过对Bi-CMOS双极型晶体管版图结构的分析,探讨了工作机理,阐明了采用标准CMOS工艺制作高性能Bi-CMOS双极型晶体管的设计方法.然后,建立了分析计算晶体管直流特性的数学模型,并分析计算了工艺参数、器件结构对器件性能的影响,给出了CMOS工艺全兼容的Bi-CMOS双极型npn晶体管的最佳设计方案.采用常规p阱CMOS工艺进行了投片试制.测试结果表明,器件性能达到了设计指标;器件的电流增益在200以上,与理论计算完全一致.     

减小双极超高速IC尺寸的技术

本文详细叙述了减小双极超高速IC器件的横向尺寸和纵向尺寸的技术,着重在多晶硅基极接触、多晶硅发射极接触、开槽隔离方面作了具体介绍;对八十年代具有代表性的先进双极工艺,如PSA、SICOS、SST、SDK和深槽隔离技术作了详尽的叙述。最后,比较了采用这些工艺所制造的双极器件及电路的性能参数。     

LDO中过温保护电路的设计

LDO是一个微型的片上系统,他包括调整管、采样网络、精密基准源、差分放大器、过流保护、过温保护等电路。分析了LDO中过温保护电路的设计,主要介绍了LDO中双极型过温保护电路和CMOS过温保护电路。由于双极器件开发早、工艺相对成熟、稳定,而且用双极工艺可以制造出速度高、驱动能力强、模拟精度高的器件,适用于高精度的模拟集成电路。因此,双极型集成稳压器应用广泛,其设计技术和制造工艺比较成熟和完善。但双极型过温保护电路本身存在热振荡的问题。给出一种新型的CMOS过温保护电路,他具有温度迟滞功能,有效地避免了芯片出现热振荡。     

METHOD OF PARAMETER STATISTICAL ANALYSIS FOR BIPOLAR INTEGRATED CIRCUIT DESIGN

The method and procedure of realizing parameter statistical correlation analysis ofbipolar analog IC's are given,and the statistical model of parameter are constructed with doubleparameters(B_F,R_S).Based on the comparison and analysis of the circuit characteristics,it isshown that the method can be used for analysis and design of bipolar IC's.     

双极模拟集成电路的参数统计性分析

本文给出了实现双极模拟集成电路参数统计相关性分析的步骤和方法,提出了含对称参数分析的双参数(BF,RS)统计分析方法。实例分析和对比表明,该方法适于模拟集成电路的分析和设计。     

Correlation of fabrication process and electrical device parameter variations

A program for modelling IC fabrication processes is described. Simulated and measured impurity profiles are shown for a bipolar transistor technology. These profiles are used to study the sensitivity of electrical device parameters to process variations. A comparison of simulated device performance using process models gives parameters which bracket measured results for 35 die across a wafer. A statistical model is given which relates twelve parameters to the base transport current.     

Silicon bipolar device structures for digital applications:technology trends and future directions

The double-polysilicon self-aligned bipolar device structure has come a long way since its first inception, but there is still room for further scaling of this structure and continued improvements in performance. An analysis of the current state-of-the-art double-poly structure leads naturally to a discussion of future trends and technologies necessary to continue scaling into the sub-0.25 μm regime. In addition, it has become highly desirable to extend bipolar processes in new directions to take advantage of the opportunities offered by emerging materials technologies, such as bonded silicon-on-insulator films and medium or low temperature Si and SiGe epitaxy. Opportunities also exist for high-performance bipolars in BiCMOS technology and in complementary bipolar processes for low-power, high-speed digital applications. These extensions beyond “conventional” bipolar technology will be discussed in terms of their requirements and the device structures that are evolving to match these needs     

Statistical Simulation for Process Design and Optimization in IC Manufacture

An approach to multidimensional statistical simulation for process design and optimization in IC manufacture is proposed. It essentially takes account of the sensitivity of circuit parameters to the random variability of process parameters. The approach is implemented in an algorithm and software for process statistical analysis and optimization. The response-surface methodology and pattern-recognition techniques are used for the approximation of relations between process and circuit parameters. The capabilities of the approach are evaluated from simulated and measured data on the fabrication of transistors by routine bipolar and CMOS technologies.     

A comparison of GaAs HJBT and silicon bipolar technologies forhigh-speed analog-to-digital converters

The potential using the emerging GaAlAs/GaAs heterojunction bipolar transistor (HJBT) technology is all-parallel analog-to-digital (A/D) converters is studied. To put into perspective the HJBT predictions made, a comparison of the ultimate performance levels achievable with contemporary silicon bipolar processes is given. Optimized latched compensators were developed for each technology and simulations on SPICE were carried out to determine the maximum sample rate and large-signal analog bandwidths that would be achieved. As both technologies are produced in-house, models were available for processors in the latter stages of development, namely the standard 1-μm silicon bipolar process, and the 4-μm HJBT process, as well as processes at an earlier stage of development, the enhanced 1-μm silicon bipolar processes and the 2.5-μm HJBT process. This enabled the trend of performance improvements with time to be compared     

RESET Mechanism of TiOx Resistance-Change Memory Device

In this letter, the physical mechanisms of resetting a TiOx resistance-change memory device are explored for both unipolar and bipolar switching modes. It is observed that the statistical distributions of switching parameters are very different for the two types of switching modes. The data support previous evidence that thermal dissolution of the conductive filament (CF) is the mechanism for unipolar reset, while local redox reaction is responsible for bipolar reset. It is found that the CF is destroyed during unipolar switching but can be reused during bipolar switching.      

Advances in bipolar VLSI

Bipolar IC processes are reviewed, and the impact of BiCMOS technology on bipolar VLSI is discussed. The discussion covers standard emitter-coupled-logic (ECL) circuit configuration, on-chip line driving, output circuitry, series gating, ECL versus CML (current-mode logic), differential logic, noise margins, interconnect capacitance, bipolar VLSI transistor design and scaling, and processes for ECL VLSI     

A complementary bipolar technology family with a VerticallyIntegrated PNP for high-frequency analog applications

Silicon complementary bipolar processes offer the possibility of realizing high-performance circuits for a variety of analog applications. This paper presents a summary of silicon complementary bipolar process technology reported in recent years. Specifically, an overview of a family of silicon complementary bipolar process technologies, called Vertically Integrated PNP (VIP^TMI) which have been used for the realization of high-frequency analog circuits is presented. Three process technologies, termed VIP-3, VIP-3H, and VIP-4H offer device breakdowns of 40, 85, and 170 V, respectively. These processes feature optimized vertically integrated bipolar junction transistors (PNPs) along with high performance NPN transistors with polycrystalline silicon emitters, low parasitic polycrystalline silicon resistors, and metal-insulator-polycrystalline silicon capacitors. Key issues and aspects of the processes are described. These issues include the polycrystalline silicon emitter optimization and vertical and lateral device isolation in the transistors. Circuit design examples are also described which have been implemented in these technologies