Shielded passive devices for silicon-based monolithic microwave and millimeter-wave integrated circuits

This paper introduces floating shields for on-chip transmission lines, inductors, and transformers implemented in production silicon CMOS or BiCMOS technologies. The shield minimizes losses without requiring an explicit on-chip ground connection. Experimental measurements demonstrate Q-factor ranging from 25 to 35 between 15 and 40 GHz for shielded coplanar waveguide fabricated on 10 /spl Omega//spl middot/cm silicon. This is more than a factor of 2 improvement over conventional on-chip transmission lines (e.g., microstrip, CPW). A floating-shielded, differentially driven 7.4-nH inductor demonstrates a peak Q of 32, which is 35% higher than an unshielded example. Similar results are realizable for on-chip transformers. Floating-shielded bond-pads with 15% less parasitic capacitance and over 60% higher shunt equivalent resistance compared to conventional shielded bondpads are also described. Implementation of floating shields is compatible with current and projected design constraints for production deep-submicron silicon technologies without process modifications. Application examples of floating-shielded passives implemented in a 0.18-/spl mu/m SiGe-BiCMOS are presented, including a 21-26-GHz power amplifier with 23-dBm output at 20% PAE (at 22 GHz), and a 17-GHz WLAN image-reject receiver MMIC which dissipates less than 65 mW from a 2-V supply.     

异步式逻辑保障片上网络传输可靠性的研究

随着Si技术的持续发展,片上系统(SoC)的规模和复杂度的增长给传统的片上互连,如总线结构,带来了前所未有的挑战。片上网络[1-2]是片上系统的一种新设计方法,是目前公认应对这种挑战较为有效的解决方案。半导体工艺进入深亚微米时代后,片上网络的可靠性也越来越成为人们关注的问题。将在研究如何应用异步式逻辑保障片上网络互连数据传输的可靠性和服务质量,提出了一个异步式片上网络的架构。通过实验证明,异步式逻辑将极大提高集成电路在应对电源不稳定性、导线间串扰、电磁干扰(EMI)、时钟偏斜和软错误方面的可靠性。采用全局异步局部同步的时钟机制,该方法带来了一种全新的片上通信方法,显著改善了传统总线式系统的性能。     

Basic RF Characteristics of the Microstrip Line Employing Periodically Perforated Ground Metal and Its Application to Highly Miniaturized On-Chip Passive Components on GaAs MMIC

In this study, highly miniaturized on-chip impedance transformers employing periodically perforated ground metal (PPGM) were developed for application to broadband low-impedance matching. In order to realize a broadband operation by using an equal ripple transfer characteristic over a passband, a three-section transformer was designed by mapping its reflection coefficient to the Chebyshev function. The three-section transformer showed a good RF performance over a broadband (1.5–13 GHz) including ultra-wideband. The size of the three-section transformer was 0.129$hboxmm^2$, which is 2.3% of the size of the transformer fabricated by a conventional microstrip line. Using the PPGM structure, a highly miniaturized on-chip Wilkinson power divider with a low port impedance of 13$Omega $was also developed, and its size is 0.11$hboxmm^2$, which is 6% of the size of the one fabricated by the conventional microstrip line. In addition, in this study, the PPGM structure was theoretically characterized using a conventional capacitive loaded periodic structure. Using the theoretical analysis, basic characteristics of the transmission line with PPGM were also investigated in order to evaluate its suitability for application to a development of miniaturized on-chip passive components. According to the results, it was found that the PPGM structure is a promising candidate for application to a development of miniaturized on-chip components on monolithic microwave integrated circuits.     

An asynchronous ternary logic signaling system

This paper presents a new approach to an on-chip asynchronous transmission system suitable for next generation asynchronous on-chip networks. It implements multivalued logic to reduce the number of wires and a low-voltage swing for lower dynamic power dissipation. Furthermore, the transmission system described here enjoys fully static design and has zero static power consumption. Two versions of the transmitter circuit and the receiver are described. The proposed signaling scheme is compared to a classical dual-rail signaling system with regard to speed, power consumption, and reliability. The simulation results show that the asynchronous ternary logic signaling (ATLS) system delivers over 70% higher bandwidth per wire and consumes over 50% less power than the dual-rail signaling system on 10-mm-long on-chip interconnection.     

VCO Design With On-Chip Calibration System

This paper presents a low-supply voltage integrated CMOS voltage-controlled oscillator (VCO) with an on-chip digital VCO calibration control system. The VCO utilizes various state-of-the-art design methods to achieve low phase noise. The calibration system includes a novel high-speed digital divide by two circuit and a counter running on 1-GHz input to enable on-chip frequency measurement. An arithmetic unit and algorithms to perform the calibration are implemented using on-chip logic. Two different types of calibration methods have been implemented and measured in order to compare the proposed VCO gain optimization method with more conventional type of VCO calibration. The measurements show that the VCO design has phase noise from$-$120.5 dBc/Hz to$-$118.7 dBc/Hz @ 400-kHz offset, measured over the frequency range from 1.67 to 1.93 GHz. The proposed VCO gain optimization method is capable of reducing the$K_ VCO$peak-to-peak variation of the presented VCO design from 54.4% to 29.8% in DCS1800 and PCS1900 GSM transmission bands when compared to the conventional type of calibration method.     

Wafer-level package interconnect options

As integrated circuit technology enters the nanometer era, global interconnects are becoming a bottleneck for overall chip performance. In this paper, we show that wafer-level package interconnects are an effective alternative to conventional on-chip global wires. These interconnects behave as LC transmission lines and can be exploited for their near speed of light transmission and low attenuation characteristics. We compare performance measures such as bandwidth, bandwidth density, latency, and power consumption of the package-level transmission lines with conventional on-chip global interconnects for different International Technology Roadmap for Semiconductors (ITRS) technology nodes. Based on these results, we show that package-level interconnects are well suited for power demanding low-latency applications. We also analyze different interconnect options such as memory buses, long inter tile interconnects, clock, and power distribution.     

A novel compact circuit for 4-PAM energy-efficient high speed interconnect data transmission and reception

Transmission of signals, whether on-chip or off-chip, places severe constraints on timing and extracts a large price in energy. New silicon device technologies, such as back-plane CMOS, provide a programmable and adaptable threshold voltage as an additional tool that can be used for low power design. We show that one particularly desirable use of this freedom is energy-efficient high-speed transmission across long interconnects using multi-valued encoding. Our multi-valued CMOS circuits take advantage of the threshold voltage control of the transistors, by using the signal-voltage-to-threshold-voltage span, in order to make area-efficient implementations of 4-PAM (pulse amplitude modulation) transceivers operating at high speed. In a comparison of a variety of published technologies, for signal transmission with interconnects of 10-15 mm length, we show up to 50% improvement in energy for on-chip signal transmission over binary encoding together with higher limits for operating speeds without a penalty in circuit noise margin.     

A 1.5 Gb/s link interface chipset for computer data transmission

The authors designed a set of four ICs to provide encoding, multiplexing, clock extraction/demultiplexing, and decoding for gigabit-rate serial data transmission. These chips form a high bandwidth data link for point-to-point communication. A new line code is implemented that provides DC balance, efficient encoding, framing, and simple clock extraction. Embedded in the code is a fixed transition used by the phase/frequency locked loop (PLL) for simple clock extraction and frame synchronization. Unlike other links, this PLL requires no trimming for data retiming, either in production or later. An on-chip voltage-controlled oscillator (VCO) with a tuning range of 1.1-1.6 GHz is available for use with the PLL. With this chip set the authors demonstrated a transmission rate of 16 bits in parallel at 75 MHz or, with encoding overhead, a serial rate of 1.5 Gb/s     

An advanced demultiplexing system for physiological stimulation

A CMOS very large scale integration (VLSI) chip has been designed and built to implement a scheme developed for multiplexing/demultiplexing the signals required to operate an intracortical stimulating electrode array. Because the use of radio telemetry in a proposed system utilizing this chip may impose limits upon the rate of data transmission to the chip, the scheme described herein was used to reduce the amount of digital information which must be sent to control a large quantity (up to several hundred) of stimulating electrodes. By incorporating multiple current sources on chip, many channels may be stimulated simultaneously. By incorporating on-chip timers, control over pulse timing is assigned to the chip, reducing by up to fourfold the amount of control data which must be sent. By incorporating on-chip RAM, information associated with the desired stimulus amplitude and pulse timing can be stored on chip, In this manner, it is necessary to send control information to the chip only when the information changes, rather than at the stimulus repeat rate for each channel. This further reduces the data rate by a factor of five to ten times or more. The architecture described here, implemented as an eight-channel stimulator, is scalable to a 625-channel stimulator while keeping data transmission rates under 2 Mbps     

A 2-Gbaud 0.7-V swing voltage-mode driver and on-chip terminatorfor high-speed NRZ data transmission

A large-swing, voltage-mode driver and an on-chip termination circuit are presented for high-speed nonreturn-to-zero (NRZ) data transmission through a copper cable. The proposed driver with active pull-up and pull-down can generate a 700-mV signal to deliver a 2 Gbaud serial NRZ data stream. Low output impedance offered by simple negative-feedback resistors alleviates the detrimental effect of the parasitic capacitance by supplying fast current impulses. A proposed on-chip termination circuit provides termination impedance to a mid-supply termination voltage with the benefit of reduced parasitic capacitance and better termination characteristics compared with off-chip termination. The driver and termination circuits have been incorporated in a 2 Gbaud transceiver chip and fabricated in 0.35 μm CMOS technology. Measurements show a 1.4 V differential swing with a slew rate of 2.5 V/ns at the receiver output and a 65% reduction of reflection by the on-chip termination circuit with power consumption of 191 mW at 3.3 V supply     

RF characterization and isolation properties of mesoporous Si by on-chip coplanar waveguide measurements

We report on the broadband electrical characterization of thick mesoporous silicon layers used as RF microplates for on-chip integration of high-Q passive devices in a CMOS-compatible process. To measure the RF losses of the microplate we have fabricated several designs of Coplanar Waveguides (CPWs), for form-factors relevant to the sizes of on-chip passive RF devices, on thick mesoporous Si layers (RF microplates) of various thicknesses, and we compared the results with those obtained from similar CPWs integrated directly on the p-type Si substrate. For maximum measurement sensitivity of the loss, the CPWs were designed to be very good transmission lines matched to 50 Ω port impedances. We also characterized the grown mesoporous Si by performing electromagnetic simulations of the structure and identifying the measured and simulated S-parameters over a broadband frequency region, for the appropriate simulator input of complex permittivity. The measured results show that, for CPW features commensurate with the scale of on-chip RF passive devices, a 50-μm-thick mesoporous Si layer on the Si substrate reduces the losses to 1/6th–1/4th of the values corresponding to a p-type Si substrate, showing that mesoporous Si is an excellent material for CMOS-compatible on-chip integration of high-Q passive devices.     

Time-domain macromodel for lossy VLSI interconnects

A new time-domain model that enables loss effects on the input impedance of on-chip transmission lines during switching transients to be accurately taken into account is presented. The model has been specifically developed for use in conjunction with MOS macromodels to predict the electrical behaviour of matched CMOS buffers. It solves the problem of mixed frequency/time domain analysis by replacing the lines with a lumped time-varying resistor     

Efficient Distributed On-Chip Decoupling Capacitors for Nanoscale ICs

A distributed on-chip decoupling capacitor network is proposed in this paper. A system of distributed on-chip decoupling capacitors is shown to provide an efficient solution for providing the required on-chip decoupling capacitance under existing technology constraints. In a system of distributed on-chip decoupling capacitors, each capacitor is sized based on the parasitic impedance of the power distribution grid. Various tradeoffs in a system of distributed on-chip decoupling capacitors are also discussed. Related simulation results for typical values of on-chip parasitic resistance are also presented. The worst case error is 0.003% as compared to SPICE.      

Enhanced transmission characteristics of on-chip interconnects withorthogonal gridded shield

On-chip interconnects over an orthogonal grid of grounded shielding lines on the silicon substrate are characterized by full-wave electromagnetic simulation. The analysis is based on a unit cell of the periodic shielded interconnect structure. It is demonstrated that the shielding structure may help to significantly enhance the transmission characteristics of on-chip interconnects particularly in analog and mixed-signal integrated circuits with bulk substrate resistivity on the order of 10 Ω-cm. Simulation results for the extracted R, L, G, C transmission line parameters show a significant decrease in the frequency-dependence of the distributed shunt capacitance as well as decrease in shunt conductance with the shielding structure present, while the series inductance and series resistance parameters are nearly unaffected. An extension of the equivalent circuit model for the shunt admittance of unshielded on-chip interconnects to include the effects of shielding is also presented     

Measurement and modeling of on-chip transmission line effects in a400 MHz microprocessor

On-chip interconnect delays are becoming an increasingly important factor for high-performance microprocessors. Consequently, critical on-chip wiring must be carefully optimized to reduce and control interconnect delays, and accurate interconnect modeling has become more important. This paper shows the importance of including transmission line effects in interconnect modeling of the on-chip clock distribution of a 400 MHz CMOS microprocessor. Measurements of clock waveforms on the microprocessor showing 30 ps skew were made using an electron beam prober. Waveforms from a test chip are also shown to demonstrate the importance of transmission line effects     

Voltage-comparator-based measurement of equivalently sampledsubstrate noise waveforms in mixed-signal integrated circuits

This paper describes measurement of substrate noise waveforms in mixed-signal integrated circuits. This method uses wide-band chopper-type single-ended voltage comparators as on-chip noise detectors. By analyzing equivalently sampled comparator outputs in synchronized operation, the noise voltage in the auto-zero and compare modes can be measured separately, and noise waveforms were experimentally reconstructed to within 0.5-ns accuracy. The noise transmission path was analyzed, and this showed that the noise sampled at the auto-zero mode of the comparator can be used to reconstruct substrate noise waveforms with high resolution. The results also explain the influence of noise coupling on analog circuits widely used in on-chip analog-to-digital converters     

High transmission gain integrated antenna on extremely high resistivity Si for ULSI wireless interconnect

We have demonstrated the highest transmission gain integrated dipole antenna on Si reported so far, to use as an integrated antenna for the purpose of ULSI on-chip wireless interconnection. A 2-mm long and 10-/spl mu/m wide dipole antenna pair at a distance of 1 cm shows a transmission gain of -36.5 dB at 18 GHz, which is 20 dB higher than the previously reported gain. This large increase in gain is achieved by proton implantation on the Si substrate, which increased the resistivity from 10 /spl Omega/-cm to 0.1 M/spl Omega/-cm. It is also found that transmission gain can be maximized for a given resistivity by optimizing the Si substrate thickness or by inserting a low-k dielectric layer below the substrate.     

Wafer-level packaging technology for high-Q on-chip inductors and transmission lines

In the current trend toward portable applications, high-Q integrated inductors have gained considerable importance. Hence, much effort has been spent to increase the performance of on-chip Si inductors. In this paper, wafer-level packaging (WLP) techniques have been used to integrate state-of-the-art high-Q on-chip inductors on top of a five-levels-of-metal Cu damascene back-end of line (BEOL) silicon process using 20-/spl Omega//spl middot/cm Si wafers. The inductors are realized above passivation using thick post-processed low-K dielectric benzocyclobutene (BCB) and Cu layers. For a BCB-Cu thickness of 16 /spl mu/m/10 /spl mu/m, a peak single-ended Q factor of 38 at 4.7 GHz has been measured for a 1-nH inductor with a resonance frequency of 28 GHz. Removing substrate contacts slightly increases the performance, though a more significant improvement has been obtained by combining post-processed passives with patterned ground shields: for a 2.3-nH above integrated-circuit (above-IC) inductor, a 115% increase in Q/sub BW//sup max/ (37.5 versus 17.5) and a 192% increase in resonance frequency (F/sub res/: 12 GHz versus 5 GHz) have been obtained as compared to the equivalent BEOL realization with a patterned ground shield. Next to inductors, high-quality on-chip transmission lines may be realized in the WLP layers. Losses below -0.2 dB/mm at 25 GHz have been measured for 50-/spl Omega/ post-processed coplanar-waveguide lines, above-IC thin-film microstrip lines have measured losses below -0.12 dB/mm at 25 GHz.     

Voltage-controlled oscillators up to 98 GHz in SiGe bipolar technology

In this paper, two fully integrated voltage-controlled oscillators (VCOs) in a 200-GHz f/sub T/ SiGe bipolar technology are presented. The oscillators use on-chip transmission lines at the output for impedance transformation. One oscillator operates up to 98 GHz and achieves a phase noise of -85dBc/Hz at an offset frequency of 1 MHz. It can be tuned from 95.2 to 98.4 GHz and it consumes 12 mA from a single -5-V supply. The second oscillator operates from 80.5 GHz up to 84.8 GHz with a phase noise of -87dBc/Hz at 1-MHz offset frequency. The output power of both circuits is about -6dBm.     

片上螺旋变压器等效电路参数的直接提取

本文比较了四端口和两端口测试方式下变压器模型的差异。虽然两端口测试方式对变压器的测试和应用更为合适,但它将给模型参数的提取带来巨大困难。在这篇文章中,一种基于物理意义的等效电路模型和它相应的直接提取步骤被提出来用于片上变压器。基于两端口（而非四端口）测试方式,这种参数提取步骤能够提取器件的模型参数而不需要使用任何参数优化和拟合。在这个步骤中,一个新方法首次被提出用来提取阶梯电路的参数,而阶梯电路被广泛用于模拟各种无源器件中的趋肤效应。这样,这个方法便可以推广应用到其他无源器件的建模中,如片上传输线、电感、巴伦等。为了检验这种参数提取步骤的有效性和准确性,我们用90-nm 1P9M CMOS工艺制作了一个片上互绕型变压器。我们比较了模型仿真和实际测试在自感、品质因数、感性互感系数和阻性互感系数等方面的结果,在很宽的频带宽度内这两者吻合得很好。