The effect of collector resistance upon the high current capability of n-p-ν-n transistors

It is shown that the onset of conductivity modulation of the bulk collector resistance causes an abrupt decrease in hFEat high current density and consequently limits the current range in which a transistor exhibits usable gain. Data are presented which demonstrate the accurate measurement of equilibrium collector resistance from a curve-tracer display. Experimental results showing the effect of partial saturation upon transistor switching time are also presented. Recognition of this phenomenon suggests a reappraisal of the importance of other potential causes of high current hFEdecrease.     

Turn-off processes in high-voltage n-p-ν-n switches

A one-dimensional solution is found for the current-continuity equations that govern minority-carrier removal from the collector region of a saturated bipolar transistor. The shape and position of the charge body is established so that the collector-voltage rise can be predicted, especially in the final stages of turn-off. Constant collector current, corresponding to an inductive load, is assumed during the charge-removal process. The effect of varying the reverse base drive is considered as is turning off from hard- and quasi-saturation. It is shown that the collector region can be swept clear of minority carriers at a collector voltage well below BVCEO. Once minority carriers have been cleared, collector current is supported by a displacement current which causes energy storage, rather than dissipation. Experimental verification is sought with a developmental transistor that minimizes two- and three-dimensional effects. Qualitative agreement is evident; reasonable quantitative agreement does not require unrealistic assumptions. Lastly, the conditions that can precipitate reverse-biased secondary breakdown are identified in an appendix.     

Epitaxial π-ν n-p-n high-voltage power transistors

A new silicon power-transistor structure has been developed which expands the frontiers of power-switching performance and high-voltage power-handling capability. This new structure employs a unique π-ν (nearly intrinsic p- and n-type) epitaxial-layer construction which utilizes "overlay" emitter concepts to achieve improved volt-ampere densities and expanded second-breakdown performance. An n⁺-p-π-ν-n⁺transistor structure is constructed using alternately grown π and ν, epitaxial high-resistivity layers, p-type base and n⁺emitter diffusions are used in the conventional manner to assure punch-through protection. The depletion region for the n⁺-p-π-ν-n⁺transistor is in the π base and the ν collector, and the maximum electrical field (E_{max}) is at the π-ν interface. The avalanche breakdown VBof the device can be controlled by the thickness (X_{n}, X_{p}) and the concentration (N_{A}, N_{D}) of the π-ν layers. Limiting the thickness of the ν collector region and adjusting the thickness of the π base layer provides a transistor with optimum volt-ampere capability. Various π-ν structures have been fabricated and are evaluated electrically for power switching and for linear applications.     

Avalanche-multiplication-region operation of n-p-n?-n+ power transistors

Internal behaviour of an n-p-n?-n+ high-voltage power transistor for the avalanche-multiplication-region operating conditions is presented as obtained by a mathematical model. This model incorporates the avalanche generation of carriers due to electric field and current density and the resulting semiconductor transport equations are solved in two dimensions by numerical methods.     

Turnover phenomenon in N ν N Si devices and second breakdown in transistors

Turnover phenomenon in N νl N Si devices was studied in relation to second breakdown in NP ν N Si transistors. The devices were fabricated by a usual diffusion method using P2O5powder as diffusant source. Four groups of the devices, each having a diameter of 1.0 mm, a thickness of 0.25 mm, a resistivity in ν layer ranging from 3 to 210 ohm-cm, and a surface concentration in N layer of 2 × 10²⁰cm^-3, were tested under two kinds of applied voltage. The applied voltage was a half-cycle voltage from ac source and single-pulse voltage with a rising and flat part. The field strength in ν layer was below 3 × 10³v/cm. The voltage vs. current characteristics and the transient figures of voltage and current were observed on a memoriscope, and the temperature of the device was determined using temperature sensitive paints. The current increases linearly with the increasing voltage at the onset of the V-I curve, and saturates with further increases in voltage. Turnover occurs after the large departure from ohmic behavior in V-I characteristics. At the turnover, the temperature of the device was estimated to be near intrinsic; 160°C for the device with ∼ 210 ohm-cm, 330°C for ∼ 3 ohm-cm. The discussions on turnover characteristics are made in terms of the decrease in carrier mobility, the increase in carrier concentration in ν layer, and the current constriction in the device.     

Conductance of MOS transistors in saturation

The output conductance of MOS transistors operating in the saturation region is studied theoretically and experimentally. A simple physical model is described which accounts for the modification of the electric field in the drain depletion region near the Si-SiO2interface, due to the presence of the gate electrode. The saturation conductance is shown on the basis of this model to be a sensitive function of the oxide thickness as well as the substrate impurity concentration. Good agreement is obtained between theory and experiment over a wide range of device parameters. The characteristics of lowly doped very-short-channel devices, which depart from this theory, are also discussed. The departure is shown to be due to a "punch-through"-type phenomenon.     

The future of bipolar power transistors

Silicon based bipolar power transistor (BPT) as a switching power transistor has been replaced by other superior power devices in the past two decades. This transformation is primarily due to the poor performance of the BPT. Among many problems of the BPT, low current gain and small safe operation area (SOA) caused by the second breakdown have been most detrimental to silicon BPT's fate. However, BPT performance based on newer materials, such as wide bandgap semiconductors, has not been previously studied. This paper systematically compares the BPTs based on wide bandgap semiconductor materials. Device figures-of-merit for conduction and switching losses are proposed. Comparison of the BPT based on total power loss is then provided. Based on this work, it is concluded that BPTs based on wide bandgap materials overcome the critical disadvantages of silicon BPTs, and are capable of switching power operation at several hundred kilohertz frequencies at very high current densities and voltages. Therefore, BPTs based on wide bandgap materials are still very attractive switching power devices for the future     

Thermionic saturation of diffusion currents in transistors

Macroscopic diffusion theory is not applicable to large percentage variations in carrier concentration over distances comparable to a scattering path length. It is plausible that the transport velocity for thermionic emission over a barrier of zero height constitutes a limit on the velocity of diffusive current flow at any point in a bulk semiconductor. Not incorporating a thermionic limit, the drift-diffusion current transport equation cannot account for thermionic emission. While a full remedy to these difficulties can only lie in a complete investigation of the relevant statistical physics, we present herein an empirical modification of the current transport equation based on the elementary concept of thermionic saturation of the diffusion current. The modified equation appears capable of accounting, at least in a crude way, for thermionically limited current flow, while permitting a unified treatment of diffusion-drift-thermionic transport. For narrow base transistors (w_b 1000 Å), much larger ratios of stored base charge to collector current are predicted than from diffusion theory. A thermionic emission-diffusion equation is derived for barrier injection in floating base transistors biased into punch-through. It is found for silicon structures that transport is diffusion-drift dominated at base impurity concentrations < 10¹⁷ cm⁻³, and thermionically controlled at higher base doping. A possible small reduction in the thermionic Richardson constant by a factor e is also predicted from the diffusion saturation equation.     

Double-interdigitated power transistors

The results of a comprehensive investigation concerning the implementation of the double-interdigitated (TIL) concept in TO-3-packaged triple-diffused power n-p-n^--n transistors are reported. The ease of manufacturing is accompanied by a relaxation of the tradeoff between the doping and width of the p-base and the main transistor parameters, which is still a crucial issue in conventionally interdigitated switches. The advantages exhibited by TIL devices when compared with identical conventional interdigitated transistors processed simultaneously are discussed     

The saturation characteristics of high-voltage transisitors

It is shown that the saturation characteristic of high-voltage NPvN transistors can only be explained by a lowering of the v-layer resistance due to conductivity modulation. A semi-quantitative model is developed which explains this modified saturation region. An experimental method of isolating the resistive portion of the external collector-base (CB) voltage is presented. The results verify that the CB junction may be forward-biased even when the characteristic seemingly indicates that the transistor is unsaturated. Data is also presented showing how variations in collector resistivity and thickness alter the saturation region.     

Electrical stress effect on RF power characteristics of SiGe hetero-junction bipolar transistors

In this paper, we investigate the electrical stress effects on both the high-frequency and RF power characteristics of Si/SiGe HBTs. Simultaneously applying a high collector current density and a high collector–base voltage upon the Si/SiGe HBTs, their hot carriers will induce device performance degradation. This stress condition is similar to the DC bias conditions of a current source RF power amplifier, and is termed as a “mixed-mode” stress. We find that not only the maximum oscillation frequency but also the output power performance of Si/SiGe HBTs are suffered by this electrical stress. In addition, the degradations of high-frequency and power characteristics are also worse under a constant base-current measurement than those under a constant collector-current measurement. Finally, we developed a commercial large-signal model to examine the degradations of the parasitic resistances and ideality factors of base and collector currents to explain the RF power and linearity degradations.     

测量大功率LDMOS晶体管特性的TRL校准方法研究

The impedance and output power measurements of LDMOS transistors are always a problem due to their low impedance and lead widths.An improved thru-reflect-line(TRL) calibration algorithm for measuring the characteristics of L-band high power LDMOS transistors is presented.According to the TRL algorithm,the individual two-port S parameters of each fixture half can be obtained.By de-embedding these S parameters of the test fixture,an accurate calibration can be made.The improved TRL calibration algorithm is successfully utilized to measure the characteristics of an L-band LDMOS transistor with a 90 mm gate width.The impedance of the transistor is obtained,and output power at 1 dB compression point can reach as much as 109.4 W at 1.2 GHz, achieving 1.2 W/mm power density.From the results,it is seen that the presented TRL calibration algorithm works well.     

Nonplanar power field-effect transistors

This paper reviews the criteria involved in the design of silicon power field-effect transistors. Particular emphasis is placed on recent nonplanar structures which will, in the near future, present a serious challenge to bipolar power transistors as linear amplifiers and high-speed switches.     

Thermal characterization of power transistors

The idealized concept of thermal resistance as applied to power transistors is discussed. This concept must be used with care because two of the basic assumptions made in applying the concept to these devices are not valid. Contrary to these assumptions, it is shown that 1) the junction temperature of a power transistor is never spatially uniform, and 2) no unique value of thermal resistance can be defined for all operating conditions. Also, various electrical methods for measuring the junction temperature (thermal resistance) of power transistors are discussed with the emphasis placed on the emitter-only switching measurement technique, which is the preferred standard method of measurement. In addition, the generation and meaning of forward-biased safe-operating-area (SOA) limits are discussed, and it is shown that because of the presence of current crowding and the associated hotspots, the specified SOA limits often permit devices to be operated at dangerously high junction temperatures. Electrical measurement methods capable of determining the peak junction temperature as well as determining the onset of current crowding are described, and it is shown how these methods might be used for the generation of improved SOA limits.     

Pattern design of power transistors

The distribution of the emitter current density along the emitter stripe in the comb structure has been analytically obtained by taking into account the junction temperature and the sheet resistance of the diffused base layer, From this result the optimum length of the emitter stripe has been obtained.     

Switching properties of epitaxial planar transistors operating in saturation

In an epitaxial transistor operating in saturation, charge is stored not only in the active and passive base regions but also in the region bounded between the collector junction and n-n⁺ interface. The saturation operation of a transistor switch is characterized by a single most fundamental parameter, the saturation time constant, which may be related to the intrinsic physical structure of the transistor.In this paper, an attempt has been made to correlate the saturation behaviour of an epitaxial planar transistor with its physical structure. The analysis takes into account the effects of n-n⁺ interface in the collector and the retarding-accelerating built in field for the minority carriers in the base, both of which so far have been subject to gross simplifications. The theoretical conclusions have been verified experimentally for some typical epitaxial planar transistors.     

The low process yield of some PNP power transistors

A study is presented of the symptoms of the devices in a slice of PNP power transistors with a poor yield. The failure modes over the slice are analysed. In specific areas the electrical characteristics and optical appearance of the devices were studied and failure statistics are presented. The low yield is ascribed to cracks in the phosphosilicate glass used for the base diffusion. The effect of these cracks is just visible in the optical and scanning electron microscope.     

An analysis of current saturation mechanism of junction field-effect transistors

A two-dimensional numerical analysis has been amde for junction field-effect transistors with small and large values of length-to-width ratio. Comparison of the results for different drain bias voltages shows the cause of the saturation of the drain current and the finite differential drain conductance in the saturation region. The effects of the geometry of the device and the field dependent mobility to the drain characteristics are clarified. Detailed pictures of the free carrier density distribution are presented, and the minimum channel width and the channel length are given for various bias conditions. A conduction path from the source to the drain with appreciable free carrier density has been found for bias conditions normally considered as pinched-off conditions. The drain characteristic with gate bias voltage is seen to be equivalent to that of a device with correspondingly smaller width and zero gate bias.     

An integrated circuit technique for saturation control of switching transistors

A limited-saturation device technique found to improve the absolute value, spread, and temperature dependence of storage times in integrated transistors, and compatible to existing integrated-circuit processing is described.