小型高功率脉冲功率放大器的研究

介绍了一种L波段的小型250 W高功率脉冲功率放大器模块.描述了该脉冲功放组件的设计过程和测试结果,讨论了直流偏置电路对脉冲上升沿和下降沿的影响.该脉冲功放在调制方式上采用了栅极调制和漏极调制相结合的方式,在机械结构设计上采用了新颖的双层腔体结构.该脉冲功放组件具有体积小,脉冲上升沿和下降沿好,稳定性高和功率大等特点.     

高功率微波发射机调制器和电源电路设计

为使高功率发射机的行波管正常工作,设计了其调制器和电源电路.用双稳态触发电路和脉冲变压器组合构成了调制器电路,输出上升沿和下降沿陡峭、时间关系与同步触发脉冲一致的调制脉冲,加到行波管的控制栅极;采用串联型开关电源电路,产生了行波管正常工作所需的低压电源;利用脉冲变换器和高压变压器产生了行波管的高压电源;此外还设计了控制...     

只使用少量高压元件的主驱动零交越检测器

本设计中的电路可生成一个交流电源的零交越脉冲,并提供电气绝缘。输出脉冲的下降沿出现在零交越点前约200μs。使用这个电路可以安全地停止一个可控硅栅极的触发,使之有时间正常地关断。只有当主电压约为0V时,电路才产生短脉冲,因此在230V、50Hz输入下只耗电200mW。     

栅极触发PDSOI CMOS闩锁效应研究

测试了不同静态栅极触发电压(输入电压)下诱发CMOS闩锁效应需要的电源电压和输出电压(即将闩锁时的输出电压),发现静态栅极触发CMOS闩锁效应存在触发电流限制和维持电压限制两种闩锁触发限制模式,并且此栅极触发电压.输出电压曲线是动态栅极触发CMOS闩锁效应敏感区域与非敏感区域的分界线.通过改变输出端负载电容,测试出了不同电源电压下CMOS闩锁效应需要的栅极触发电压临界下降沿,并拟合出了0 pF负载电容时的临界下降沿,最终得出了PDSOI CMOS电路存在的CMOS闩锁效应很难通过电学方法测试出来的结论.     

脉冲功率放大器调制技术分析

介绍了微波固态脉冲功率放大器的工作原理、脉冲调制的实现方法,分析了栅极调制与漏极调制的实现方式和优缺点,应用GaN功率芯片设计制作出了采用漏极调制方案的脉冲功率放大器,在设计过程中介绍了高压脉冲调制的实现方案,并给出了详细的电路原理图,对如何进一步提升脉冲功放的上升/下降沿进行了分析。     

大功率半导体激光器的高精度脉冲电源设计

为了满足大功率半导体激光器脉冲应用的实际需求, 针对单脉冲内电流平顶下降问题和重复性情况下电流稳定性降低的问题, 设计了一种多参数宽范围可调的高精度高稳定脉冲驱动电源。该电源以大功率场效应晶体管为核心, 通过现场可编程门阵列产生的高精度时序波形来完成单脉冲内的上升沿调控和栅极控制电压补偿, 通过微控制器结合电流采样的闭环控制方案实现重频运行下的电流高稳定输出。结果表明, 在输出电流100 A、脉冲宽度400 μs、重复频率1 kHz的最大功率输出驱动二极管负载时, 驱动电流上升沿过冲幅度小于0.5%、单脉冲内电流衰减小于0.2%、重复率脉冲不稳定度小于0.1%;在同样输出条件下驱动半导体激光器, 其在单脉冲内光功率过冲小于2%, 重复光脉冲不稳定度小于0.2%。该研究有助于提高脉冲电源脉冲电流稳定性, 对现有脉冲电源结构的改进具有一定的参考意义。     

一种窄边框的液晶显示面板设计

为了满足市场对LCD面板高分辨率、窄边框的需求,面板设计引入了玻璃上集成栅极驱动设计。本文对传统液晶显示面板栅极电路设计做了介绍,分析了集成栅极驱动电路技术在实现显示面板窄边框化时的优缺点。提出了一种新型栅极驱动电路,将空间控制转化为时间控制,使用一条栅极走线控制两行甚至多行像素。模拟分析结果表明:新型栅极驱动电路在关态下会产生2.5V的较小噪声;栅极信号的上升沿及下降沿的时间延迟总和只有3.5μs,可以实现像素节点的正常充放电并完成显示面板的正常显示。同时,本文提出的新型驱动电路可成倍减少显示面板边框栅极走线数量,减少栅极走线所占用的空间,实现高分辨率高解析度显示面板的窄边框化设计。     

GaN微波器件转移特性脉冲测试研究

对GaN微波器件的转移特性开展了脉冲测试研究.通过改变脉冲通道的数量、 静态工作点和脉冲宽度,获得了不同的脉冲测试条件下GaN晶体管的转移特性,并对不同测试条件下的测试结果进行了对比分析,获得了不同的脉冲测试条件对器件转移特性的影响.得到了GaN晶体管的转移特性对栅极脉冲比较敏感,漏极脉冲只是在栅极电压作用下起辅助作用,其对转移特性的影响程度主要依据栅极电压的影响而定的结论.     

无源核子料位计脉冲信号采集与时频域特征分析

通过示波器的远程功能,对无源核子料位计探头输出的负脉冲信号进行了采集。在时域内,对脉冲信号的下降沿时间、上升沿时间、下降沿电压变化率、上升沿电压变化率等指标进行了分析。结果表明,对于不同幅度的脉冲信号,上升沿时间和下降沿时间的离散性较小,上升沿和下降沿的电压变化率基本与脉冲幅度成正比,后续电路的压摆率指标要足够大,以不失真地响应这种变化。在频域内,对脉冲信号周期性延展后进行了快速离散傅里叶变换得到了其频谱。结果表明,脉冲信号的最高频率分量为1.296 MHz左右,后续处理电路的带宽要至少大于此频率值。为了对频域分析的结果进行验证,使用频谱数据对信号进行了重构,得到的近似波形与实测波形具有很好的吻合度。     

硅基半导体功放模块邻道干扰特性优化方法

基于硅基半导体器件的功放模块，由于器件本身物理结构特性引起的功放开关时间以及开关时上升沿、下降沿斜率的控制不当，导致调制邻道功率（Modulation of Adjacent Channel Power，ACP）以及瞬态切换邻道功率（Adjacent channel transient power，ACTP）较差，从而引起邻道干扰。针对硅基半导体器件功放模块在数字对讲机中的应用，创造性地提出了一种新的方法，对功放栅极偏置电路优化，从理论上分析和推导出功放开关时间以及开关时上升沿、下降沿斜率对ACP以及ACTP的影响，并在实际应用中通过适当调节对讲机功放模块栅极偏置电路电容以及串联电阻，实现了功放开关的上升沿以及下降沿斜率调节。实验结果表明:该方法在不影响功放输出功率以及效率的前提下，当信道间隔为12.5 kHz时，ACP-60 dBc，ACTP-50 dBc，有效改善了ACP、ACTP的性能，具有一定的实际意义和应用价值。     

The role of electron trap creation in enhanced hot-carrierdegradation during AC stress [n-channel MOSFET]

Enhanced AC degradation during gate voltage transients is shown to be related to neutral electron traps created at low gate voltages under conditions of hole injection and filled at high gate voltages under conditions of electron injection. During DC stress, where interface state damage dominates, electron trap damage is not seen because the created traps are neutral. In experiments where inductive ringing is eliminated, AC degradation rates are independent of the type of edge (falling versus rising) and independent of the rise/fall time     

门电路参数对互连线时延影响的仿真研究

文章推广了Wang氏RC梯形电路模型，对互连线阶跃响应上升时间与门电路参数的关系进行了仿真研究，给出了定量结果。门电路参数有输出电阻、输入电阻和电容。     

Characterization of P-channel power trench MOSFETs with polycrystalline silicon germanium gate electrode for faster switching

Electrical switching characteristics using polycrystalline silicon–germanium (poly-Si_l?xGe_x) gate for P-channel power trench MOSFETs was investigated. Switching time reduction of over 22% was observed when the boron-doped poly-Si gate was replaced with a similarly boron-doped poly-SiGe gate on the P-channel power MOSFETs. The fall time (T_f) on MOSFETs with poly-SiGe gate, was found to be ～11 ns lesser than the poly-Si gate MOSFET which is ～60% improvement in switching performance. However, all the switching improvement was observed during the fall times (T_f). The reason could be the higher series resistance in the switching test circuit masking any reduction in the rise times (T_r). Faster switching is achieved due to a lower gate resistance (R_g) offered by the poly-SiGe gate electrode as compared to poly-silicon (pSi) material. The pSi gate resistance was found to be 6.25 Ω compared to 3.75 Ω on the poly-SiGe gate measured on the same device. Lower gate resistance (R_g) also means less power is lost during switching thereby less heat is generated in the device. A very uniform boron doping profile was achieved with-in the pSiGe gate electrode, which is critical for uniform die turn on and better thermal response for the power trench MOSFET. pSiGe thin film optimization, properties and device characteristics are discussed in details in the following sections.     

Analog performance of double gate junctionless tunnel field effect transistor

For the first time, we investigate the analog performance of n-type double gate junctionless tunnel field effect transistor （DG-JLTFET） and the results are compared with the conventional n-type double gate tunnel field effect transistor （DG-TFET） counterpart. Using extensive device simulations, the two devices are compared with the following analog performance parameters, namely transconductance, output conductance, output resistance, intrinsic gain, total gate capacitance and unity gain frequency. From the device simulation results, DG-JLTFET is found to have significantly better analog performance as compared to DG-TFET.     

Hot carrier analysis in low-temperature poly-Si TFTs using picosecond emission microscope

We have investigated the degradation of n-channel thin-film transistors under dynamic stress. Degradation was examined for various pulse parameters such as rising time or frequency. A shortfall time led to a large degradation. This mechanism was analyzed by using a picosecond emission microscope and a device simulator to examine the transient current, experimentally and theoretically, respectively. We have successfully detected emission at the pulse fall edge for the first time. Emission intensity increased with the decrease in pulse fall time. By means of the transient device simulation, transient current corresponding to the gate pulse was obtained. From the comparison between internal field and transient current, hot carrier current generated in the pulse fall was detected for the first time. A reasonable agreement between the data obtained by the emission microscope and those obtained by the device simulator clearly indicates that hot electrons are the dominant cause of degradation under dynamic stress. On the basis of the comparison between experimental and theoretical results, we proposed a model which takes into consideration electron traps in poly-Si.     

Transferred-electron logic gates

A two-dimensional modeling technique is used to simulate GaAs transferred-electron devices operated as a logic gate (the TELD) and as a threshold gate. The simple logic gate has a good transfer characteristic but is shown sensitive to bias variations and operates with monostable output. For an input logic swing of 0.6 V and a fanout of 2, a propagation delay of 26 ps and gain of 1.25 is predicted. A bi-stable threshold gate shows a turn-on time of about 80 ps. An FET-triggered two-terminal transferred-electron device is calculated to have propagation delay of 27 ps with a gain of -1.2. Subsequent similar stages would require a noninverted output obtainable from a capacitive electrode on the TED. However, it is shown that additional anode load resistance is required to obtain a significant positive pulse output from such capacitive electrodes. The bias power requirement is estimated to be similar to the simple TELD gate.     

The influence of gate edge shape on the degradation in hot-carrierstressing of n-channel transistors

The hot-carrier properties of planar and graded gate structures (upturning of the gate edge in the gate overlap region) of n-MOS transistors were examined. It was found that the type of degradation suffered by each type of device depends on the shape of the gate edge. This is interpreted in terms of the degree of gate control of the gate over the region in which the damage takes place in the different devices. The nongraded gate (NGG) devices degrade chiefly by a V_t shift, whereas the graded gate (GG) devices show a pronounced transconductance decay, with practically no V_t shift. It is suggested that the damage is situated in the gate overlap region, and that the different degradations result from a weaker field control of the gate over the degraded region leading to a series resistance type of effect in the case of the GG structure. This is supported by two-dimensional simulations     

A physics-based frequency dispersion model of GaN MESFETs

A physics-based model for GaN MESFETs is developed to determine the frequency dispersion of output resistance and transconductance due to traps. The equivalent circuit parameters are obtained by considering the physical mechanisms for current collapse and the associated trap dynamics. Detrapping time extracted from drain-lag measurements are 1.55 and 58.42 s indicating trap levels at 0.69 and 0.79 eV, respectively. The dispersion frequency is in the range of megahertz at elevated temperature, where a typical GaN power device may operate, although at room temperature it may be few hertz. For a 1.5 /spl times/ 150 /spl mu/m GaN MESFET with drain and gate biases of 10 V and -1 V, respectively, 5% decrease in transconductance and 62% decrease in output resistance at radio frequencies (RFs) from their DC values are observed. The dispersion characteristics are found to be bias dependent. A significant decrease in transconductance is observed when the device operates in the region where detrapping is significant. As gate bias approaches toward cutoff, the difference between output resistance at dc and that at RF increases. For drain and gate biases of 10 and -5 V, output resistance decreases from 60.2 k/spl Omega/ at dc to 7.5 k/spl Omega/ at RF for a 1.5 /spl mu/m /spl times/ 150 GaN MESFET.     

Effect of silicon-gate resistance on the frequency response of MOS transistors

A polycrystalline silicon gate has finite sheet resistivity, typically in the range of tens of ohms per square. The resulting gate resistance and the gate capacitance form a distributed RC network. The gate voltages appearing along this distributed network, hence, the summation drain current, is delayed from the input voltage applied to the contact pad(s). The delay of the distributed RC network is analyzed for both small and large signals. The analysis shows that when the RC time constant of the gate is comparable to the period of the signal, the frequency response is degraded. This time constant varies as the square of the gate width. For a gate width in the fractional millimeter range (typical of output MOS transistors in an integrated circuit), the time constant may be in the 100-ns range; for gate width in the 10-µ range, in the subnanosecond range.