A modelling language for cooperative plans in highly dynamic domains

Cooperative behaviour is one of the challenges most pronounced in the RoboCup Middle Size League. Especially the dynamic nature of the domain, which calls for swift adaptation by each robot and the team as a whole, is a distinctive property of the league. The ability to establish highly responsive teamwork while facing unreliable communication and sensory noise is a key to successful soccer teams. Moreover, modelling such responsive, cooperative behaviour is difficult. In this work, we specify a novel model for cooperative behaviour geared towards highly dynamic domains, focussing on the language syntax and semantics. In our approach, agents estimate each other’s decision and correct these estimations once they receive contradictory information. We provide a comprehensive approach for agent teamwork featuring intuitive modelling capabilities for multi-agent activities, abstractions over activities and agents, and a clear operational semantics. Moreover, we briefly present a graphical modeling tool for cooperative strategies, which is based directly on the theory laid out, together with a practical framework for executing said strategies. We show experimentally the responsiveness and coherence of the resulting team play.     

网络支付协议的形式化安全需求及验证逻辑

从整个网络支付协议的安全角度出发，提出网络支付协议的多层安全需求模型，包括以认证和密钥分配为基础的基层需求、网络支付协议固有的中层需求(包括保密性、原子性、公平性、完整性、匿名性、不可否认性、可追究性等)、以及面向具体应用的高层需求。基于一阶逻辑和时序逻辑，提出一种适合描述网络支付协议的形式化安全需求的逻辑，描述了该逻辑的语法结构和推理规则，并用该安全需求逻辑对网络支付协议的多层安全需求进行了形式化描述。最后，以SET协议为例进行需求验证。     

A BiCMOS wired-OR logic

This paper proposes a BiCMOS wired-OR logic for high-speed multiple input logic gates. The logic utilizes the bipolar wired-OR to circumvent the use of a series connection of MOS transistors. The BiCMOS wired-OR logic was found to be the fastest compared with such conventional gates as CMOS NOR, BiCMOS multiemitter logic and CMOS wired-NOR logic, when the number of inputs was more than four and the supply voltage was 3.3 V. The BiCMOS wired-OR logic was also determined to be the fastest of the four when the fan-out number was below 20 and the number of inputs was eight. In addition, the speed was more than twice as faster when the fan-out number was less than 10. The BiCMOS wired-OR logic was applied to a 64-b 2-stage carry look-ahead adder, and was fabricated with a 0.5-μm BiCMOS process technology. A critical path delay time of 3.1 ns from an input to a sum output was obtained at the supply voltage of 3.3 V. This is 35% faster than that of conventional BiCMOS adders     

A charge-transfer-device logic cell

A logic scheme capable of performing AND-OR logic functions using charge-transfer devices is presented in this paper. Applications of the logic cell are discussed. A half-adder, a ‘flip-flop’, a majority logic gate, an analog-to-digital and a digital-to-analog converter are obtained by extending or modifying the basic scheme. An integrated MOS BBD realization of the AND-OR logic cell is described in detail. Experimental results are presented and shown to be in agreement with theoretical calculations.     

A bibliography of accelerated test plans

This article provides a current bibliography of 159 references on statistical plans for accelerated tests. It will aid practitioners in selecting plans, and will stimulate researchers to develop needed plans & software.     

A fuzzy logic inference processor

A mixed analog-digital fuzzy logic inference engine chip fabricated in an 0.8 μm CMOS process is described. Interface to the processor behaves like a static RAM, and computation of the fuzzy logic inference is performed between memory locations in parallel by an array of analog charge-domain circuits. Eight inputs and four outputs are provided, and up to 32 rules may be programmed into the chip. The results of the inference over all rules, including a center-of-mass defuzzification, may be computed in 2 μs     

A new current-routing logic counter

The integrated synchronous 2³-counter described below uses binary current-routing logic stages with a minimum number of components, crossings and collector islands. Maximum toggle frequency is 60 MHz at 12 mW per stage. With few interconnections between identical chips a synchronous 2⁹-counter can be realized.     

一种模糊时态描述逻辑

针对现实生活中信息的时间性和模糊性,在模糊描述逻辑和时态逻辑的基础上,提出了一种模糊时态描述逻辑FTDL,并给出了其语法和语义的相关说明。与模糊描述逻辑FALC相比,FTDL的提出为语义Web服务的建模和推理提供了一种有效的途径。     

A new RTD-FET logic family

We describe a new family of clocked logic gates based on the resonant-tunneling diode (RTD). Pairs of RTDs form storage latches, and these are connected by networks consisting of field-effect transistors (FETs), saturated resistors, and RTDs. The design, operation, and expected performance of both a shift register and a matched filter using this logic are discussed. Simulations show that the RTD circuits can achieve higher performance in terms of speed and power in many signal processing applications. Compared to circuits using III-V FETs alone, the RTD circuits are expected to run nearly twice as fast at the same power or at the same speed with reduced power. Compared to circuits using Lincoln Laboratory's fully depleted silicon-on-insulator CMOS, implementation using state-of-the-art RTDs should operate five times faster when both technologies follow the CMOS design rules     

A logic nanotechnology featuring strained-silicon

Strained-silicon (Si) is incorporated into a leading edge 90-nm logic technology . Strained-Si increases saturated n-type and p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) drive currents by 10 and 25%, respectively. The process flow consists of selective epitaxial Si/sub 1-x/Ge/sub x/ in the source/drain regions to create longitudinal uniaxial compressive strain in the p-type MOSFET. A tensile Si nitride-capping layer is used to introduce tensile uniaxial strain into the n-type MOSFET and enhance electron mobility. Unlike past strained-Si work: 1) the amount of strain for the n-type and p-type MOSFET can be controlled independently on the same wafer and 2) the hole mobility enhancement in this letter is present at large vertical electric fields, thus, making this flow useful for nanoscale transistors in advanced logic technologies.     

A spatially and temporally correlated fading model for arrayantenna applications

In this paper, a new channel model is proposed. Since it is spatially and temporally correlated simultaneously, this new model is well consistent with the real environment of array antenna applications. The widely used sum of scattered waves and the measurement-based model have a common drawback of imperfect statistical properties, reducing the reliability of simulation results. The new model (spatially and temporally correlated fading model [STCFM]) is derived rigorously in the spatiotemporal domain so that it can provide high accuracy for the evaluation of the array antenna system. Simulation results show that direction of arrival (DOA) and angle of spread (AOS) are well defined in STCFM, BPSK with two-branch maximal ratio combining and DBPSK with differential detection are considered to verify the spatial and temporal correlation robustness of the new model, respectively. As is shown, the simulation results agree well with the theory     

Threshold logic functions in programmable logic arrays

Methods of implementing threshold-logic functions in programmable logic arrays are described. Use is made of the properties of the threshold functions to achieve a more efficient implementation, in terms of silicon area required, than a previously described cellular array.     

A four-variable programmable universal logic module using digital summation threshold logic gates

Combining the concepts of programmable logic arrays (PLAs) and conventional universal logic modules (ULMs) a new type of programmable ULM for four variables has been proposed. The realization is based on the digital summation threshold logic (DSTL) gates, a cellular array for realizing threshold logic functions.     

A heuristic for decomposition in multilevel logic optimization

A heuristic for finding common subexpressions of given Boolean functions based on Shannon-type factoring is proposed. This heuristic limits the search space considerably by applying a top-down approach in which synthesis of a Boolean network flows from the primary outputs to the primary inputs. The common subexpressions and their complements in N variables are extracted before common subexpressions and their complements in (N-1) variables. This decomposition of the network depends on a permutation of Boolean variables and has a polynomial complexity for restricted extraction of complements. A multilevel logic optimization system, MULTI, has been implemented using this heuristic. Good results on several benchmark circuits show its effectiveness     

A proposed distributed Josephson logic circuit

A new Josephson logic circuit is proposed with spatially distributed inputs and outputs. It is uniquely suited to picosecond functional logic arrays, memory peripheral circuits, and other applications requiring large distributed fan-in.     

一种改进SVO逻辑的新方法

安全协议的形式化验证能有效检验安全协议的安全性,BAN类逻辑的发展极大的促进了这一领域的研究,而SVO逻辑是BAN类逻辑的佼佼者.本文通过增加和改进SVO逻辑的推理规则以及公理,提出了一种改进SVO逻辑的新方法,使其可以更好的分析认证协议.本文运用改进SVO逻辑对Needham-Schroeder认证协议进行形式化分析,发现改进的SVO逻辑能证明Needham-Schroeder认证协议能够达到预期目标.     

A successive approximation logic frequency-to-code converter

A new frequency-to-code converter (fDC) circuit in which an input frequency fiis processed by successive approximation logic (SAL) to generate a proportional digital number is described in this letter. Several ingenious subcircuits plus the conventional sequencer clocked by the input hertz constitute the SAL fDC. Conversion time is equal to nTiwhere n is the number of bits in the output digital word and Tiis the period of the input hertz.