基于Rebeca模型的硬件设计形式化验证

形式化验证是对传统验证方法的补充,是数字电路验证的一条有效途径,对于并发系统,行为建模是一种非常合适的建模方法;Rebeca是由Sirjani和Movaghar提出的一种基于行为的建模语言,支持形式化,一方面,Rebeca是一种类Java的语言,软件工程师很容易使用,另一方面,它是一种支持形式化验证及其相关理论的模型语言,可以为不精通于形式化方法的开发人员和研究人员提供方便的验证过程;在深入研究Rebeca的基础上,采用Rebeca对硬件设计进行建模,然后Modere形式化验证工具对AES密码芯片进行形式化验证。     

Formal Verification of Websites

In this paper, a model for websites is presented. The model is well-suited for the formal verification of dynamic as well as static properties of the system. A website is defined as a collection of web pages which are semantically connected in some way. External web pages (which are related pages not belonging to the website) are treated as the environment of the system. We also present the logic which is used to specify properties of websites, and illustrate the kinds of properties that can be specified and verified by using a model-checking tool on the system. In this setting, we discuss some interesting properties which often need to be checked when designing websites. We have encoded the model using the specification language Maude which allows us to use the Maude model-checking tool.     

一种基于状态机的形式化验证技术

状态机作为一种描述实体间交互或者单个实体行为的建模图,它具有丰富的直观图形化的符号。在许多模型的设计阶段都采用它来建模。但是因为缺乏精确完整的语义定义,给它的形式化验证带来困难。本文给出一种形式化操作语义,并概述基于形式化规则的验证技术。     

一种系统安全性的形式化验证方法

随着计算机系统应用的深入和广泛,系统安全性越来越成为人们关注的焦点,形式化模型检验是解决系统特性验证问题的一种有效途径,用有限自动机表示系统的设计和实现,用计算树逻辑CTL(ComputationalTreeLogic)公式表示系统的安全特性,探讨了系统安全性形式化验证的方法。     

A Design Phase Directed Formal Verification Process

The presence of an effective verification process at an earlier phase of the system development lifecycle will have a greater impact on productivity and product quality than a verification process at a later phase. The usual verification process at the later coding phases involves some form of testing. As high-level design cannot be tested in the same way as code, an option at that phase is some kind of formal verification. A process of verification is presented for the high-level design phase of an operating system development, where both rigorous and formal verification are used, and the rigorous directs the formal. The methodology is based on temporal logic. Formal proofs are manageable on an in-house theorem prover.     

一种基于状态机的形式化验证技术

状态机作为一种描述实体间交互或者单个实体行为的建模图,它具有丰富的直观图形化的符号。在许多模型的设计阶段都采用它来建模。但是因为缺乏精确完整的语义定义,给它的形式化验证带来困难。本文给出一种形式化操作语义,并概述基于形式化规则的验证技术。     

DMA控制器的一种硬件验证方法

在微处理器或SOC芯片设计过程中,DMA控制器的硬件仿真验证是难以解决的问题之一,因为DMA控制器与包括微处理器核和内存控制器在内的几乎所有部件都有数据通信,如将所有部件集成后进行仿真测试,则一旦发现错误后,定位错误会非常困难.本文为此提出了一种简化测试模型和验证方法,可以有效解决上述问题.     

一种新的安全协议形式化验证方法

形式化方法能有效检验安全协议的安全性,BAN类逻辑的发展极大地促进了这一领域的研究,但是现有的BAN类逻辑仍然存在许多问题．在分析现有BAN类逻辑的基础上,提出一种新的安全协议形式化验证方法,实现现有BAN类逻辑的验证功能,并使安全协议验证工作简单可行,便于实现机器自动验证．为安全协议形式化验证提供了一种新的途径．     

Statecharts的形式化验证研究

给出了Statecharts的抽象语法描述,以及Statecharts各个构成元素的语义,包括状态、迁移、事件和条件、表达式、动作和当前状态格局的语义函数等,并给出Statecharts一步的操作语义.然后在此基础上把一个图形化的语言转换为文本的方式来描述,并对Statecharts进行形式化分析及验证.     

Dynamic and Formal Verification of Embedded Systems: A Comparative Survey

Embedded Systems, by their nature, constitute a meeting point for communities with extremely different background. In particular, the high demands for quality and reliability for embedded systems have led to complementary quality assurance efforts: hardware engineers have developed techniques for dynamic verification in terms of co-simulation, which, in particular, addresses the different nature of hardware and software components. Thus these techniques are tailored for the transactional level, which comprises dedicated models for the hardware and the software parts. On the other hand, there is a bulk of work on formal verification techniques, which typically address higher levels of abstraction. These techniques are exhaustive in the sense that they cover all the infinite possible paths of their models, however at the price of neglecting many of the low-level aspects treated by co-simulation. It is the goal of this paper to increase the mutual understanding between these communities and to animate research at this exciting borderline.     

混成系统形式化验证

混成系统是实时嵌入式系统的一种重要子类,其行为中广泛存在离散控制逻辑跳转与连续实时行为交织混杂的情况,因此行为复杂,难以掌握与控制.由于此类系统广泛出现在工控、国防、交通等与国计民生密切相关的安全攸关的领域,因此,如何对相关系统进行有效的分析与理解,从而保障系统安全运营,是一项具有重要意义的工作.常规的系统安全性分析手段,如测试、仿真等仅能在一定输入的情况下运行系统来观测系统行为,无法穷尽地检测复杂混成系统在所有可能输入下的行为,因此并不足以保证系统的安全性.区别于测试等方法,形式化方法通过求解系统模型状态取值范围等方法来确认系统模型中一定不会出现相关错误.因此,其对于保障安全攸关混成系统的安全性具有十分重要的意义.形式化方法由形式化规约与形式化验证两个方面构成.因此从以上两个角度分别对形式化规约方向上现有混成系统建模语言、关注性质以及形式化验证方向的混成系统模型检验、定理证明的现有主要技术与方法进行了综述性的回顾与总结.在此基础上,针对现阶段实时嵌入式系统复杂化、网络化的特性,对混成系统形式化验证的重要关注问题与研究方向进行了探索与讨论.     

Polynomial Formal Verification of Multipliers

Not long ago, completely automatical formal verification of multipliers was not feasible, even for small input word sizes. However, with Multiplicative Binary Moment Diagrams (*BMD), which is a new data structure for representing arithmetic functions over Boolean variables, methods were proposed by which verification of multipliers with input word sizes of up to 256 Bits is now feasible. Unfortunately, only experimental data has been provided for these verification methods until now.In this paper, we give a formal proof that logic verification with *BMDs is polynomially bounded in both, space and time, when applied to the class of Wallace-tree like multipliers. Using this knowledge online detection of design errors becomes feasible during a verification run.     

Kaman协议的形式化验证

Kaman协议是移动Ad Hoc网络安全认证机制,然而,协议设计者未对该协议的安全性作严格的形式化分析。协议复合逻辑PCL是验证协议安全属性的形式化方法,PCL逻辑能够简化协议安全分析过程。本文在协议复合逻辑PCL中描述Kaman协议并分析Kaman协议的安全属性,证明Kaman协议能够实现其安全目标。     

面向特征编程范式的形式化验证技术研究综述

以面向对象编程范式开发软件经常面临类(Class)与用户需求项无法直接对应的尴尬,面向特征编程范式(FOP)旨在解决这个问题,因此具有重要意义。本文首先简介了FOP编程范式的思想,它与面向方面编程范式的异同,以及它给相应的形式化验证技术带来的挑战;然后综述了现有的FOP形式化验证方法以及我们所做的相关工作,比较了它们的优缺点;最后讨论了FOP形式化验证今后可能的研究方向。     

事务级形式验证技术及8051验证模型

提出一种基于事务的用于电路系统的形式验证方法(TBFV)．应用该方法，验证工程师可以在行为级对系统进行验证，无需了解设计的细节．为了对该方法进行示范，验证了8051的RTL级实现，并给出了8051指令集的TBFV模型．     

Web服务的形式化验证

将Web服务组合建模为多智能体系统,采用时态知识逻辑模型检测工具MCTK刻画贷款协议Web服务实例,并验证相关的时态知识规范。在同一实验环境下,采用另一种时态知识逻辑模型检测工具MCMAS进行建模,并验证该实例。实验结果表明,基于MCTK的Web服务模型检测方法比基于MCMAS的方法更有效。     

Formal Verification Successes at Motorola

Formal tools are either too labor intensive or are completely impractical for industrial-size problems. This paper describes two formal verification tools used within Motorola, Versys2 and CBV, that challenge this assertion. The two tools are being used in current design verification flows and have shown that it is possible to seamlessly integrate formal tools into existing design flows.