Gate dielectric degradation in CMOS inverters

To study the gate oxide degradation under stress conditions closer to the actual operation of devices in circuits, in this work, CMOS inverters have been stressed using DC and pulsed signals at the input. Uniform and non-uniform Fowler-Nordheim and Channel Hot Carrier stresses have been identified as those governing the oxide degradation, depending on the input signal, and modifying the electrical response of the device. In particular, a decrease of the saturation current is observed, which depends on the transistor type (NMOS or PMOS), input signal, and stress time. The results show larger degradations in the NMOS when the input frequency is increased, which has been attributed to the Channel Hot Carriers contribution during the output state transitions in the inverter. Also the impact of the different stresses on the circuit output is analyzed and related to the degradation of the devices. A shift in the inverter voltage transfer characteristic has been observed, whose direction depends on the degradation that the transistors have suffered, being more important at elevated frequencies.     

一种二维SOI CMOS门级瞬态数值模型

本文给出一种SOI CMOS门级二维集成数值模型.该模型直接将端点电流、端点电压与内部载流子的输运过程联系在一起,可准确地模拟亚微米SOI CMOS反相器的瞬态特性、并给出清晰的内部物理图象.模型采用一种新的数值方法──交替方向法,将二维瞬态方程转化为两个相邻时间层的一维问题解,并提出动态二步迭代法以确保瞬态模拟的快速、稳定收敛.本文简要讨论了SOI CMOS器件中少子的累积对电路瞬态特性的影响.本模型还可用于计算辐射对SOI器件的影响以及研究漏电机理,它为高可靠亚微米SOI器件及电路的研制提供了方便的CAD工具.     

Relating CMOS inverter lifetime to DC hot-carrier lifetime ofNMOSFETs

The authors report that comparison with measured 75-MHz CMOS ring-oscillator speed degradation suggests that quasi-static circuit aging simulations using DC stress data do not underestimate circuit degradation. Roughly speaking, 10% degradation in NMOSFET linear current results in only about 1.3% increase in CMOS inverter propagation delay. This 10% current degradation occurs in an inverter-based circuit over a time that is about six times the MOSFET DC lifetime at maximum I_sub and about 30 times the DC lifetime at maximum I_sub³/I_ds²     

CMOS反相器低频噪声模型及可靠性表征研究

为了表征CMOS反相器的可靠性,从其负载电流和输出电压的特性入手,详细推导了一种基于载流子波动理论的低频噪声模型,并由实验数据验证了模型的准确性.由实验结果可知,负载电流功率谱密度随频率的增加而减小,遵循1/f噪声的变化规律;得到了负载电流归一化噪声功率谱密度与器件尺寸的关系.通过深入研究1/f 噪声与界面态陷阱密度的关系,验证了1/f噪声可用于表征CMOS反相器的可靠性,证明了噪声幅值越大,器件可靠性越差,失效率显著增大,为评价CMOS反相器的靠性提供了一种可行及有效的方法.     

Hot carrier degradation modeling of short-channel n-FinFETs suitable for circuit simulators

The hot-carrier (HC) degradation of short-channel n-FinFETs is investigated. The experiments indicate that interface trap generation over the entire channel length, which is enhanced near the drain region, is the main degradation mechanism. The relation of the hot-carrier degradation with stress time, channel length, fin width and bias stress voltages at the drain and gate electrodes is presented. A HC degradation compact model is proposed, which is experimentally verified. The good accuracy of the degradation model makes it suitable for implementation in circuit simulation tools. The impact of the hot-carriers on a CMOS inverter is simulated using HSPICE.     

Investigation of the degradation mechanisms of InP/InGaAs DHBT under bias stress conditions to achieve electrical aging model for circuit design

The reliability of InP/InGaAs DHBT under high collector current densities and low junction temperatures is analyzed and modeled. From the Gummel characteristics, we observe several types of device degradation, resulting from the long term changes of base and collector current in both lower and higher base–emitter voltage ranges which impacts the reduction of DC current gain. In this paper, we investigate the underlying physical mechanism of base and collector current degradation with the help of TCAD device simulation. We chose the HICUM model level2 for the modeling purpose to evaluate the drift of model parameters according to stress time. The evolution of the model parameters is described with suitable equations to achieve a physics based compact electrical aging model. The aging laws and the parameter evolution equations with stress time are implemented in compact electrical aging model which allows us to simulate the impact of device failure mechanisms on the circuit in operating conditions.     

Hot-carrier-reliability design guidelines for CMOS logic circuits

Long-term ring-oscillator hot-carrier degradation data and simulation results are compared to demonstrate that a circuit reliability simulator BERT can predict CMOS digital circuit speed degradation from transistor DC stress data. We present generalized hot-carrier-reliability design rules that translate device-level degradation rate to CMOS circuit lifetime. The design rules, which consist of lifetime and speed degradation factors, can roughly predict CMOS circuit degradation during the initial design, and can help reliability engineers to quickly estimate the overall product hot-carrier reliability. The NMOSFET and PMOSFET lifetime factors were found to obey 4/ft_rise and 10/ft_fall respectively. Typically, the NMOSFET and PMOSFET speed degradation factors are 1/4 and 1/2, respectively, with saturation region drain current as the monitor, while for a 100 MHz operating frequency and for an input rise time of 0.35 ns, the NMOSFET and PMOSFET time factors are 120 and 300, respectively     

Hot-carrier-reliability design rules for translating devicedegradation to CMOS digital circuit degradation

Long term ring-oscillator hot-carrier degradation data and simulation results are compared to demonstrate that a circuit reliability simulator BERT can predict CMOS digital circuit speed degradation from transistor DC stress data. Initial fast degradation is noted and attributed to the “zero crossing” effect caused by PMOSFET current enhancement. Saturation drain current, measured at V_gs=V_ds=Vdd/2, is a better monitor for CMOS circuit hot-carrier reliability. We present generalized hot-carrier-reliability design rules, lifetime and speed factors, that translate DC device lifetime to CMOS digital circuit lifetime. The design rules can roughly predict CMOS circuit degradation during the initial design and can aid reliability engineers to quickly estimate the overall product hot-carrier reliability. The NMOSFET and PMOSFET lifetime factors are found to obey 4/ft_rise and 10/ft_fall, respectively. Typically, the NMOSFET and PMOSFET speed degradation factors are 1/4 and 1/2, respectively, with saturation region drain current as the monitor while, for a 100 MHz operating frequency and for an input rise time of 0.35 ns, the NMOSFET and PMOSFET lifetime factors are 120 and 300, respectively     

An analytic potential model for symmetric and asymmetric DG MOSFETs

This paper presents an analytic potential model for long-channel symmetric and asymmetric double-gate (DG) MOSFETs. The model is derived rigorously from the exact solution to Poisson's and current continuity equation without the charge-sheet approximation. By preserving the proper physics, volume inversion in the subthreshold region is well accounted for in the model. The resulting analytic expressions of the drain-current, terminal charges, and capacitances for long-channel DG MOSFETs are continuous in all operation regions, i.e., linear, saturation, and subthreshold, making it suitable for compact modeling. As no fitting parameters are invoked throughout the derivation, the model is physical and predictive. All parameter formulas are validated by two-dimensional numerical simulations with excellent agreement. The model has been implemented in Simulation Program with Integrated Circuit Emphasis version 3 (SPICE3), and the feasibility is demonstrated by the transient analysis of sample CMOS circuits.     

Degradation Characteristics of n- and p-Channel Polycrystalline-Silicon TFTs Under CMOS Inverter Operation

The degradation characteristics of n- and p-channel polysilicon thin-film transistors (TFTs) under circuit operation were investigated by using CMOS inverter circuits consisting of n-channel TFTs with a lightly doped drain (LDD) structure and p-channel TFTs with a single-drain (SD) structure. A new test element made it possible to separately evaluate the degradation characteristics of each type of TFT during CMOS inverter operation. In regard to n-channel LDD TFTs, the device degradation is mainly caused by accumulated dc stress under the condition that the gate voltage is near the threshold voltage and the high drain voltage, i.e., the drain-avalanche hot-carrier (DAHC) stress condition. In p-channel SD TFTs, the device degradation is caused by the mutual interaction between DAHC stress and negative-bias-temperature (NBT) stress. Hole injection due to NBT stress is accelerated by DAHC-stress-induced trapped electrons under inverter-circuit operation. The effect is thus enhanced not only by the increase in the number of hole injections but also by the increase in the number of electron injections. It was found that the device characteristics of p-channel TFTs are more rapidly degraded as the rising time of the input pulse becomes shorter. This degradation is caused by the transient increase in the number of hot electrons, which are generated when holes are emitted from the trap states when the p-channel TFTs are turned off.      

基于40nm CMOS工艺电路的NBTI退化表征方法

负偏压温度不稳定性(NBTI)退化是制约纳米级集成电路性能及寿命的主导因素之一,基于40 nm CMOS工艺对NBTI模型、模型提参及可靠性仿真展开研究。首先对不同应力条件下PMOS晶体管NBTI退化特性进行测试、建模及模型参数提取,然后建立了基于NBTI效应的VerilogA等效受控电压源,并嵌入Spectre^TM仿真库中,并将此受控电压源引入反相器及环形振荡器模块电路中进行可靠性仿真分析,可有效反映NBTI退化对电路性能的影响。提出了一套完整可行的电路NBTI可靠性预测方法,包括NBTI模型、模型参数提取、VerilogA可靠性模型描述以及电路级可靠性仿真分析,可为纳米级高性能、高可靠性集成电路设计提供有效参考。     

Hot-carrier degradation of p-MOSFET's under analog operation

The hot-carrier degradation of p-MOSFET's is investigated from the viewpoint of analog operation. We apply sensitive measurement methods to determine drain current, drain conductance, and transconductance in the saturation regime besides the commonly investigated parameters in the linear regime of operation. Those investigations are performed for different gate lengths in order to allow comparisons between the shortest channels used for digital and the long channels usually used for analog operation, it is found that the drain conductance important in many analog applications, does not show a channel length dependence for gate lengths above 1.5 times the minimum gate length. The stress time dependencies are determined predominantly finding logarithmic behaviors. These findings are explained by a model which highlights the importance of the lengths of the regions of damage and carrier velocity saturation. Moreover, the dependencies of the different characterization parameters on stress time, channel length and voltages of operation are evaluated. Finally, methods are given for extrapolation of degradation of analog parameters to operating conditions for reliability assurance     

Switching characteristics of scaled CMOS circuits at 77 K

Performance enhancement of CMOS inverters at room and liquid-nitrogen temperatures are studied. The extent of delay improvement at low temperature is limited by the velocity saturation effect, as the channel lengths are decreased and/or the supply voltage increased. An analytical delay model taking into account velocity saturation is developed that accurately predicts the measured delay of CMOS inverter chains with drawn channel lengths down to 0.5 µm, Compared are the relative merits of CMOS devices operating at 77 K and those scaled for room-temperature operations.     

一种抗热载流子退化效应的新型CMOS电路结构

本文在分析MOSFET衬底电流原理的基础上,提出了一种新型抗热载流子退化效应的CMOS数字电路结构.即通过在受热载流子退化效应较严重的NMOSFET漏极串联一肖特基二级管,来减小其所受电应力.经SPICE及电路可靠性模拟软件BERT2.0对倒相器的模拟结果表明:该结构使衬底电流降低约50%,器件的热载流子退化效应明显改善而不会增加电路延迟;且该电路结构中肖特基二级管可在NMOSFET漏极直接制作肖特基金半接触来方便地实现,工艺简明可行又无须增加芯片面积.     

Degradation of static and dynamic behavior of CMOS inverters during constant and pulsed voltage stress

We study the degradation of CMOS inverters under DC and pulsed stress conditions before the occurrence of the gate oxide breakdown. Our results show an overall speed reduction, caused by the transistor drain current drop, and a leftward shift of the inverter voltage transfer characteristics, due to a larger degradation of the PMOSFET as compared to the NMOSFET. We attribute this behavior to the build-up of defects/trapped charge featuring a different kinetics in P- and N-type MOSFETs.     

Analytical transient response and propagation delay evaluation ofthe CMOS inverter for short-channel devices

In this paper an accurate, analytical model for the evaluation of the CMOS inverter transient response and propagation delay for short-channel devices is presented. An exhaustive analysis of the inverter operation is provided which results in accurate expressions of the output response to an input ramp. Most of the factors which influence the inverter operation are taken into account. The α-power law MOS model, which considers the carriers' velocity saturation effects of short-channel devices, is used. The final results are in excellent agreement with SPICE simulations     

基于速度饱和的CMOS倒相器延迟模型

提出了一个新的小尺寸CMOS倒相器延迟模型,它考虑了速度饱和效应以及非阶梯的输入信号对延迟的影响并给出了倒相器快输入响应与慢输入响应的判据,模型计算结果与SPICEBSIM1模型的模拟结果吻合得很好.     

Si-SiGe材料三维CMOS集成电路技术研究

根据SiGe材料的物理特性,提出了一种新有源层材料的三维CMOS集成电路.该三维CMOS集成电路前序有源层仍采用Si材料,制作nMOS器件;后序有源层则采用SiGe材料,以制作pMOS器件.这样,电路的本征性能将由Si nMOS决定.使用MEDICI软件对Si-SiGe材料三维CMOS器件及Si-SiGe三维CMOS反相器的电学特性分别进行了模拟分析.模拟结果表明,与Si-Si三维CMOS结构相比,文中提出的Si-SiGe材料三维CMOS集成电路结构具有明显的速度优势.     

Delay and Power Expressions for a CMOS Inverter Driving a Resistive-Capacitive Load

A delay and power model of a CMOS inverter driving aresistive-capacitive load is presented. The model is derivedfrom Sakurais alpha-power law and exhibits good accuracy. Themodel can be used to design and analyze those CMOS invertersthat drive a large RC load when considering bothspeed and power. Expressions are provided for estimating thepropagation delay and transition time which exhibit less than27% discrepancy from SPICE for a wide variety of RCloads. Expressions are also provided for modeling the short-circuitpower dissipation of a CMOS inverter driving a resistive-capacitiveinterconnect line which are accurate to within 15% of SPICEfor most practical loads.