A simple analytical model for hot-carrier MOSFETs

Several second-order effects such as mobility degradation, carrier velocity saturation, and channel-length modulation are included in the model. The source-drain series resistances are accounted for, and a simple formula to calculate the output conductance without creating a discontinuity at the transition from the linear to the saturation region is proposed. The accuracy of the model is confirmed by comparing its theoretical predictions with the experimental data available in the literature. The model is used to estimate the lateral electric field at the drain to which hot-carrier effects are sensitive     

An analytical hot-carrier induced degradation model in polysilicon TFTs

Hot-carrier effects in n-channel polysilicon thin-film transistors (TFTs), with channel width W=10 /spl mu/m and length L=10 /spl mu/m, are investigated. An analytical model predicting the post-stress performance is presented, by treating the channel of the stressed device as a series combination of a damaged region extended over a length /spl Delta/L beside the drain and a region of length L-/spl Delta/L having the properties of the unstressed device. The apparent channel mobility is derived considering that the mobility of the damaged region is described with the mobility of amorphous Si TFTs, whereas the mobility of the undamaged region is described with the mobility of the virgin device. From the evolution of the static characteristics during stress, the properties of the damaged region with stress time are investigated.     

A physical-based analytical turn-on model of polysilicon thin-filmtransistors for circuit simulation

A physical-based analytical current model of poly-Si thin film transistors (TFT's) for circuit simulation is presented. The model includes the barrier potential at grain boundaries, drain induced grain barrier lowering (DIGBL), temperature dependence, and the kink effect. The basic equation in the model has an analytic form for implementation in circuit simulators. The model has simple relationships between model parameters and device or material parameters. In addition to the current model, a capacitance model based on the current model is presented. Comparisons between the model and measured results show excellent agreement over wide ranges of operating voltages and for devices with different channel lengths     

A model for AC hot-carrier degradation in n-channel MOSFETs

A recently developed model for AC hot-carrier lifetimes is shown to be valid for typical and worst-case stress waveforms found in CMOS circuits. Three hot-carrier damage mechanisms are incorporated into the model: interface states created at low and medium gate voltages, oxide electron traps created at low gate voltages, and oxide electron traps created at high gate voltages. It is shown that the quasi-static contributions of these three mechanisms fully account for hot-carrier degradation under inverterlike AC stress. No transient effects are required to explain AC stress results, at least for frequencies up to 1 MKz     

An analytical approach for physical modeling of hot-carrier induced degradation

We develop an analytical model for hot-carrier degradation based on a rigorous physics-based TCAD model. The model employs an analytical approximation of the carrier acceleration integral (calculated with our TCAD approach) by a fitting formula. The essential features of hot-carrier degradation such as the interplay between single-and multiple-electron components of Si–H bond dissociation, mobility degradation during interface state build-up, as well as saturation of degradation at long stress times are inherited. As a result, the change of the linear drain current can be represented by the analytical expression over a wide range of stress conditions. The analytical model can be used to study the impact of device geometric parameters on hot-carrier degradation.     

A unified model for the self-limiting hot-carrier degradation inLDD n-MOSFETs

A new insight into the self-limiting hot-carrier degradation in lightly-doped drain (LDD) n-MOSFETs is presented. The proposed model is based on the charge pumping (CP) measurement. By progressively lowering the gate base level, the channel accumulation layer is caused to advance into the LDD gate-drain overlap and spacer oxide regions, extending the interface that can be probed. This forms the basis of a novel technique, that allows the contributions to the CP current, due to stress-induced interface states in the respective regions, to be effectively separated. Results show that interface state generation initiates in the spacer oxide region and progresses rapidly into the overlap/channel region with stress time. The close correspondence between the linear drain current degradation, measured at high and low gate bias, and the respective interface state generation in the spacer and the overlap/channel regions deduced from CP data, provides an unambiguous experimental evidence that the degradation proceeds in a two-stage mechanism, involving first a series resistance increase and saturation, followed by a carrier mobility reduction. The saturation in series resistance increase results directly from a reduced interface state generation rate in the spacer oxide. For a given density of defect precursors and considering an almost constant channel field distribution near the drain region during stress, interface trap generation rate is shown to exhibit an exponential stress time dependence, with a characteristic time constant determined by the applied voltages. This observation leads to a lifetime extrapolation methodology. Lifetime due to a particular stress drain voltage V_d, may be extracted from a single composite degradation characteristic, obtained by shifting characteristics for various stress V_d's, along the stress time axis, until the characteristics merge into a single curve     

Consistent model for the hot-carrier degradation in n-channel andp-channel MOSFETs

A model is derived using the charge-pumping technique for the evaluation of the interface characteristics, in combination with the behavior of the drain and the substrate currents after degradation. For n-channel transistors the degradation is mainly caused by the generation of interface traps. Only in the region of hole injection (V_g≈V_t) is the degradation dominated by the trapped holes, which mask the effect of the generated interface traps. The degradation of p-channel transistors, although completely different at first sight, occurs by the same mechanisms. For this case, the degradation is caused by trapped negative charge, which masks the influence of the interface traps. The latter are nevertheless generated in comparable amounts as in n-channel transistors. Based on these insights, improved procedures for accelerated-lifetime experiments are proposed for both channel types. Finally, the peculiar degradation behavior of n-channel transistors under alternating injection conditions is discussed and fully explained based on the static stress degradation model     

An empirical model for device degradation due to hot-carrier injection

An empirical model for device degradation due to hot-carrier injection in submicron n-channel MOSFET's is presented. Relationships between device degradation, drain voltage, and substrate current are clarified on the basis of experiments and modeling. The presented model makes it possible to predict the lifetime of submicron devices by determining a certain criterion, such as taking a Vthshift of 10 mV over ten years as being allowable. This could also provide quantitative guiding principles for devising "hot-carrier resistant" device structures.     

Modeling of substrate current in p-MOSFET's

It is shown that the substrate current characterization method and modeling approach used for n-MOSFET's is also applicable to p-MOSFET's. The impact ionization rate extracted for holes is found to be 8 × 10⁶exp (-3.7 × 10⁶/E), where E is the electric field. Based on our measurement and modeling result, roughly twice the channel electric field is required for p-MOSFET's to generate the same amount of substrate current as n-MOSFET's. The hot-carrier-induced breakdown voltage is therefore also about two times larger.     

Drain current model for undoped Gate Stack Double Gate (GSDG) MOSFETs including the hot-carrier degradation effects

In this paper, analytical models of drain current and small signal parameters for undoped symmetric Gate Stack Double Gate (GSDG) MOSFETs including the interfacial hot-carrier degradation effects are presented. The models are used to study the device behavior with the interfacial traps densities. The proposed model has been implemented in the SPICE circuit simulator and the capabilities of the model have been explored by circuit simulation example. The developed approaches are verified and validated by the good agreement found with the 2D numerical simulations for wide range of device parameters and bias conditions. GSDG MOSFET design and the accurate proposed model can alleviate the critical problem and further improve the immunity of hot-carrier effects of DG MOSFET-based circuits after hot-carrier damage.     

Hot-carrier degradation of p-MOSFET's under analog operation

The hot-carrier degradation of p-MOSFET's is investigated from the viewpoint of analog operation. We apply sensitive measurement methods to determine drain current, drain conductance, and transconductance in the saturation regime besides the commonly investigated parameters in the linear regime of operation. Those investigations are performed for different gate lengths in order to allow comparisons between the shortest channels used for digital and the long channels usually used for analog operation, it is found that the drain conductance important in many analog applications, does not show a channel length dependence for gate lengths above 1.5 times the minimum gate length. The stress time dependencies are determined predominantly finding logarithmic behaviors. These findings are explained by a model which highlights the importance of the lengths of the regions of damage and carrier velocity saturation. Moreover, the dependencies of the different characterization parameters on stress time, channel length and voltages of operation are evaluated. Finally, methods are given for extrapolation of degradation of analog parameters to operating conditions for reliability assurance     

Compact analytical physical-based model of LTPS TFT for active matrix displays addressing circuits simulation and design

Either at pixel or driver levels, low-temperature polysilicon (LTPS) is becoming a standard technology for the fabrication of thin-film transistors (TFTs) used in active matrix liquid crystal displays and in active matrix organic light emissive displays. Given the complexity of addressing or pixel circuits, simulation is becoming more and more necessary. In order to reach the required level of simulation efficiency, an accurate model has been developed. This model takes into account all the operating regimes, capacitors contributions, and frequency dispersion effects. In order to be able to simulate large number of matrix pixels and/or integrated drivers, this model is simple enough to allow simulator convergence. Based on 38 parameters, it presents an easy electrical parameters characterization methodology. Moreover, physical parameters use allows an easy modification of the model performances depending on polycrystalline silicon TFT technology properties and evolution.     

A lifetime prediction method for hot-carrier degradation insurface-channel p-MOS devices

Hot carrier degradation of p-MOS devices at low gate voltages (V_g<V_d) is examined. It is shown that the electronic gate current is the principal factor in stress damage in this gate voltage range and that the damage itself consists of trapped electrons, localized close to the drain junction. The saturation of the transconductance change as a function of time which is seen at long stress times of high stress voltages results from a change in the injected gate current as a function of time. This is caused by changes in electric field in the silicon due to charge trapping in the oxide during stress. The saturation effect can, however, be transformed into a simple power law if the time axis is multiplied by the square of the instantaneous gate current. This allows for the development of a lifetime-prediction method. The method is applied to 1.0-μm p-MOS devices, and a lifetime is estimated     

Leakage-current-induced hot-carrier degradation of p-channelMOSFETs

Leakage-current-induced hot-carrier effects have been observed during stressing of p-channel MOSFETs in the OFF state with V _GS>0 V and V_DS<0 V. This mode of stressing results in increased leakage current and a positive shift in the value of V_GS, corresponding to the onset of avalanche breakdown of the drain junction. These effects are related to generation of interface states near the drain in forward-mode operation. By comparison, conventional stressing in the ON state with V _GS<0 V and V_DS<0 V resulted in little change in these p-channel MOSFET characteristics     

An analytical threshold voltage model of NMOSFETs with hot-carrier induced interface charge effect

An analytical threshold voltage model of NMOSFETs including the effect of hot-carrier-induced interface charges is presented. A step function describing the interface charge distribution along the channel is used to account for the hot carrier induced damage, and a pseudo-2D method is applied to derive the surface potential. The threshold voltage model is then developed by solving the gate-to-source voltage at the onset of surface inversion where the minimum surface potential equals the channel potential. Both the drain-induced barrier lowering (DIBL) and body effects are included in the present model as well. The present threshold voltage model is validated for both fresh and damaged devices. The results show that the threshold voltage shifts upward and approaches a maximum value with negative interface charges and shifts downward and reaches a minimum value with positive interface charges as the interface charge region length is increased from zero to the channel length. Model is successfully verified using simulation data obtained from TCAD (technology-based computer-aided design).     

An analytical subthreshold current model for pocket-implanted NMOSFETs

An analytical subthreshold current model for metal oxide semiconductor field effect transistors (MOSFETs) with pocket implantation is presented. The model is developed based on considering an averaged localized pileup of channel dopants near the source and drain ends of channel to account for the pocket implantation effect and to derive the channel potential using a pseudo-two-dimensional (2-D) method. This, together with the conventional drift-diffusion theory, leads to the development of a subthreshold current model for pocket-implanted MOS devices. Model verification is carried out using data measured from a set of pocket-implanted NMOSFETs fabricated from a 0.17-/spl mu/m, DRAM process. Very good agreement is obtained between the model calculations and measurement results.     

An analytical gate tunneling current model for MOSFETs

Gate tunneling current of MOSFETs is an important factor in modeling ultra small devices. In this paper, gate tunneling in present-generation MOSFETs is studied. In the proposed model, we calculate the electron wave function at the semiconductor-oxide interface and inversion charge by treating the inversion layer as a potential well, including some simplifying assumptions. Then we compute the gate tunneling current using the calculated wave function. The proposed model results have an excellent agreement with experimental results in the literature.     

A reassessment of ac hot-carrier degradation in deep-submicrometer LDD N-MOSFET

In deep submicrometer N-MOSFET, a "backdrop" of substantial defect generation by the quasi-static V/sub g/=V/sub d/ stress phase is shown to significantly influence the accuracy of interpretation of ac stress data. If neglected, a severe overestimation of ac stress induced degradation would result. Through an approach that eliminates this damage component from the overall ac stress damage, increased parametric shifts, associated with the gate pulse transition phase, are found to occur in different time windows, delineated by the relative importance of hot-hole and hot-electron induced damage at different stages of the stress, the interaction between the two damages at specific stages of the stress, as well as the sensitivities of the device parameters to the spatial evolution of the two damages.     

A bidirectional NMOSFET current reduction model for simulation ofhot-carrier-induced circuit degradation

An approach for modeling hot-electron induced change in drain current that significantly improves the ease of parameter extraction and provides new capabilities for modeling the effect of bidirectional stressing and the asymmetrical I-V characteristics after stressing is presented. The change in the drain current, ΔI_D is implemented as an asymmetrical voltage-controlled current source and the new ΔI_D model is independent of the MOSFET model used for circuit simulation. The physical basis of the model, the analytical model equations, the implementation scheme in BERT (BErkeley Reliability Tools) simulator and simulation results for uni- and bidirectional circuit stressing are presented     

A new quasi-2-D model for hot-carrier band-to-band tunnelingcurrent

A significant mismatch occurs when we predict the gate-induced drain leakage current (GIDL) by using existing one-dimensional (l-D) models. It's found that the gate-induced drain leakage current is attributed to not only the vertical field but also the lateral field near the drain-to-gate overlap region. Therefore, a new quasi-two-dimensional (quasi-2-D) model considering both the lateral and vertical fields for predicting the gate-induced drain leakage current is proposed by using the drain-induced energy-barrier reduction in our model. The calculated results using the developed quasi-2-D model are in good agreement with measured values for a wide range of gate and drain biases. Therefore, the proposed new model can be used to simulate the hot-carrier band-to-band tunneling current for p-channel flash memory device