一种基于图模式匹配的逻辑单元映射算法

基于数学中图模式匹配的概念,根据电路特征在于图同构算法中加入图约束条件,研究了针对不同结构的FPGA逻辑单元都能适用的映射算法FDUMap．实验中应用FDUMap将测试电路映射到不同的逻辑单元中,该算法比现有的专用的逻辑单元映射算法通用性更好,而平均性能上仅相差3％。     

A Data-Parallel FP Compiler

In data-parallel programming, operations are performed simultaneously on all elements of large data structures. Backus′s FP functional language promotes this view. FP provides a large set of data rearrangement primitives, and a useful set of functional combining forms that are applied to entire data structures. We describe an FP compiler that generates programs capable of exploiting data-parallelism. The FP compiler deduces the type and shape of objects through type inference, and generates efficient parallel implementations of combining forms. In addition, the compiler determines the effects of data rearrangement functions at compile-time, thereby avoiding creation of large intermediate data structures, and reducing interprocessor communication overhead. FP and its compiler are formally specified, reducing ambiguity concerning constructs of the language and results of the compiler. Performance and speed-ups achieved from our compilation and optimization techniques are demonstrated with timings from a prototype implementation on the Connection Machine CM-2.     

编译基础设施中多目标编译技术探讨

从编译基础设施的基本概念出发，着重讨论了编译器后端构造所涉及的关键技术；比较全面地总结并评述了具有代表性的公共编译设施及春采用的中间表示技术、后端构造技术和相关工具；并探讨了编译器后端构造研究中存在的一些问题及相应的解决方案。     

A Formally Verified Compiler Back-end

This article describes the development and formal verification (proof of semantic preservation) of a compiler back-end from Cminor (a simple imperative intermediate language) to PowerPC assembly code, using the Coq proof assistant both for programming the compiler and for proving its soundness. Such a verified compiler is useful in the context of formal methods applied to the certification of critical software: the verification of the compiler guarantees that the safety properties proved on the source code hold for the executable compiled code as well.     

Compiler Verification and Compiler Architecture

We study issues in verifying compilers for modern imperative and object-oriented languages. We take the view that it is not the compiler but the code generated by it which must be correct. It is this subtle difference that allows for reusing standard compiler architecture, construction methods and tools also in a verifying compiler.Program checking is the main technique for avoiding the cumbersome task of verifying most parts of a compiler and the tools by which they are generated. Program checking remaps the result of a compiler phase to its origin, the input of this phase, in a provably correct manner. We then only have to compare the actual input to its regenerated form, a basically syntactic process. The correctness proof of the generation of the result is replaced by the correctness proof of the remapping process. The latter turns out to be far easier than proving the generating process correct.The only part of a compiler where program checking does not seem to work is the transformation step which replaces source language constructs and their semantics, given, e.g., by an attributed syntax tree, by an intermediate representation, e.g., in SSA-form, which is expressing the same program but in terms of the target machine. This transformation phase must be directly proven using Hoare logic and/or theorem-provers. However, we can show that given the features of today's programming languages and hardware architectures this transformation is to a large extent universal: it can be reused for any pair of source and target language. To achieve this goal we investigate annotating the syntax tree as well as the intermediate representation with constraints for exhibiting specific properties of the source language. Such annotations are necessary during code optimization anyway.     

A Vectorizing Compiler for Multimedia Extensions

In this paper, we present an implementation of a vectorizing C compiler for Intel's MMX (Multimedia Extension). This compiler would identify data parallel sections of the code using scalar and array dependence analysis. To enhance the scope for application of the subword semantics, our compiler performs several code transformations. These include strip mining, scalar expansion, grouping and reduction, and distribution. Thereafter inline assembly instructions corresponding to the data parallel sections are generated. We have used the Stanford University Intermediate Format (SUIF), a public domain compiler tool, for our implementation. We evaluated the performance of the code generated by our compiler for a number of benchmarks. Initial performance results reveal that our compiler generated code produces a reasonable performance improvement (speedup of 2 to 6.5) over the the code generated without the vectorizing transformations/inline assembly. In certain cases, the performance of the compiler generated code is within 85% of the hand-tuned code for MMX architecture.     

IDL编译器的Java实现

文章从阐述接口定义语言（ＩＤＬ）编译器在ＣＯＲＢＡ开发模型中的作用开始,提出了ＩＤＬ编译器的开发模型,然后讨论了编译器的实现过程中的技术问题。     

一种有效的优化编译实现策略

优化编译技术在现代处理器的研究中表现出越来越重要的作用。文章从现代编译器的结构入手,综合介绍现代编译器所普遍采用的优化技术,并提出了一种有效的优化编译器实现策略。     

A Compiler Intermediate Representation for Reconfigurable Fabrics

Configurable computing relies on the expression of a computation as a circuit. Its main purpose is the hardware based acceleration of programs. Configurable computing has received renewed interest with the recent rapid increase in both size and speed of FPGAs. One of the major obstacles in the way of wider adoption of (re)configurable computing is the lack of high-level tools that support the efficient mapping of programs expressed in high-level languages (HLL) to reconfigurable fabrics. The major difficulty in such a mapping is the translation from a temporal execution model to a spatial execution model. An intermediate representation (IR) is the central structure around which tools such as compilers and synthesis tools are built. In this paper we propose an IR specifically designed for reconfigurable fabrics: CIRRF (Compiler Intermediate Representation for Reconfigurable Fabrics). We describe the design of CIRRF and its initial implementation as part of the ROCCC compiler for translating C code to VHDL. CIRRF is designed to support the creation of a datapath and the scheduling of operations on it. It provides support for buffers, look-up tables, predication and pipelining in the datapath. One of the important features of CIRRF, and ROCCC, is its support for the import of pre-designed IP cores into the original C source code allowing the user to leverage the huge wealth of existing IP cores while programming the configurable platform using a HLL. Using experiments and examples we show that CIRRF is a solid foundation to generate high-performance hardware.     

一种支持DSP条件执行指令的编译框架

为克服条件跳转指令的缺陷,新一代超长指令字（VLIW）体系结构的数字信号处理器（DSP）提供了对条件执行指令的支持。为使得此类指令的优势得以充分发挥,该文设计并实现了一种基于hyperblock区域结构的编译框架。实验结果表明,该框架很好地提高了指令级并行虚（ILP）,减少了指令执行时间。     

一种面向可重构硬件的编译中间表示方法

中间表示氓是构建编译和高级综合工具的基础。本文设计了一种面向可重构硬件的编译中间表示方法。这一工作是我们设计的高级综合工具的一部分。实验结果表明,应用这 一中间表示,可以将C源程序高效地映射到目标可重构硬件上。     

A Framework for Incremental Extensible Compiler Construction

Extensibility in complex compiler systems goes well beyond modularity of design and it needs to be considered from the early stages of the design, especially the design of the Intermediate Representation. One of the primary barriers to compiler pass extensibility and modularity is interference between passes caused by transformations that invalidate existing analysis information. In this paper, we also present a callback system which is provided to automatically track changes to the compilers internal representation (IR) allowing full pass reordering and an easy-to-use interface for developing lazy update incremental analysis passes. We present a new algorithm for incremental interprocedural data flow analysis and demonstrate the benefits of our design framework and our prototype compiler system. It is shown that compilation time for multiple data flow analysis algorithms can be cut in half by incrementally updating data flow analysis.     

CCC: A Caching Compiler for C

C compilers in production environments often have to reprocess the same header files. CCC is a caching C compiler which maintains a database of partially processed header files so that repetitive work may be eliminated. © 1997 by John Wiley & Sons, Ltd.     

低功耗多线程编译优化技术

提出了在多线程体系结构中通过降低执行频率有效减小功耗的理论模型和方法.首先研究识别可降频运行的线程的计算模型和降频因子的计算,然后给出在编译过程中基于对应用程序行为的分析,结合线程划分的低功耗编译优化算法和实现策略.该模型和方法可用于具有执行频率可动态调整的多处理器类多线程体系结构,既可开发TLP(thread level parallelism),又可有效减小功率消耗.     

编译课程体系建设刍议

针对大学计算机专业编译课程教学实际,分析了编译课程在计算机人才培养过程中的重要性;通过对国内外知名高校编译课程设置的梳理以及编译技术最新进展的研究,结合国家自主安全可控计算机生态链建设的需求,提出了构建编译课程体系的初步构想。