Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test

This paper presents the results of resistive-open defect insertion in different locations of Infineon 0.13 m embedded-SRAM with the main purpose of verifying the presence of dynamic faults. This study is based on the injection of resistive defects as their presence in VDSM technologies is more and more frequent. Electrical simulations have been performed to evaluate the effects of those defects in terms of detected functional faults. Read destructive, deceptive read destructive and dynamic read destructive faults have been reproduced and accurately characterized. The dependence of the fault detection has been put in relation with memory operating conditions, resistance value and clock cycle, and the importance of at speed testing for dynamic fault models has been pointed out. Finally resistive Address Decoder Open Faults (ADOF) have been simulated and the conditions that maximize the fault detection have been discussed as well as the resulting implications for memory test.This work has been partially funded by the French government under the framework of the MEDEA + A503 ASSOCIATE European program.A paper based on this work was presented at the Eighth IEEE European Test Workshop, Maastricht, The Netherlands, May 2003.Simone Borri received the M.Sc. Degree (summa cum laude) in Electronics Engineering from the University of Pisa (Italy) in 1995. In 1997 he joined STMicroelectronics as a digital designer in the DSP development group of S.S.D. (formerly Parthus, now Ceva), Dublin, Ireland. From 1998 to 2000 he was with ST Microelectronics, Milan, Italy as ASIC DSP designer in the Car Communication business unit. Since 2000 he is with Infineon Technologies, Sophia-Antipolis, France as Staff design engineer in the embedded-SRAM design group. He has recently joined the Secure Mobile System Business Unit. His current interests include BIST, DFT techniques and SoC verification. Simone is an IEEE member since 1995.Magali Hage-Hassan was born near Lyon (France) in 1979. She received a Master of Science degree of Microelectronics and Automatics from the Institute of Engineering Sciences of Montpellier in 2003. She is currently working for Infineon in the memory library department in Sophia-Antipolis. She participated to the European research project MEDEA associate. Hage-Hassans interest include memory test.Luigi Dilillo was born in Barletta (Italy) in 1974. At this moment he is doing his last year of Ph.D. in the Microelectronics Department of the Laboratory of Informatics, Robotics and Microelectronics of Montpellier (LIRMM) in France. He received his degree in Electrical Engineering in 2001, at Politecnico di Torino (Italy). His researches include MEMS and digital circuits. At this moment he is working on delay-fault testing, and memory testing.Patrick Girard is presently Researcher at CNRS (French National Center for Scientific Research), and works in the Microelectronics Department of the LIRMM (Laboratory of Informatics, Robotics and Microelectronics of Montpellier—France). His research interests include the various aspects of digital testing, with special emphasis on DfT, logic BIST, delay fault testing and diagnosis, low power testing and memory testing. He has authored and co-authored 1 book and more than 100 papers on these fields. He has managed several European research projects and industrial research contracts. He is Editor-in-Chief of JOLPE—Journal of Low Power Electronics, and Associate Editor of JEC—Journal of Embedded Computing. He will serve as Program vice-Chair for the International Conference on Embedded And Ubiquitous Computing in 2005 and as Program Chair for the IEEE International Workshop on Electronic Design, Test & Applications in 2006. He is also topic chair of two European conferences (DATE and ETS) and is member of the program committee of several other international conferences. Patrick GIRARD obtained the Ph.D. degree in microelectronics from the University of Montpellier in 1992 and the Habilitation à Diriger des Recherches degree from the University of Montpellier in 2003.Serge Pravossoudovitch was born in 1957. He is currently professor in the electrical and computer engineering department of the University of Montpellier and his research activities are performed at LIRMM (Laboratoire dInformatique, de Robotique et de Microélectronique de Montpellier). He got the Ph.D. degree in electrical engineering in 1983 for his work on symbolic layout for IC design. Since 1984, he is working in the testing domain. He obtained the doctorat détat degree in 1987 for his work on switch level automatic test pattern generation. He is presently interested in memory testing, delay fault testing, design for testability and power consumption optimization. He has authored and co-authored numerous papers on these fields, and has supervised several Ph.D. dissertations. He has also participated to several European projects (Microelectronic regulation, Esprit, Medea).Arnaud Virazel was born in Montpellier (France) in 1974. He is presently assistant professor at the university of Montpellier, and works with the LIRMM (Laboratoire dInformatique, de Robotique et de Microélectronique de Montpellier). He received the B.Sc. (1995) and the M.Sc. (1997) degrees in Electrical Engineering and the Ph.D. (2001) degree in Microelectronics, all from the University of Montpellier/LIRMM. A. Virazels interests include delay testing, memory testing and power optimization during test.     

Efficiency of Optimized Dynamic Test Flows for ADCs: Sensitivity to Specifications

The long and complex procedure to test ADCs constitutes an important issue in the context of mixed-signal testing. To lower the testing costs, we propose shorter but less selective test flows solely based on spectral analysis. This paper investigates the efficiency that can be achieved using this approach and studies the influence of the ADC specifications on the efficiency of the proposed dynamic-only test flows.Florence Azaïs received the Ph.D. degree in electrical engineering from the University of Montpellier, France in 1996. She is currently working in the Microelectronics department of the Laboratory of Computer Science, Robotics and Microelectronics of Montpellier (LIRMM) as a researcher of the National Council of Scientific Research (CNRS). Since 1993, she has been interested in the general domain of test and reliability of integrated circuits and systems. Her main research interests include fault modeling, analog and mixed-signal circuit testing, MEMS testing, reliability and failure analysis of integrated systems. She has authored or co-authored over 80 international papers on these topics. She also served as a member of the Program Committee of several international conferences (DATE, ICCD, ETS, IMSTW, LATW).Serge Bernard received the M.S. degree in Electrical Engineering from the University of Paris XI, France in 1998 and the Ph.D. degree in Electrical Engineering from the University of Montpellier, France in 2001. He is a researcher of the National Council of Scientific Research (CNRS) in the Microelectronics Department of the Laboratory of Computer Science, Robotics and Microelectronics of Montpellier (LIRMM). His main research interests include Test, Design-For-Testability and Built-In-Self-Test for mixed-signal circuits and Design-For-Reliability for medical application ICs.Yves Bertrand is a Professor at the University of Montpellier (France). He works at the Microelectronics Department of the Laboratoire dAutomatique, Robotique et Microélectronique de Montpellier (LIRMM). Previously, Yves Bertrand worked in the field of solid-state physics and published several papers, especially on the photoemission of the semiconductors under synchrotron radiation. He joins the LIRMM in 1988. His research interests are principally, Fault Modeling, Design-For-Test and Built-In Self-Test for digital and mixed-signal analog/digital Integrated Circuits. He is author or co-author of about 200 papers in the field of solid-state physics and microelectronics. He is presently responsible for the CRTC (Centre de Ressources de Test du CNFM), which is the Common Test Resources Center for the French and European Universities.Mariane Comte took her Master of Engineering and Master of Sciences degrees in microelectronics engineering at INPG, (Institut National Polytechnique de Grenoble, National Engineering University Institution of Grenoble), France, in 2000. She carried out her Ph.D. studies at LIRMM (Laboratoire dInformatique, de Robotique et de Microélectronique de Montpellier, Computer Sciences, Robotics and Microelectronics Laboratory of Montpellier), France, working on Analog-to-Digital Converter testing, and received Ph.D. degree in microelectronics from the University of Montpellier, France, in 2003. After a post-doctoral fellow position at the Computer Design and Test Laboratory of NAIST (Nara Institute of Science and Technology), Japan, where she investigated on the detection of Gate-Oxide Shorts in Domino Logic cells, she is currently working as an assistant professor at the University of Montpellier. Her fields of interest spread from analog and mixed-signal testing to defect modeling.Michel Renovell is head of the Microelectronics Department at LIRMM (Laboratory of Computer Science, Automation and Microelectronics of Montpellier). His research interests include: Fault modeling, Analog testing and FPGA testing. He is Vice-Chair of the IEEE TTTC (Test Technology Technical Committee). He is a member of the editorial board of JETTA and the editorial board of IEEE Design & Test. Michel has been General Chair of the International Mixed Signal Testing Workshop IMSTW2000, the Field Programmable Logic Conference FPL2002 and the European Test Symposium ETS2004.     

Applying the Oscillation Test Strategy to FPAA’s Configurable Analog Blocks

This paper presents the application of the oscillation test methodology as an alternative to test configurable analog blocks of Field Programmable Analog Arrays. The blocks of the device under test are first configured to behave as oscillators. Then, the output frequency and amplitude are observed to obtain the signature of the fault-free circuit. During test, this signature is compared to the actual output signal. Experimental results show the effectiveness of the method in detecting parametric and large deviation faults of the tested components.A paper based on this work was presented at the Fourth IEEE Latin American Test Workshop, Natal, Brazil, February 2003.Tiago Roberto Balen was born in Erechim, Brazil, in 1979. He received the Electrical Engineering degree from the Universidade Federal do Rio Grande do Sul (UFRGS), Porto Alegre, Brazil in 2004. At present, he is M.Sc. student in the Electrical Engineering Department and works in the Prototyping and Test Laboratory at UFRGS. His research interests include analog and mixed-signal design and test, built-in self-test and design-for-testability. He has published papers on FPAA testing in important conferences, such as the VLSI Test Symposium (VTS) and the International Test Conference (ITC).Antonio Andrade, Jr., received the Electrical Engineering degree from the Universidade Federal da Bahia (UFBA), Salvador, Brazil, in 2003, and is currently pursuing the M.Sc. degree at Universidade Federal do Rio Grande do Sul (UFRGS), Porto Alegre, Brazil. His experience as a researcher includes the design of a temperature controller using thermo-resistive sensors and FPGA prototyping, at the Instrumentation Laboratory in UFBA, in 2001, a 2-month scholarship from Laboratorio Nacional de Luz Sincrotron (LNLS), Campinas, Brazil, in 2002, and 2 years as a graduate student at the Prototyping and Test Laboratory, at UFRGS. His primary research topics include Mixed-Signal Circuit and Systems Testing as well as fast system prototyping in platforms as FPGAs and FPAAs, having published papers in important conferences, such as the VLSI Test Symposium (VTS) and International Test Conference (ITC), in the field of FPAA testing.Florence Azaïs received the Ph.D. degree in electrical engineering from the University of Montpellier, France in 1996. She is currently working in the Microelectronics department of the Laboratory of Computer Science, Robotics and Microelectronics of Montpellier (LIRMM) as a researcher of the National Council of Scientific Research (CNRS). Since 1993, she has been interested in the general domain of test and reliability of integrated circuits and systems. Her main research interests include fault modeling, analog and mixed-signal circuit testing, MEMS testing, reliability and failure analysis of integrated systems. She has authored or co-authored over 80 international papers on these topics. She also served as a member of the Program Committee of several international conferences (DATE, ICCD, ETS, IMSTW, LATW).Marcelo Lubaszewski received the Electrical Engineering and M.Sc. degrees from the Universidade Federal do Rio Grande do Sul (UFRGS), Porto Alegre, Brazil, in 1986 and 1990, respectively. In 1994, he received the Ph.D. degree from the Institut National Polytechnique de Grenoble (INPG), France. In 2001, he joined the Laboratoire dInformatique, Robotique et Microélectronique de Montpellier in France as an Invited Researcher for 3 months and, in 2004, the Instituto de Microelectrónica de Sevilla (IMSE) in Spain for 1 year. He is currently with UFRGS, where he has been an Associate Professor since 1990. His primary research interests include design and test of mixed-signal, micro-electro-mechanical and core-based systems, self-checking and fault-tolerant architectures, and computer-aided testing. He has published over 150 papers in international journals and conferences on these topics. Dr. Lubaszewski has served as the general chair or program chair of the Symposium on Integrated Circuits and Systems Design (SBCCI) and of the Latin American Test Workshop (LATW), and as a member of the Organizing or the Program Committee of the VLSI Conference, the International Mixed-Signals Testing Workshop, the Asian Test Symposium, the European Design and Test Conference, the Design of Complex Integrated Systems Conference, the European Test Symposium and the GHz/Gbps Test Workshop. He has also served as a Guest Editor of the Journal of Electronic Testing: Theory and Applications and as an Associate Editor of the Design and Test of Computers Magazine.Michel Renovell is head of the Microelectronics Department at LIRMM (Laboratory of Computer Science, Automation and Microelectronics of Montpellier). His research interests include: Fault modeling, Analog testing and FPGA testing. He is Vice-Chair of the IEEE TTTC (Test Technology Technical Committee). He is a member of the editorial board of JETTA and the editorial board of IEEE Design & Test. Michel has been General Chair of the International Mixed Signal Testing Workshop IMSTW2000, the Field Programmable Logic Conference FPL2002 and the European Test Symposium ETS2004.     

Design and implementation of an optimised wireless pressure sensor for biomedical application

This paper presents design and implementation of a wireless pressure sensor system for biomedical application. The system consists of a front-end Micro-Electro- Mechanical System (MEMS) sensing capacitor along with an optimised MEMS-based oscillator for signal conditioning circuit. In this design, vertical fringed comb capacitor is employed due to the advantages of smaller area, higher linearity and larger full scale change in capacitance compared to parallel plate counterparts. The MEMS components are designed in Coventorware design suite and their Verilog-A models are extracted and then imported to Cadence for co-simulation with the CMOS section of the system using AMI 0.6-micron CMOS process. In this paper, an optimisation method to significantly reduce the system power consumption while maintaining the system performance sufficient is also proposed. A phase noise optimisation approach is based on the algorithm to limit the oscillator tail current. Results show that for the pressure range of 0–300 mmHg the device capacitance range of 1.31 pF – 1.98 pF is achieved which results in a frequency sweep of 2.54 GHz – 1.95 GHz. Results also indicate that a 42% reduction of power consumption is achieved when the optimisation algorithm is applied. This characteristic makes the sensor system a better candidate for wireless biomedical applications where power consumption is the major factor. Hai Phuong Le received his B.E. (Hons) degree in Electronic and Computer System Engineering from University of Tasmania, Hobart, Australia in 2000. He received his Ph.D. degree in Microelectronics from Victoria University, Melbourne, Australia in 2005. At present, he is a post-doctoral research fellow and lecturer in the Centre for Telecommunications and Microelectronics, Victoria University. His research and teaching interests include data acquisition system, mixed-signal integrated circuit design and wireless smart sensor systems. Kriyang Shah received his B.E. Degree in Electronics and Communication Engineering from Sardar Patel University, Vallabh Vidyanagar, Gujarat, India and his Master Degree in Microelectronics in 2004. He is currently a Ph.D. research student in the Centre for Telecommunications and Microelectronics, Victoria University, Melbourne, Australia. His research interests include MEMS Sensors, RF MEMS, process integration for MEMS and CMOS and MEMS-CMOS co-simulation. Jugdutt (Jack) Singh received his B.Sc. in Electronics Engineering from University of Brighton, UK and M.Sc. in Electronics Engineering from University of Alberta, Canada in 1978 and 1986 respectively. He completed his Ph.D. at Victoria University, Australia in 1997. Since 1989 he has been at Victoria University, Melbourne, Australia. Currently he is a Professor of Microelectronics in the Centre for Telecommunications and Microelectronics at Victoria University. His major area of research interests are in the RF, analog and mixed signal design, reconfigurable architectures, low power VLSI circuits and systems design. He has published number of articles in education and research in microelectronics and small technologies area. Aladin Zayegh received his B.E. degree in Electrical Engineering from Aleppo University in 1970 and Ph.D. degree from Claude Bernard University, France in 1979. In 1980, he joined the Faculty of Engineering, Tripoli, Libya. Since 1984 he has held lecturing position at Victoria University, Melbourne, Australia. He is currently an Associate Professor and the Head of School in the School of Electrical Engineering, Faculty of Health, Engineering and Engineering and Science at Victoria University. His research interest includes microprocessor-based system, instrumentation, data acquisition and interfacing, and microelectronics.     

On-Chip Pseudorandom MEMS Testing

This paper presents a Built-In-Self-Test (BIST) implementation of pseudo-random testing for MEMS. The technique is based on Impulse Response (IR) evaluation using pseudo-random Maximum–Length Sequences (MLS). The MLS approach is capable of providing vastly superior dynamic range in comparison to the straightforward technique using an impulse excitation and is thus an optimal solution for measurements in noisy environments and for low-power test signals. The use of a pseudo-random sequence makes the practical on-chip implementation very efficient in terms of the extra hardware required for on-chip testing. We will demonstrate the use of this technique for an on-chip fast and accurate broadband determination of MEMS behaviour, in particular for the characterisation of cantilever MEMS structures, determining their mechanical and thermal behaviour using just electrical tests.Libor Rufer has received Engineering and PhD degrees from the Czech Technical University, Prague, Czech Republic. Until 1993 he was with the Faculty of Electrical Engineering of the Czech Technical University, Prague and since 1994, he is Associate Professor at the Joseph Fourier University, Grenoble, France. In 1998, he joined the Microsystems research team of the TIMA Laboratory. Currently he is a member of the Reliable Mixed-signal Systems Group of the same Laboratory. His expertise and research interests pertain MEMS-based sensors and actuators, electro-acoustic and electro-mechanical transducers, their modelling, applications, associated measurement techniques, and analogue and mixed-signal system test.Salvador Mir has an Industrial Engineering (Electrical, 1987) degree from the Polytechnic University of Catalonia, Barcelona, Spain, and M.Sc. (1989) and Ph.D. (1993) degrees in Computer Science from the University of Manchester, UK. He is a researcher of Centre National de la Recherche Scientifique, France, and he is leading the RMS (Reliable Mixed-signal Systems) Group at TIMA Laboratory in Grenoble, France. He is the author of many research papers and editor of two books on silicon microsystems. His research interests include analogue, mixed-signal, RF and microsystem design and test, and applications of Artificial Intelligence to Computer-Aided Design.Emmanuel Simeu received Electrical Engineering degree, DEA and Ph.D. in Automatic Control from National Polytechnic Institute of Grenoble in 1987, 1988 and 1992, respectively. He is Associate Professor of Automatic Control and Electrical engineering in Joseph Fourier University of Grenoble. He is also a researcher in the RMS Group at TIMA Laboratory. His research interests include system modelling, reliability of integrated systems, online testing of analogue, digital and mixed signal systems.Christian Domingues was born in Lyon, France, in 1978. He received a Master degree in Microelectronics from the Institut National Polytechnique de Grenoble, France, in 2001. He is currently pursuing a Ph.D. degree at TIMA Laboratory in Grenoble, France. His research interests include mixed-signal integrated circuit design, and micromachined sensors and actuators.     

CCII-Based Grounded to Floating Immittance Converter and a Floating Inductance Simulator

A new circuit employing second-generation current conveyors (CCIIs), and unmatched resistors for converting a grounded immittance to the corresponding floating immittance with either positive or negative adjustable multiplier, is presented. Moreover, the proposed circuit can also realize a synthetic floating inductance employing a grounded capacitor depending on the passive element selection. Simulation results using 0.35 μ m TSMC CMOS technology parameters are given. Erkan Yuce was born in 1969 in Nigde, Turkey. He received the B.Sc. from Middle East Technical University and M.Sc. degrees from Pamukkale University in 1994 and 1998 respectively. He is a Ph.D. student at Bogazici University all in Electrical and Electronics Engineering. He is currently Research Assistant at the Electrical and Electronics Engineering Department of Bogazici University. His current research interests include analog circuits, active filters, synthetic inductors, and current-mode circuits. He is the author or co-author of about 10 papers published in scientific journals or conference proceedings. Oguzhan Cicekoglu was born in 1963 in Istanbul, Turkey. He received the B.Sc. and M.Sc. degrees from Bogazici University and the Ph.D. degree from Istanbul Technical University all in Electrical and Electronics Engineering in 1985, 1988 and 1996 respectively. He served as lecturer at the School of Advanced Vocational Studies Electronics Prog. of Bogazici University where he held various administrative positions between 1993 and 1999, and as part time lecturer at various institutions. He was with Biomedical Engineering Institute between 1999 and 2001. He is currently Associate Professor at the Electrical and Electronics Engineering Department of Bogazici University. His current research interests include analog circuits, active filters, analog signal processing applications and current-mode circuits. He is the author or co-author of about 150 papers published in scientific journals or conference proceedings. Oguzhan Cicekoglu is a member of the IEEE. Shahram Minaei received his B.Sc. degree in Electrical and Electronics Engineering from Iran University of Science and Technology in 1993. He received his M.Sc. and Ph.D. degrees in Electronics and Communication Engineering from Istanbul Technical University in 1997 and 2001, respectively. He is currently an Associate Professor at the Electronics and Communication Engineering Department of Dogus University in Istanbul, Turkey. He has more than 50 journal or conference papers in scientific review. He served as reviewer for a number of international journals and conferences. His current field of research concerns current-mode circuits and analog signal processing. Shahram Minaei is a member of the IEEE.     

Multidimensional DSP Core Synthesis for FPGA

Current rapid synthesis approaches for reusable dedicated hardware components (cores) for digital signal processing systems are ineffective since they fail to capture and exploit the manner in which the resulting components are used as part of a heterogeneous system. This leads to counter-productive core redesign for each use of the core. This paper presents a solution to this issue which combines a novel but intuitive system modeling technique and associated core generation and integration methodology which generates reuable core architectures which may be optimised via algorithm level transformations. For an example design problem, these provide an effective rapid core synthesis and implementation exploration flow which allows a factor 3.9 throughput increase with no extra hardware expense. John McAllister received a first honours B.Eng degree in Electrical and Electronic Engineering and the degree of PhD from Queen’s University Belfast, UK in 2001 and 2004 respectively.From October 2004 to July 2005 he was a Postdoctoral Research Assistant in the Programmable Systems Laboratory in the System on Chip research group in the Institute for Electronics, Communication and Information Technology (ECIT) at Queen’s University Belfast.In July 2005 he was appointed to a lectureship in SoC technology in the International Centre for System-on-Chip and Advanced Microwireless (SoCAM) project at ECIT. Roger Woods received the degree of B.Sc with Honours in Electrical and Electronic Engineering and degree of Ph.D. from the Queen’s University of Belfast, UK in 1985 and 1990 respectively. From 2003, he has been a Professor at the same university and leads the programmable systems and networks laboratory there. His main research interests are programmable hardware systems using FPGAs, design tools for heterogeneous platforms and low power VLSI. He has published over 120 papers in the area of VLSI and DSP, holds two patents and serves on numerous technical program committees including Workshop on Signal Processing Systems, Field Programmable Logic and Field Programmable Technology. He is a member the IEEE Signal Processing Society Technical Committee for the Design and Implementation of Signal Processing Systems and chair of the IEE Professional Network on Microelectronics and Embedded Systems. Richard Walke received his Ph.D. from Warwick University in 1998 for work on arithmetic, architectures and implementations of adaptive weight calculation in ASIC. Subsequently he worked on the implementation of a range of DSP algorithms in FPGA, specialising in floating-point arithmetic, digital receivers and adaptive beamformers on FPGA. In recent years he has lead work to address the design of heterogeneous systems employing both processor and FPGA. Last year he moved to Xilinx, and is now responsible for the development of their floating-point IP solution. Darren Reilly received first honours B.Eng. Degree in Electronic and Software Engineering from the Queen’s University Belfast in 2002. He is currently pursuing a Ph.D. in Queen’s University Belfast due to finish in September 2005. His research interests lie in the rapid development of efficient architectures for FPGA as part of a system level design flow.     

A new CMOS multimode digital pixel sensor dedicated to an implantable visual cortical stimulator

We describe in this paper a new CMOS multimode image pixel sensor (MIPS) dedicated to an implantable visual cortical stimulator. Each 16 μm × 16 μm pixel area contains a photodiode, with a fill factor of 22%, a comparator used to convert the pixel level from analog to digital (A/D) values and an 8-bit DRAM, resulting in a total of 44 transistors per pixel. The A/D conversions use one common digital to analog converter to deliver the voltage reference needed to determine the pixel voltage. Three selectable operation modes are combined in the proposed MIPS: A high dynamic range logarithmic mode, a linear integration mode, and a novel differential mode between two consecutive images. This last mode that allows 3D information is required for a visual cortical stimulator. A test chip has been fabricated in CMOS 0.18 μm technology and tested to validate the full operation of the different proposed modes. Mohamad Sawan received the B.Sc. degree in electrical engineering from Université Laval, Canada in 1984, the M.Sc. and Ph.D. degrees, both in electrical engineering, from Université de Sherbrooke, Canada, in 1986 and 1990 respectively, and postdoctorate training from McGill University, Canada in 1991. He joined Ecole Polytechnique de Montréal in 1991 where he is currently a Professor in Microelectronics. His scientific interests are the design and test of mixed-signal (analog, digital and RF) circuits and systems, the digital and analog signal processing, the modeling, design, integration, assembly and validation of advanced wirelessly powered and controlled monitoring and measurement techniques. These topics are oriented toward the biomedical implantable devices and telecommunications applications. Dr. Sawan is a holder of a Canadian Research Chair in Smart Medical Devices. He is leading the Microelectronics Strategic Alliance of Quebec (Regroupement stratégique en microélectronique du Québec – ReSMiQ). He is founder of the Eastern Canadian IEEE-Solid State Circuits Society Chapter, the International IEEE-NEWCAS conference, and Polystim neurotechnologies laboratory at the Ecole Polytechnique de Montreal. He is cofounder of the International Functional Electrical Stimulation Society (IFESS), and the IEEE International Conference on Electronics, Circuits and Systems (ICECS). Dr. Sawan is involved in the committees of many national and international conferences and other scientific events. He published more than 350 papers in peer reviewed journals and conference proceedings and is awarded 6 patents. He is editor of the Springer Mixed-signal Letters, Distinguished Lecturer for the IEEE CAS Society, President of the biomedical circuits and systems (BioCAS) technical committee of the IEEE CAS Society, and he is representative of IEEE-CAS in the International Biotechnology council. He received the Barbara Turnbull 2003 award for spinal cord research, the Medal of Merit from Lebanon, and the Bombardier Medal from the French Association for the advancement of sciences. Dr. Sawan is Fellow of the Canadian Academy of Engineering, and Fellow of the IEEE. Annie Trépanier received her Bachelor of Engineering Degree in Electrical Engineering in 2002 and her Master of Applied Sciences Degree in Microelectronics in 2005 from the Ecole Polytechnique de Montreal as a member of the Cortivision team in the Polystim Neurotechnologies Laboratory. She held a summer job at Nortel Networks and trained at Mindready. She is currently employed at Matrox, Montreal. Jean-Luc Trépanier received his Bachelor of Engineering Degree in Electrical Engineering in 2000 and his Master of Applied Sciences Degree in Microelectronics in 2003 from the Ecole Polytechnique de Montreal where he was a member of the Cortivision team in the Polystim Neurotechnologies Laboratory. He started his first company, Olyxia inc., where he developed the soon to be released Cute Spider VoIP Network. He is also the founder and CEO of Nexyrius inc. which develops a new generation of embedded systems. Yves Audet received his M.Sc. degree from a joint program between the University of Sherbrooke, QC, Canada and Université Joseph Fourier in Grenoble, France. He completed his Ph.D. at Simon Fraser University, BC, Canada. He has been working for three years in Research and Development with Mitel Corporation before being hired as assistant professor at école Polytechnique of Montreal, QC, Canada, in 2001. His research interests are CMOS sensor arrays and mixed signal circuits. Roula Ghannoum received her Bachelor of Engineering Degree in Computer and Communications Engineering from the Lebanese American University, Byblos—Lebanon, in July 2005. She is currently pursuing her Master of Applied Sciences in Microelectronics at the Ecole Polytechnique de Montreal as a member of the Cortivision team in the Polystim Neurotechnologies Laboratory working on image sensors as part of a global project that aims at restoring sight to the visually incapacitated.     

Single DDCC Biquads with High Input Impedance and Minimum Number of Passive Elements

Two new configurations for the design of biquad filters with high input impedance are presented. The first configuration can synthesize low-pass and high-pass filter functions according to the passive components used. The second one can synthesize a band-pass filter function. The proposed configurations employ only one differential difference current conveyor (DDCC) as active elements and minimum number of passive elements, namely two resistors and two capacitors. Another filter topology based on DDCC is presented that allows modifying the quality factor without changing its natural frequency. All the filters enjoy low sensitivities. SPICE simulation results are given to confirm the validity of the analysis and to point out the high performance of the filters.Muhammed A. Ibrahim was born in Erbil, Iraq in 1969. He obtained his B.Sc. and M.Sc. degrees from Salahaddin University, Erbil, Iraq and Istanbul Technical University, Istanbul, Turkey in 1990 and 1999, respectively, all in electronics and communication engineering. Between 1992 and 1996 he worked as Research Assistant at Salahaddin University where he was later appointed as Assistant Lecturer in 1999. Since 2000 he has been studying for his Ph.D. degree in Electronics and Communication Engineering Program at Istanbul Technical University. His main research interests are CMOS circuit design, current-mode circuits and analog signal processing applications. He has more than 20 international journal and conference papers in scientific review.H. Hakan Kuntman received his B.Sc., M.Sc. and Ph.D. degrees from Istanbul Technical University in 1974, 1977 and 1982, respectively. In 1974 he joined the Electronics and Communication Engineering Department of Istanbul Technical University. Since 1993 he is a professor of electronics in the same department. His research interest include design of electronic circuits, modeling of electron devices and electronic systems, active filters, design of analog IC topologies. Dr. Kuntman has authored many publications on modelling and simulation of electron devices and electronic circuits for computer-aided design, analog VLSI design and active circuit design. He is the author or the coauthor of 76 journal papers published or accepted for publishing in international journals, 91 conference papers presented or accepted for presentation in international conferences, 99 turkish conference papers presented in national conferences and 10 books related to the above mentioned areas. Furthermore he advised and completed the work of 7 Ph.D. students and 31 M.Sc. students. Currently, he acts as the head of the Electronics and Communication Engineering Department in Istanbul Technical University. Dr. Kuntman is a member of the Chamber of Turkish Electrical Engineers (EMO).Oguzhan Cicekoglu received the B.Sc. and M.Sc. degrees from Bogazici University and the Ph.D. degree from Istanbul Technical University all in Electrical and Electronics Engineering in 1985, 1988 and 1996 respectively. He served as lecturer at the School of Advanced Vocational Studies Electronics Prog. of Bogazici University where he held various administrative positions between 1993 and 1999. He served also as part time lecturer at various institutions. He was with the Biomedical Engineering Institute of the Bogazici University between 1999 and 2001. He is currently Associate Professor at the Electrical and Electronics Engineering Department of the same University.His current research interests include analog circuits, active filters, analog signal processing applications and current-mode circuits. Oguzhan Cicekoglu is the author or co-author of 62 journal papers and about 90 international or local conference papers published or accepted for publishing in journals or conference proceedings.He served as the committee member in various scientific conferences and as reviewer in numerous journals including Analog Integrated Circuits and Signal Processing, IEEE CAS-I, IEEE CAS-II, International Journal of Electronics, Microelectronics Journal, Solid State Electronics and IEE Proceedings Pt.G.Oguzhan Cicekoglu is a member of the IEEE.     

New Four-Quadrant CMOS Current-Mode and Voltage-Mode Multipliers

In this paper, a four-quadrant current-mode multiplier based on a new squarer cell is proposed. The multiplier has a simple core, wide input current range with low power consumption, and it can easily be converted to a voltage-mode by using a balanced output transconductor (BOTA) [1]. The proposed four-quadrant current-mode and voltage-mode multipliers were confirmed by using PSPICE simulation and found to have good linearity with wide input dynamic range. For the proposed current-mode multiplier, the static power consumption is 0.671 mW, the maximum power consumption is 0.72 mW, the input current range is ± 60 μ A, the bandwidth is 31 MHz, the input referred noise current is 46 pA/√Hz, and the maximum linearity error is 3.9%. For the proposed voltage-mode multiplier, the static power consumption is 1.6 mW, the maximum power consumption is 1.85 mW, the input voltage range is ± 1V from ± 1.5V supply, the bandwidth is 25.34 MHz, the input referred noise voltage is 0.85 μV/√Hz, and the maximum linearity error is 4.1%. Mohammed A. Hashiesh was born in Elkharga, New Valley, Egypt, in 1979. He received the B.Sc. degree with honors from the Electrical Engineering Department, Cairo University, Fayoum-Campus, Egypt in 2001, and he received the M.Sc. degree in 2004 from the Electronics and Communication Engineering Department, Cairo University, Egypt. He is currently a Teacher Assistant at the Electrical Engineering Department, Cairo University, Fayoum-Campus. His research interests include analog CMOS integrated circuit design and signal processing, and digitally programmable CMOS analog building blocks. Soliman A. Mahmoud was born in Cairo, Egypt, in 1971. He received the B.Sc. degree with honors, the M.Sc. degree and the Ph.D. degree from the Electronics and Communications Department, Cairo University—Egypt in 1994, 1996 and 1999 respectively. He is currently an Assistant Professor at the Electrical Engineering Department, Cairo University, Fayoum-Campus. He has published more than 50 papers. His research and teaching interests are in circuit theory, fully integrated analog filters, high frequency transconductance amplifiers, low voltage analog CMOS circuit design, current-mode analog signal processing and mixed analog/digital programmable analog blocks. Ahmed M. Soliman was born in Cairo Egypt, on November 22, 1943. He received the B.Sc. degree with honors from Cairo University, Cairo, Egypt, in 1964, the M.S. and Ph.D. degrees from the University of Pittsburgh, Pittsburgh, PA., U.S.A., in 1967 and 1970, respectively, all in Electrical Engineering. He is currently Professor Electronics and Communications Engineering Department, Cairo University, Egypt. From September 1997–September 2003, Dr Soliman served as Professor and Chairman Electronics and Communications Engineering Department, Cairo University, Egypt. From 1985–1987, Dr. Soliman served as Professor and Chairman of the Electrical Engineering Department, United Arab Emirates University, and from 1987–1991 he was the Associate Dean of Engineering at the same University. He has held visiting academic appointments at San Francisco State University, Florida Atlantic University and the American University in Cairo. He was a visiting scholar at Bochum University, Germany (Summer 1985) and with the Technical University of Wien, Austria (Summer 1987). In 1977, Dr. Soliman was decorated with the First Class Science Medal, from the President of Egypt, for his services to the field of Engineering and Engineering Education. Dr Soliman is a member of the Editorial Board of Analog Integrated Circuits and Signal Processing. Presently Dr. Soliman is Associate Editor of the IEEE Transactions on Circuits and Systems I (Analog Circuits and Filters).     

FGMOS Current Mirror: Behaviour and Bandwidth Enhancement

This paper presents a high performance, resistively compensated low voltage current mirror using floating gate MOSFETs (FGMOS). The compensation technique desensitizes the output current and input compliance voltage with respect to the process generated variations in the threshold voltages of the mirroring transistors. Theoretical and simulation results exhibit an appreciable increase in bandwidth of the current mirror for this compensation technique. The operation of these circuits has been verified using PSpice simulations for 0.5 μ m CMOS technology at a supply voltage of ±0.75 V. A part of this paper has appeared in IEEE APCCAS 2002 and NSM 2003. S. Sharma was born on 6th July 1967 at village Bhagta, district Udhampur, J and K (India). He received MSc Physics (Electronics) degree from University of Jammu in 1991 and was awarded University Gold Medal. After qualifying NET (CSIR), he joined as Lecturer in 1995 in the department of Physics and Electronics of the same University. He is presently a Senior Lecturer and pursuing for Ph.D. degree in the area of Analog Integrated Circuits. He has eight papers published in National/International Conferences/Journals. He is a life member of IETE (India). S.S. Rajput was born on July 1, 1957, at village Bashir Pur, District Bijnor UP India. He received his B. E. in Electronics and Communication Engineering and M. E. in Solid State Electronics Engineering from University of Roorkee, Roorkee, India (Now IIT, Roorkee) in 1978 and 1981 respectively and was awarded University gold medal in 1981. He earned his Ph.D. degree from Indian Institute of Technology, Delhi in 2002 and his topic of research was “Low voltage current mode analog circuit structures and their applications”. He joined National Physical Laboratory, New Delhi, India as Scientist B in 1983, where he is presently serving as Scientist EII. He has worked for the design, development, testing and fabrication of an instrument meant for space exploration under the ISRO-NPL joint program for development of scientific instruments for the Indian Satellite SROSS-C and SROSS-C2 missions. His research interests include low voltage analog VLSI, instrument design for space applications, Digital Signal Processing, Fault tolerant design, and fault detection. He has chaired the many sessions in Indian as well as International conferences. He is Fellow member of IETE (India). He has been awarded best paper award for IETE Journal of Education for the year 2002. He has delivered many invited talks on Low Voltage Analog VLSI. Few tutorials have been presented in International Conferences on his Research Work. He has more than 30 publications in national and international journals. L.K. Mangotra was born on 14th April 1944 at Jammu, India. He received M.Sc. (Physics) from University of Kashmir in 1968 and Ph.D. (High Energy Physics) from University of Jammu in 1974. He worked as Assistant Director in Forensic Laboratory of J and K Govt. from 1974–78. He joined Physics Department, University of Jammu as Lecturer in 1978 and became Professor in 1988. He has 131 publications in International Journals and 41 papers in proceedings of International/National Conferences. He has number of visits to foreign Universities in connection with research and has been awarded various Fellowships. He is a member of various Professional/Academic/Administrative bodies. Presently, Prof. Mangotra is an Advisor to University of Jammu for Modernization of University Infrastructure and Principal Investigator for Jammu University and Coordinator of All India Universities in the International Collaborative research project “ALICE” in High Energy Physics sponsored by Department of Atomic Energy and Department of Science and Technology, Govt. of India. S.S. Jamuar was born on 27th November 1949. He received his BSc. Engineering Degree in Electronics and Communication from Bihar Institute of Technology, Sindri in 1967, M. Tech and Ph.D. in Electrical Engineering from Indian Institute of Technology, Kanpur, India in 1970 and 1977 respectively. He worked as Research Assistant, Senior Research Fellow and Senior Research Assistant from 1969 to 1975 at IIT Kanpur. During 1975–76, he was with Hindustan Aeronautics Ltd., Lucknow. Subsequently he joined the Lasers and Spectroscopy Group in the Physics Department at IIT Kanpur, where he was involved in the design of various types of Laser Systems. He joined department of Electrical Engineering of IIT Delhi in 1977, where he became Professor in 1991. He is presently Professor in the department of Electrical and Electronic Engineering Department, Faculty of Engineering, University Putra Malaysia, Malaysia. His area of research interest includes Electronic Circuit Design, Instrumentation and Communication systems. He is recipient of Meghnad Saha Memorial Award 1976 from IETE, Distinguished Alumni Award from BIT Sindri in 1999. Dr. Jamuar is senior member of IEEE and Fellow member of IETE (India). He is presently the Chair for CASS Chapter of IEEE Malaysia Section.     

On the Performance Analysis of a Class of Neuron Circuits

A new performance metric, Peak-Error Ratio (PER) has been presented to benchmark the performance of a class of neuron circuits to realize neuron activation function (NAF) and its derivative (DNAF). Neuron circuits, biased in subthreshold region, based on the asymmetric cross-coupled differential pair configuration and conventional configuration of applying small external offset voltage at the input have been compared on the basis of PER. It is shown that the technique of using transistor asymmetry in a cross-coupled differential pair performs on-par with that of applying external offset voltage. The neuron circuits have been experimentally prototyped and characterized as a proof of concept on the 1.5 μm AMI technology. Amit K. Gupta received his B.Tech. in Electrical Engineering from the Indian Institute of Technology Kanpur, India, in 2000 and the M.Sc. (Engg.) in Microelectronics from the Indian Institute of Science, Bangalore, India in 2004. He joined the Semiconductor Products Sector, Motorola (currently Freescale Semiconductor), India, in 2000, where he is currently working as a Design Engineer. His research interest includes low power analog circuit design and neuromorphic engineering. Navakanta Bhat received his B.E. in Electronics and Communication from University of Mysore in 1989, M.Tech. in Microelectronics from I.I.T. Bombay in 1992 and Ph.D. in Electrical Engineering from Stanford University, Stanford, CA in 1996. Then he worked at Motorola's Networking and Computing Systems Group in Austin, TX until 1999. At Motorola he worked on logic technology development and he was responsible for developing high performance transistor design and dual gate oxide technology. He joined Indian Institute of Science, Bangalore in 1999 where he is currently Assistant Professor in the Electrical Communication Engineering department. His current research is focused on Analog and RF Microsystems using CMOS and MEMS technology. The work includes process development, device design and modeling, circuit design. He has several research publications in international journals and conferences and 2 US patents to his credit. He is the recipient of the Young Engineer Award (2003) from the Indian National Academy of Engineering. He is currently the chair of the IEEE Electron Devices and Solid-State Circuits society, Bangalore chapter which has been recognized as the Outstanding Chapter of the Year (2003) by the IEEE SSC society.     

The Effects of Non-Idealities and Current Limitations on the Simulated Inductances Employing Current Conveyors

Active devices such as current conveyors play an essential role on the performance of simulated inductances. The effects of second-generation current conveyor (CCII) non-idealities on the proposed and on the previously published inductances are investigated, in which lossless inductances are realized. CCIIs like all active devices have terminal current limitations that can not be exceeded. Thus, the values of the applied input current sources for the proposed and previously published inductances depending on the passive elements values and applied signal frequency impose restrictions on the input current of the inductor. Erkan Yuce was born in 1969 in Nigde, Turkey. He received the B.Sc. degree from Middle East Technical University and M.Sc. degree from Pamukkale University in 1994 and 1998 respectively, all in Electrical and Electronics Engineering. He is currently Research Assistant and a Ph.D. student at the Electrical and Electronics Engineering Department of Bogazici University. His current research interests include analog circuits, active filters, synthetic inductors, voltage-mode current-mode circuits. He is the author or co-author of about 4 papers published in scientific journals or conference proceedings Oguzhan Cicekogluwas born in 1963 in Istanbul, Turkey. He received the B.Sc. and M.Sc. degrees from Bogazici University and the Ph.D. degree from Istanbul Technical University all in Electrical and Electronics Engineering in 1985, 1988 and 1996 respectively. He served as lecturer at the School of Advanced Vocational Studies Electronics Prog. of Bogazici University where he held various administrative positions between 1993 and 1999, and as part time lecturer at various institutions. He was with Biomedical Engineering Institute between 1999 and 2001. He is currently Associate Professor at the Electrical and Electronics Engineering Department of Bogazici University. His current research interests include analog circuits, active filters, analog signal processing applications and current-mode circuits. He is the author or co-author of about 150 papers published in scientific journals or conference proceedings. Oguzhan Cicekoglu is a member of the IEEE.     

Design and frequency/phase-noise analysis of a 10-GHz CMOS ring oscillator with coarse and fine frequency tuning

A 10-GHz CMOS ring oscillator that employs a multi-pass technique for boosting its frequency is proposed in this paper. The proposed circuit allows the tuning gain to be lowered by deploying the coarse/fine frequency tuning whilst maintaining wide frequency coverage. The small signal model of the proposed delay stage and the circuit operation are discussed in this paper. The time-variant analysis presented permits accurate prediction of the frequency tuning characteristic and the results have been verified by simulation. The phase noise analysis is also discussed in detail to provide better insight to the noise that is contributed by each transistor. The calculated results agreed well with that of the simulations. Hai Qi Liu was born in Jiangsu, China, in 1979. He received the B.S. and M.Sc. degrees, both in electrical engineering from the Tianjin University, Tianjin, China, in 2000, and Tongji University, Shanghai, China, in 2003, respectively. He is currently working toward the Ph.D. degree at the Nanyang Technological University, Singapore. His research focuses mainly on the design of fully integrated oscillators and Phase-Locked Loops for optical communication applications. His research interests also include RF frequency synthesizers and RF front-end designs for wireless applications. Wang Ling Goh obtained both her B.Eng and Ph.D. degrees from the department of Electrical and Electronic Engineering at the Queen’s University of Belfast (QUB) in United Kingdom. When working on her Ph.D., she was also engaged as a research associate at the Northern Ireland Semiconductor Research Centre (NISRC) at QUB. Dr Goh joined the School of Electrical and Electronic Engineering at the Nanyang Technological University (NTU) in Singapore as a lecturer in January 1996. She is now an Associate Professor in the Division of Circuits and Systems, School of Electrical & Electronic Engineering. Dr Goh has to-date co-authored 1 book, filed 13 patents (granted), and published about 60 research papers in international conferences and journals. Her research interests are in areas of silicon device processing technologies as well as digital and mixed-signal IC designs. Liter Siek received the B.A.Sc. degree from University of Ottawa, Ontario, Canada; the M.Eng.Sc. from University of New South Wales, Sydney, Australia; and the Ph.D. from Nanyang Technological University, Singapore. From 1981 to 1983 he was employed in several companies in the area of automation and control. From 1983 to 1985, he was with SGS, currently known as ST Microelectronics situated in Castelletto, Milan, Italy, where he worked in the central R&D Laboratories for Linear IC. From 1985 to 1987, he was with the same company situated in Singapore’s Asia Pacific Design Center. Since October 1988, he has been with Nanyang Technological University. His research interests are in the design of bipolar, CMOS and BiCMOS analog/mixed signal ICs. In addition, he has authored and co-authored 53 international journal/conference technical papers.     

A Novel Approach to Cell Coverage Area Determination for FDMA–CDMA Systems

There is no theoretical time or frequency restrictions on capacity in DS-CDMA systems. In these systems, the signal to interference ratio (SIR) has a major effect on capacity. Since an increase in the user SIR at the base station (BS) leads to higher capacity, transmission power control is employed. The nonuniform distribution of users in the network causes different quality of service (QOS) in distinct regions, therefore network resources may not be utilized properly. A dynamic distribution algorithm can be employed to balance the QOS delivered in different regions of the network. In this paper, a novel dynamic distribution algorithm is introduced. The proposed algorithm deactivates certain users when the network encounters an overload. By applying this policy, the required SIR can be maintained for the remaining users. F. Hendessi received a B.Sc. degree from Baluchestan University, Iran in 1986, and an M.Sc. degree from Isfahan University of Technology, Iran in 1988, both in Electrical Engineering. In 1993 he received a Ph.D. in Electrical Engineering from Carleton University, Ottawa, Ontario, Canada. He is currently an Assistant Professor in the Department of Electrical Engineering at Isfahan University of Technology. A. Ghayoori received B.Sc. and M.Sc. degrees in Electrical Engineering from Isfahan University of Technology, Isfahan, Iran, in 2001 and 2003, respectively. He is currently a Research Engineer with the ICT research center at IUT. T. A. Gulliver received a Ph.D. degree in Electrical and Computer Engineering from the University of Victoria, Victoria, BC, Canada in 1989. From 1989 to 1991 he was employed as a Defence Scientist at Defence Research Establishment Ottawa, Ottawa, ON, Canada. He has held academic positions at Carleton University, Ottawa, and the University of Canterbury, Christchurch, New Zealand. He joined the University of Victoria in 1999 and is a Professor in the Department of Electrical and Computer Engineering. He is a Senior Member of the IEEE and a member of the Association of Professional Engineers of Ontario, Canada. In 2002, he became a Fellow of the Engineering Institute of Canada. His research interests include information theory and communication theory, algebraic coding theory, cryptography, construction of optimal codes, turbo codes, spread spectrum communications, space-time coding and ultra wideband communications.     

Analog behavioral modeling by multi-companding and wavelet collocation method

In this paper, we develop a wavelet collocation method with multi-companding for behavioral modeling of analog circuits. In the multi-companding procedure, the nonlinear companding algorithm is developed to control the error distribution continuously, while the adaptive scheme is employed to reduce the number of used wavelets. Consequently, the proposed multi-companding algorithm can not only modify the modeling error distribution continuously but also decrease the number of basis functions efficiently. Moreover, the companding function generation is automatic and can be applied for the behavioral modeling of any analog circuits. Jun Tao received the B.S degree in electrical engineering from Fudan University, China, in 2002. Now she is currently working toward the Ph.D. degree in micro-electronic engineering at the Fudan University. Her research interest includes analog behavioral modeling, analog circuit simulation and DFM. Xuan Zeng (M97) received the B.Sc. and Ph.D. degrees in electrical engineering from Fudan University, Shanghai, China, in 1991 and 1997, respectively. She joined the Electrical Engineering Department, Fudan University in 1997 and became a full professor in Microelectronics Department in 2001. Now she serves as the Vice Director of ASIC & System State key Lab. and the Associate Head of Microelectronics Department Fudan University. She was a visiting professor in the Electrical Engineering Department, Texas A&M University, USA and Microelectronics Department of TU Delft, Netherland in 2002 and 2003 respectively. Her research interests include DFM, analog and mixed signal design automation (behavioral modeling, circuit simulation and analog layout generation), high speed interconnect analysis and design and ASIC design. Dr. Zeng received the Cross-Century Outstanding Scholar Award from the Ministry of Education of China in 2002. She was selected into “IT Top 10” in Shanghai China in 2003. She served in the technical program committee of IEEE/ACM ASP-DAC in 2000 and 2005. Dian Zhou received the B.S degree in physics and M.S degree in electrical engineering from Fudan University, China, in 1982 and 1985, respectively, and the Ph.D. degree in electrical and computer engineering from the University of Illinois in 1990. He joined the University of North Carolina at Charlotte as an assistant professor in 1990, where he became an associate professor in 1995. He joined the University of Texas at Dallas as a full professor in 1999, and joined Fudan university as a Changjiang Professor in 2003 (on-leave from the University of Texas at Dallas). Currently, he serves as the dean of Microelectronics School, director of National Key Lab. on ASICs and Systems, and director of Miro-nano-electronics Innovation Platform at Fudan University. His research interests include: High-speed VLSI systems, CAD tools, mixed-signal ICs, and algorithms. Charles Chiang received his Bachelor degrees from the Department of Political Science, Tunghai University at Taichung, Taiwan in 1980, and Department of Computer Science, New Mexico State University, Las Cruces, New Mexico in 1986. Then he had his Masters and Ph.D. degree from the Department of Electrical Engineering and Computer Science, Northwestern University, Illinois in 1988 and 1991, respectively. After working at IBM and EDA companies for 10 years, he joined the Advanced Technology Group at Synopsys, Inc. in 2001. His research interests include routing, placement, floorplan, and signal integrity. His main research focus is now on design for manufacturability (DFM). Dr. Chiang has been a Senior Member of IEEE since 1998. He received the Superior Design Recognition award and the ADAL award from IBM Rochester in 1993 and 1994, respectively. He is one of the top 15 winners with new patent filing in 2005 and 2006 in Synopsys. He has served on the technical committee of ICCAD from 2004 to 2006, on that of Field Programming Logic (FPL) from 2002 to 2003, as well as on the committee of ASP-DAC in 2007. He has published more than 40 technical papers and filed 10 US patents.     

A Realistic Timing Test Model and Its Applications in High-Speed Interconnect Devices

This paper extends the timing test model in [5] to be more realistic by including the effects of the test fixtures between a device under test and a tester. The paper enables analyzing the trade-offs that arise between the predicted yield and the required overall test environment timing accuracy (OTETA) which involves the tester overall timing accuracy (OTA) and the test fixtures' impacts. We specifically focus on the application of the extended model to predict the test yield of standard high-speed interconnects, such as PCI Express, Parallel/Serial RapidIO, and HyperTransport. The extended model reveals that achieving an actual yield of 80% with a test escape of 300 DPM (Defects Per Million) requires an equivalent OTETA that is about half the acceptable absolute limit of the tested parameter. Baosheng Wang received his B.S. degree from Beijing University of Aeronautics and Astronautics (BUAA), Beijing, P.R. China, in 1997 and M.S. degree from Precision Instrument & Mechanical Engineering from the Tsinghua University, Beijing, P. R. China in 2000. In 2005, he received his Ph.D. degree in Electrical Engineering from the University of British Columbia (UBC), Vancouver, BC, Canada. During his Master study, he was doing MEMS, Micro Sensors and Digital Signal processing. From 2000 to 2001, he worked in Beijing Gaohong Telecommunications Company as a hardware engineer in ATM technology. Currently, he is a Design-for-Test (DFT) engineer at ATI Technologies Inc., Markham, Ontario, Canada. He publishes widely at international conferences and journals. His primary research interests are time-driven or timing-oriented testing methodologies for System on-a-Chip (SoC). These fields include test time reduction for SRAMs, accelerated reliability test for non-volatile memories, yield analysis for SoC timing tests, SoC path delay timing characterization and embedded timing measurements. Andy Kuo is currently a Ph.D student of System on a Chip (SoC) Research Lab at the Department of Electrical and Computer Engineering, University of British Columbia. He received his M.A.Sc. and B.A.Sc in electrical and computer engineering from University of British Columbia and University of Toronto in 2004 and 2002 respectively. His research interests include high-speed signal integrity issues, jitter measurement, serial communications. Touraj Farahmand received the B.Sc. degree in Electrical Engineering from Esfahan University of Technology, Esfahan, Iran in 1989 and the M.Sc. in Control Engineering from Sharif university of Technology, Tehran, Iran in 1992. After graduation, he joined the Electrical and Computer Research center of Esfahan University of Technology where he was involved in the DSP algorithm development and design and implementation of the control and automation systems. Since October 2001, he has been working in the area of high-speed signal timing measurement at SoC (System-on-a-Chip) lab of UBC (University of British Columbia) as a research engineer. His research interests are signal processing, jitter measurement, serial communication and control. André Ivanov is Professor in the Department of Electrical and Computer Engineering, at the University of British Columbia. Prior to joining UBC in 1989, he received his B.Eng. (Hon.), M. Eng., and Ph.D. degrees in Electrical Engineering from McGill University. In 1995–96, he spent a sabbatical leave at PMC-Sierra, Vancouver, BC. He has held invited Professor positions at the University of Montpellier II, the University of Bordeaux I, and Edith Cowan University, in Perth, Australia. His primary research interests lie in the area of integrated circuit testing, design for testability and built-in self-test, for digital, analog and mixed-signal circuits, and systems on a chip (SoCs). He has published widely in these areas and holds several patents in IC design and test. Besides testing, Ivanov has interests in the design and design methodologies of large and complex integrated circuits and SoCs. Dr. Ivanov has served and continues to serve on numerous national and international steering, program, and/or organization committees in various capacities. Recently, he was the Program Chair of the 2002 VLSI Test Symposium (VTS'02) and the General Chair for VTS'03 and VTS'04. In 2001, Ivanov co-founded Vector 12, a semiconductor IP company. He has published over 100 papers in conference and journals and holds 4 US patents. Ivanov serves on the Editorial Board of the IEEE Design and Test Magazine, and Kluwer's Journal of Electronic Testing: Theory and Applications. Ivanov is currently the Chair of the IEEE Computer Society's Test Technology Technical Council (TTTC). He is a Golden Core Member of the IEEE Computer Society, a Senior Member of the IEEE, a Fellow of the British Columbia Advanced Systems Institute and a Professional Engineer of British Columbia. Yong Cho received the B.S. degree from Kyung Pook National Unviersity, Korea, in 1981 and the M.S. degree from in electrical and computer engineering from the University of South Carolina, Columbia, S.C., in 1988 and the Ph.D. degree in electrical engineering and applied physics from Case Western Reserve University, Cleveland, OH, in 1992. He is currently a Professor with the Department of Electronics Engineering, Konkuk University, Seoul, Korea. His recent research interests include SoC Design and Verification, H/W and S/W co-design, and embedded programming on SoC. Sassan Tabatabaei received his PHD in Electrical Engineering from the University of British Columbia, Vancouver, Canada in 2000. Since then, he has held several senior technical positions at Vector12 Corp, Guide Technology, and Virage Logic. His professional and research interests include mixed-signal design and test, and signal integrity and jitter test methodologies for high-speed circuits and multi-Gbps serial interfaces. He has published several papers and holds a US patent in the area of timing and jitter measurement. Currently, he holds the position of the director for embedded test at Virage Logic Corporation.     

Low-Cost Testing of 5 GHz Low Noise Amplifiers Using New RF BIST Circuit

This paper presents a new low-cost RF BIST (Built-In Self-Test) scheme that is capable of measuring input impedance, gain, noise figure and input return loss for a low noise amplifier (LNA) in RF systems. The RF BIST technique requires an additional RF amplifier and two peak detectors, and its output is a DC voltage level. The BIST circuit is designed using 0.18 μm SiGe technology. The test technique utilizes output DC voltage measurements and these measured values are translated into the LNA specifications such as input impedance and gain using the developed mathematical equations. Simulation results are presented for an LNA working at 5 GHz. Measurement data are compared with simulation results to validate the developed mathematical equations. The technique is simple and inexpensive. Jee-Youl Ryu received the BS and MS degrees in 1993 and 1997 from Pukyong National University in Electronic Engineering, Pusan, South Korea respectively. He also received the PhD degree in 2004 from Arizona State University in Electrical Engineering, Arizona, USA. He is currently with Samsung SDI Co., Ltd. His current research interests include RF IC design and testing, MMIC design and testing, analog IC design and testing, passives modeling, testing and analysis, and MEMS technology. Dr. Bruce Kim received the B.S.E.E. degree from the University of California, Irvine in 1981, the M.S. degree in electrical engineering from the University of Arizona in 1985, and the Ph.D. degree in electrical engineering from Georgia Institute of Technology in 1996. He was an Associate Professor at Arizona State University until 2005. Currently, he is an Associate Professor at The University of Alabama. His current research interests include RF IC testing, MEMS integration and VLSI circuits. He has been working on SiP testing technologies, package electrical modeling, and measurements of RF IC packages. Dr. Kim is a 1997 recipient of the National Science Foundation's CAREER Award and received the Meritorious Award from IEEE. He serves as the Chair of the IEEE CPMT Society TC-Electrical Test, associate editor of the IEEE Transactions on Advanced Packaging, associate editor of Design and Test of Computers, and program committee member of Electronic Components and Technology Conference. He is a senior member of IEEE.     

Performance of multiuser network-aware prefetching in heterogeneous wireless systems

We study the performance of multiuser document prefetching in a two-tier heterogeneous wireless system. Mobility-aware prefetching was previously introduced to enhance the experience of a mobile user roaming between heterogeneous wireless access networks. However, an undesirable effect of multiple prefetching users is the potential for system instability due to the racing behavior between the document access delay and the user prefetching quantity. This phenomenon is particularly acute in the heterogeneous environment. We investigate into alleviating the system traffic load through prefetch thresholding, accounting for server queuing prioritization. We propose a novel analysis framework to evaluate the performance of the thresholding approach. Numerical and simulation results show that the proposed analysis is accurate for a wide variety of access, service, and mobility patterns. We further demonstrate that stability can be maintained even under heavy usage, providing both the same scalability as a non-prefetching system and the performance gain associated with prefetching. A preliminary version of this article was presented in the International Conference on Quality of Service in Heterogeneous Wired/Wireless Networks (QShine) 2006. This work was supported in part by the Natural Sciences and Engineering Research Council of Canada and Bell Canada through its Bell University Laboratories R&D program. Ben Liang received honors simultaneous B.Sc. (valedictorian) and M.Sc. degrees in electrical engineering from Polytechnic University in Brooklyn, New York, in 1997 and the Ph.D. degree in electrical engineering with computer science minor from Cornell University in Ithaca, New York, in 2001. In the 2001–2002 academic year, he was a visiting lecturer and post-doctoral research associate at Cornell University. He joined the Department of Electrical and Computer Engineering at the University of Toronto as an Assistant Professor in 2002. His current research interests are in mobile networking and multimedia systems. He received an Intel Foundation Graduate Fellowship in 2000 toward the completion of his Ph.D. dissertation, the Best Paper Award at the IFIP Networking conference in 2005, and the Runner-up Best Paper Award at the International Conference on Quality of Service in Heterogeneous Wired/Wireless Networks in 2006. He is a senior member of IEEE and a member of ACM and Tau Beta Pi. He serves on the organizational and technical committees of a number of major conferences each year. Stephen Drew received his B.A.Sc with honours in Computer Engineering from the University of Waterloo in 2003, and his M.A.Sc in Electrical Engineering at the University of Toronto in 2005 under the supervision of Ben Liang of the Communications group. He is currently employed by General Dynamics Canada, in the engineering research and development team. Da Wang is a third year Electrical Engineering student at the University of Toronto. He has been a recipient of the Adel S. Sedra Outstanding Student Award, the IEEE Canada-Toronto Section Scholarship and the Nortel Institute Undergraduate Scholarship. He held an NSERC award for the summer of 2005.