A micropower CMOS continuous-time filter with on-chip automatic tuning

This paper presents a CMOS implementation of a low-voltage micropower G/sub m/-C biquad with on-chip automatic tuning. The filter is suitable for any kind of application involving low-frequency ranges, and very low-power consumption, such as biomedical devices. The operational transconductance amplifier (OTA) is implemented with the transistors working in the weak inversion saturation region, thus allowing the use of very small currents that minimize the power consumption. The aspect ratios are small enough not to degrade the frequency response. The tuning algorithm is based on amplitude tracking. The filter output amplitude is quantized using a low-power amplifier and an asymmetric comparator. A digital controller varies the tuning parameters until the maximum quantized amplitude is found. The system works down to a voltage supply of 1.75 V. The center frequency is tunable over one and a half decades, from 300 Hz to 10 kHz for bias currents changing from 6 to 200 nA and a 20-pF integrating capacitance, giving an overall filter accuracy of up to 99.55%. The power consumption of the second-order filter including the common-mode correction circuitry is in the order of 200 nW for the 10-nA bias current. It exhibits a dynamic range of 54 dB and occupies an area of 0.06 mm/sup 2/ excluding the area of the integrating capacitances.     

An elliptic continuous-time CMOS filter with on-chip automatic tuning

A voice-band continuous-time filter is described which was designed based on the technique of fully balanced networks and was fabrication in a 3.5-/spl mu/ CMOS technology. The filter implements a fifth-order elliptic low-pass transfer function with 0.05-dB passband ripple and 3.4 kHz cutoff frequency. A phase-locked loop control system fabricated on the same chip automatically references the frequency response of the filter to an external fixed clock frequency. The cutoff frequency was found to vary by less than 0.1% for an operating temperature range of 0-85/spl deg/C. The absolute value accuracy of the cutoff frequency was 0.5% (standard deviation). With /spl plusmn/5-V power supplies the measured dynamic range of the filter was approximately 100 dB.     

A 60-mW 200-MHz continuous-time seventh-order linear phase filter with on-chip automatic tuning system

A full CMOS seventh-order linear phase filter based on g/sub m/-C biquads with a -3-dB frequency of 200 MHz is realized in 0.35-/spl mu/m CMOS process. The linear operational transconductance amplifier is based on complementary differential pairs in order to achieve both low-distortion figures and high-frequency operation. The common-mode feedback (CMFB) employed takes advantage of the filter architecture; incorporating the load capacitors into the CMFB loop improves further its phase margin. A very simple automatic tuning system corrects the filter deviations due to process parameter tolerances and temperature variations. The group delay ripple is less than 5% for frequencies up to 300 MHz, while the power consumption is 60 mW. The third-harmonic distortion is less than -44 dB for input signals up to 500 mV/sub pp/. The filter active area is only 900 /spl times/ 200 /spl mu/m/sup 2/. The supply voltages used are /spl plusmn/1.5 V.     

A 10.7-MHz 68-dB SNR CMOS continuous-time filter with on-chipautomatic tuning

A maximally flat 10.7-MHz fourth-order bandpass filter with an on-chip automatic tuning system is presented. The signal-to-in-band integrated noise ratio (SNR) of the automatically tuned filter is around 68 dB. The third intermodulation distortion (IM3) is lower than -40 dB for a two-tone input signal of 3.2 V peak to peak (V_p-p). The complete system operates with supply voltages of ±2.5 V. The power consumption of the system is 220 mW. All this has been achieved due to the use of a low-distortion transconductor, the development of a high-frequency CMOS resistor, and the realization of an advanced on-chip automatic tuning system for both frequency and bandwidth control. The chip has been fabricated in a standard 1.5-μm n-well CMOS process     

A ±1.5-V, 4-MHz CMOS continuous-time filter with asingle-integrator based tuning

A 4-MHz, fifth-order elliptic low-pass Gm-C filter is described whose characteristics are tuned by an on-chip automatic tuning circuit. The tuning circuit uses only one integrator as the master of tuning instead of problematic voltage controlled oscillator (VCO) and voltage controlled filter (VCF). MOS transistors in linear operation region perform the voltage-to-current conversion in an operational transconductance amplifier, and thereby we achieved ±1.5 V operation. A prototype filter was implemented in a 0.8-μm double-poly, double-metal CMOS process. The filter exhibits the dynamic range of 57.6 dB and dissipates 10 mW with ±1.5-V supply. The stopband attenuation is better than 45.0 dB and the passband ripple is smaller than 1.0 dB     

A CMOS G_m-C complex filter with on-chip automatic tuning for wireless sensor network application

A G_m-C complex filter with on-chip automatic tuning for wireless sensor networks is designed and implemented using 0.18μm CMOS process.This filter is synthesized from a low-pass 5th-order Chebyshev RLC ladder filter prototype by means of capacitors and fully balanced transconductors.A conventional phase-locked loop is used to realize the on-chip automatic tuning for both center frequency and bandwidth control.The filter is centered at 2 MHz with a bandwidth of 2.4 MHz.The measured results show that the filter provides more than 45 dB image rejection while the ripple in the pass-band is less than 1.2 dB.The complete filter including on-chip tuning circuit consumes 4.9 mA with 1.8 V single supply voltage.     

A 3-V continuous-time filter with on-chip tuning for IS-95

This paper describes a low-voltage channel selection analog front end with continuous-time low-pass filters and on-chip tuning for a receiver in an IS-95 cellular phone. The filters were realized as balanced seventh-order elliptical g_mC filters to achieve low current consumption. The transconductors were realized by using second-generation current conveyors (CCII) and resistors to achieve good intermodulation distortion performance. A novel CCII circuit topology was developed to fulfil the low supply-voltage requirement. The cutoff frequency tuning was implemented with capacitance matrices and a time-domain master-slave tuning circuit     

Design of low-voltage CMOS continuous-time filter with on-chipautomatic tuning

A technique for designing a low-voltage continuous-time active filter is presented in this paper. In this technique, current sources are added to the inverting or noninverting op-amp terminals such that the op-amp input common-mode voltages can be set close to one of the supply rails to allow low-voltage operation. An automatic frequency and Q tuning technique is proposed for tuning the active filter using programmable capacitor arrays (PCAs). The proposed tuning technique does not require any peak detectors, which are difficult to implement at a low supply voltage. Instead, it uses a few analog comparators, a digital comparator, and a few binary counters to adjust the PCAs. To demonstrate the proposed techniques, a 1-V 1-MHz second-order filter fabricated in a conventional 1.2-μm CMOS process is presented. For a 5-kHz input signal, the filter achieves a THD of -60.2 dB for a peak-to-peak output voltage of 600 mV. The frequency tuning range is between 585 kHz and 1.325 MHz. The measured power consumption for the filter alone consumes about 0.52 mW and for the entire system consumes about 1.6 mW for a supply voltage of ±0.5 V     

A 2-V/sub pp/ 80-200-MHz fourth-order continuous-time linear phase filter with automatic frequency tuning

A CMOS 80-200-MHz fourth-order continuous-time 0.05/spl deg/ equiripple linear phase filter with an automatic frequency tuning system is presented. An operational transconductance amplifier based on transistors operating in triode region is used and a circuit that combines common-mode feedback, common-mode feedforward, and adaptive bias is introduced. The chip was fabricated in a 0.35-/spl mu/m process; filter experimental results have shown a total harmonic distortion less than -44 dB for a 2-V/sub pp/ differential input with a single 2.3-V power supply. The group delay ripple is less than 4% for frequencies up to 1.5 f/sub c/. The frequency tuning error is below 5%.     

A low power Gm-C filter with on-chip automatic tuning for a WLAN transceiver

正A sixth-order Butterworth Gm-C low-pass filter(LPF) with a continuous tuning architecture has been implemented for a wireless LAN(WLAN) transceiver in 0.35μm CMOS technology.An interior node scaling technique has been applied directly to the LPF to improve the dynamic range and the structure of the LPF has been optimized to reduce both the die size and the current consumption.Measurement results show that the filter has 77.5 dB dynamic range,16.3 ns group delay variation,better than 3%cutoff frequency accuracy,and 0 dBm passband IIP3.The whole LPF with the tuning circuit dissipates only 1.42 mA(5 MHz cutoff frequency) or 2.81 mA(10 MHz cutoff frequency) from 2.85 V supply voltage,and only occupies 0.175 mm~2 die size.     

A low power Gm-C filter with on-chip automatic tuning for a WLAN transceiver

A sixth-order Butterworth Gm-C low-pass filter(LPF)with a continuous tuning architecture has been implemented for a wireless LAN(WLAN)transceiver in 0.35 μm CMOS technology.An interior node scaling technique has been applied directly to the LPF to improve the dynamic range and the structure of the LPF has been optimized to reduce both the die size and the current consumption.Measurement results show that the filter has 77.5 dB dynamic range,16.3 ns group delay variation,better than 3% cutoff frequency accuracy,and 0 dBm passband IIP3.The whole LPF with the tuning circuit dissipates only 1.42 mA(5 MHz cutoff frequency)or 2.81 mA(10 MHz cutoff frequency)from 2.85 V supply voltage,and only occupies 0.175 mm2 die size.     

A 1.6-GHz CMOS PLL with on-chip loop filter

A 1.6-GHz phase locked loop (PLL) has been fabricated in a 0.6-μm CMOS technology. The PLL consists of an LC-tank circuit, divider, phase detector with charge pump, and an on-chip passive loop filter. When the oscillator is open loop, it exhibits -115 dBc/Hz phase noise at a 600-kHz offset from the carrier. The PLL occupies an active area of 1.6 mm² and dissipates 90 mW from a single 3-V supply     

A 200-MHz seventh-order equiripple continuous-time filter by designof nonlinearity suppression in 0.25-μm CMOS process

Seventh-order equiripple filter with cutoff frequency of 200 MHz is developed in CMOS 0.25-μm process. A new design method has been adopted to obtain enough accuracy and linearity in high-frequency operation. Optimal device sizes are determined, which maximize the accuracy. The most suitable filter configuration is determined, which suppresses the influence of the nonlinearity of the transconductors over the linearity of the filter. Experimental results satisfied group delay variation of ±5% and achieved total harmonic distortion of less than 1% for 800 mV_ppd differential input     

On-chip automatic tuning based on amplitude detection and its application in CMOS continuous-time filters

This paper describes the results of investigation of a continuous-time CMOS voltage controlled IC filter using amplitude detectors in the tuning scheme in the form of an amplitude-locked loop. This tuning scheme is used to stabilize the filter characteristics. A prototype 20-kHz fifth-order Chebyshev low-pass filter with 0.1-dB passband ripple was realized to study the performance of the tuning scheme. Voltage controlled integrators were used as building blocks, and the design details of these integrators, whose unity-gain frequency can be varied from 8 to 32 kHz are given. Two amplitude detector circuits—a precision rectifier and an averaging rectifier-were used to test the tuning scheme. The filter cutoff frequency was held within 1% of its room temperature value over the temperature range of 0° to 70°C. All the circuits were fabricated in a standard 3-micron double-metal p-well CMOS process.     

A digital automatic tuning technique for high-order continuous-time filters

A digital automatic tuning technique for high-order continuous-time filters is proposed. Direct tuning of overall response is achieved without separating individual biquad sections, eliminating switches and their parasitics. Output phase of each biquad section is tuned to known references, which are generated by a frequency synthesizer. The core tuning circuit consists of D flip-flops (DFF) and simple logic gates. DFFs are utilized to perform binary phase detection. Frequency and quality factor tuning loops for each biquad are controlled digitally, providing more stable tuning by activating only one loop at a given time. The tuning system was verified by a prototype sixth-order bandpass filter which was fabricated in a conventional 0.5 /spl mu/m CMOS process with /spl plusmn/1.5 V power supply.     

1.5-V square-root domain second-order filter with on-chip tuning

A novel square-root domain (SRD) second order filter with automatic tuning control is described. The tuning system is based on a master-slave configuration, where the master is a SRD current-mode magnitude locked loop. The control circuitry allows tuning of the cut-off frequency as well as the quality factor and gain of the filter. The basic building blocks of the complete system are implemented employing a design strategy based on the inherent nonlinear characteristic of Class-AB linear transconductors. A proper biasing scheme in such transconductors leads to operation with very low supply voltages (as low as V/sub GS/+2V/sub DSsat/). Simulation and numerical results together with measurements from a fabricated prototype in a 0.8-/spl mu/m CMOS technology are included in order to validate the design technique proposed.     

A 48-16-MHz CMOS SC decimation filter

This paper presents a CMOS switched-capacitor decimation filter for prefiltering operations in video communications systems, reducing the complexity of continuous-time antialiasing filters and alleviating dynamic range requirements of analog-to-digital converters. As a consequence of the structure's low sensitivity to process variations, predicted by theory and verified in the laboratory by measurements on all samples of the same batch, it was possible to apply capacitor arrays having minimum feasible size units of 100 fF to implement the filter coefficients, leading to substantial savings in power consumption. Implemented in a standard 0.8-/spl mu/m CMOS process with poly-poly capacitors, the experimental device samples the incoming continuous-time analog signal at 48 MHz and presents a filtered sampled-data output at 16 MHz, with a measured pass-band deviation smaller than 0.22 dB up to the cutoff frequency of 3.6 MHz, output noise power spectrum of 1.1 nV/sub RMS///spl radic/(Hz) and a signal handling ability of 1.4 V/sub pp/, resulting in a dynamic range of 48 dB, meeting the usual specifications for video-frequency signal processing.     

Gyrator video filter IC with automatic tuning

A single-chip gyrator filter for separating the components of the video signal in a TV receiver is described which is suitable for mass production in a standard bipolar process (f/SUB T//spl ap/400 MHz). The 11 mm/SUP 2/ filter chip operates at frequencies up to 10 MHz, requires no tuning or alignment and has Q-factors which are stable with temperature. The IC contains an automatic tuning system which tunes the five resonators of the filter by aligning an auxiliary gyrator resonator with the crystal oscillator present in the color decoder of a TV receiver. Problems of matching the frequencies of the individual gyrator resonators are discussed, showing how alignment accuracy of 0.5 percent can be obtained when resistivities and specific capacitances have production spreads of at least 10 percent. Various gyrator circuit configurations are given which minimize the circuit complexity and, hence, the chip area. Computer aided design techniques for the filter using geometrically scaled models and macromodeling are presented and it is shown how a complete simulation of the chip led to a significant improvement in bandstop performance. Finally, the measured responses are presented and the filter performance is discussed in the light of present-day requirements.     

A 1-V 1.8-MHz CMOS switched-opamp SC filter with rail-to-railoutput swing

A low-voltage switched capacitor (SC) filter operated from a single 1 V supply and realized in a standard 0.5-μm CMOS technology is presented. Proper operation is obtained using the switched-opamp technique without any clock voltage multiplier or low-threshold devices. This makes the circuit compatible with future deep submicrometer technology. As opposed to previous switched-opamp implementations, the filter uses a fully differential topology. This allows operation with a rail-rail output swing and reduction of the number of opamps required to build high order infinite impulse response (IIR) filters. On the other hand, a low-voltage common-mode feedback (CMFB) circuit is required. In addition, the circuit uses an opamp which is only partially turned off during the off phase. This enables an increase in the maximum sampling frequency. The filter implements a bandpass response (f_s/f _o=4, Q=7) and it has been characterized with a 1.8 MHz sampling frequency. Its power consumption is about 160 μW. The filter is still fully functional down to 0.9 V supply voltage