In-situ monitoring of dry corrosion degradation of au ball bonds to al bond pads in plastic packages during HTSL

The ageing of Au ball bonds to Al bond pads during HTSL is studied by in-situ monitoring of the contact resistance. Unless the introduction of contact failures, the initial degradation of the ball bond resistance is independent of the moulding compound.     

Study of die bond voids on memory semiconductor devices in 24-L cerquad packages

Die bond voids were encountered in the eutectic die-attachment of memory products. The failures observed were characterized by the depletion of the Au layer of the base substrate thus exposing the underlying bare ceramic. An evaluation carried out showed that the voids encountered were not related to the Au thickness of the base substrate. Instead, the quality of the Au layer would affect eutectic wettability and percentage of die bond voids over the intended contact area under the die. Subsequent study identified oxide contaminant to be the cause of the die bond voids and showed that units with dice that had been chemically treated to remove the oxide layer were free of die bond voids. Units with untreated die backside were found to have a higher percentage of Si in the Au-Si bond while units with treated backside were found to have a Au-Si com-position closer to the eutectic point. To prevent oxide growth during high temperature exposure, a Au-Si alloying process in a N₂/H₂ reducing gas ambient was investigated. The results showed that no die bond voids were encountered in the die bonding process under this condition.     

Scanning electron microscopy study of the cross section of intermetallic compound in the solder ball on the plastic ball grid array package following reliability tests

The 63Sn-37Pb solder ball (φ=300 μm) was attached to gold-nickel-plated plastic ball grid array (PBGA) substrates, with gold and nickel thicknesses of 0.6 μm and 7 μm, respectively. The thickness of the intermetallic compound (IMC) in solder balls was measured following each instance of infrared (IR) reflow (90 sec at 230 °C), level II preconditioning, a pressure cooking test (for 96 h or 168 h), and a temperature cycle test (with 500 or 1,000 cycles). Scanning electron microscopy (SEM) was used to identify the cross-section sites of the solder balls following testing. Following all the reliability tests, the IMC demonstrated that an IMC thickness exceeding 5 μm will reduce the solder ball shear strength owing to diffusion of Ni into the solder balls.     

A simple moisture diffusion model for the prediction of optimal baking schedules for plastic SMD packages

The moisture concentration at the chip surface is the important parameter for the moisture sensitivity of the P-MQFP80 product considered here. When the critical moisture concentration at the die surface is reached, delamination occurs after soldering shock, e.g at 240°C. This critical moisture concentration, which can be determined by experiments conducted at 30°C/60% relative humidity (RH) followed by soldering shock, allows to predict the product’s moisture performance at other ambient conditions. In the case studied here, prediction was done at a customer use condition of 30°C/85% RH. Furthermore, this work showed that preconditioning of plastic packages not only induces the onset of delamination at the die surface but it appears to weaken the adhesion at this interface as well. As a result, delamination failure starts to occur earlier (i.e. within shorter moisture exposure time) in the devices tested after subsequent thermal cycling stress test. A simple moisture diffusion analytical model is proposed here for predicting the optimal baking schedules for plastic SMD packages.     

A methodology for identification of fingerprints based on Gabor filter

This work presents an automatic fingerprint identification system using a coefficient map in the power spectrum based on Gabor filter. This filter was created by Dennis Gabor in 1946 and is being used in many biometric technologies. The fingerprint core is found by pixel neighborhood technique. Around the core, the input image is divided in quadrants where information about texture orientation in three different Gabor filter directions is extracted. The angles used are 0, 45 and 90 degrees. It is accomplished convolutions among such Gabor filter orientations with each quadrant of the input image through the Fast Fourier Transform routine. After that, it is needed to identify the image in the frequency domain and the power spectrum is done. The maximum coefficient of the power spectrum is found and a map of forty coefficients is created around this maximum coefficient. That map is summed and divided by the maximum coefficient. Each result is an identifier of the image. Accomplishing such method using three Gabor filter orientations convoluted with the quadrants of the input image results in twelve identifiers. Those twelve identifiers are compared in the matching process. Experimental results demonstrate the good efficiency of the methodology for fingerprint images of good quality.     

Die degradation effect on aging rate in accelerated cycling tests of SiC power MOSFET modules

In order to distinguish the die and bond wire degradations, in this paper both the die and bond wire resistances of SiC MOSFET modules are measured and tested during the accelerated cycling tests. It is proved that, since the die degradation under specific conditions increases the temperature swing, bond wires undergo harsher thermo-mechanical stress than expected. The experimental results confirm the die-related thermal failure mechanism. An improved degradation model is proposed for the bond-wire resistance increase in case of die degradation.     

Intermetallic compounds formed during the reflow and aging of Sn-3.8Ag-0.7Cu and Sn-20In-2Ag-0.5Cu solder ball grid array packages

After reflow of Sn-3.8Ag-0.7Cu and Sn-20In-2Ag-0.5Cu solder balls on Au/Ni surface finishes in ball grid array (BGA) packages, scallop-shaped intermetallic compounds (Cu_0.70Ni_0.28Au_0.02)₆Sn₅ (IM1a) and (Cu_0.76Ni_0.24)₆(Sn_0.86In_0.14)₅ (IM1b), respectively, appear at the interfaces. Aging at 100°C and 150°C for Sn-3.8Ag-0.7Cu results in the formation of a new intermetallic phase (Cu_0.70Ni_0.14Au_0.16)₆Sn₅ (IM2a) ahead of the former IM1a intermetallics. The growth of the newly appeared intermetallic compound, IM2a, is governed by a parabolic relation with an increase in aging time, with a slight diminution of the former IM1a intermetallics. After prolonged aging at 150°C, the IM2a intermetallics partially spall off and float into the solder matrix. Throughout the aging of Sn-20In-2Ag-.5Cu solder joints at 75°C and 115°C, partial spalling of the IM1b interfacial intermetallics induces a very slow increase in thickness. During aging at 115°C for 700 h through 1,000 h, the spalled IM1b intermetallics in the solder matrix migrate back to the interfaces and join with the IM1b interfacial intermetallics to react with the Ni layers of the Au/Ni surface finishes, resulting in the formation and rapid growth of a new (Ni_0.85Cu_0.15)(Sn_0.71In_0.29)₂ intermetallic layer (IM2b). From ball shear tests, the strengths of the Sn-3.8Ag-0.7Cu and Sn-20In-2Ag-0.5Cu solder joints after reflow are ascertained to be 10.4 N and 5.4 N, respectively, which drop to lower values after aging. An erratum to this article is available at .     

Impact of the number of chips on the reliability of the solder balls for wire-bonded stacked-chip ball grid array packages

This investigation examines how the number of chips affects the reliability of solder balls for wire-bonded stacked-chip ball grid array packages under thermal cycling tests. The studied objects were packages with one, two, three and four stacked chips. Three-dimensional finite element analysis was utilized to simulate the stress/strain behavior of all studied packages. Two kinds of properties of 63Sn/37Pb eutectic solder were employed individually in the finite element analyses. One property of the solder was assumed to exhibit the elastic–plastic–creep behavior. Temperature-dependent stress/strain curves and Norton’s steady creep equation were used in the analysis. Another property of the solder governed by the Anand’s viscoplastic model was also employed to describe the behavior of solder balls. The simulation results in the elastic–plastic–creep analyses and viscoplastic analyses reveal that the von Mises stress, the non-linear strain, and the inelastic strain energy density of the critical solder balls increase with the number of stacked chips, but the increments become gradually stable as the number of chips increases. Three fatigue life prediction models—Darveaux’s model, the modified Coffin–Manson model and the creep-fatigue model—were applied to evaluate the fatigue life of the studied packages. Prediction results indicate that the fatigue life of the solder balls decreases as the number of stacked chips increases, and the decrease in predicted life shows stable behavior as the number of chips increases. The stable trend is consistent with experimental observation in the thermal cycling tests. By comparing with the experimental data, it is shown that the Darveaux’s model gives better prediction than the other two models.     

A new methodology for quantifying the multi-scale similarity of images

Metrology of devices becoming more and more sophisticated, the collected information is subsequently still increasing. The characteristics of an engineering surface can often be recorded as an image. To compare the characteristics of two different engineering surfaces X and Y tailored with different process parameters, to determine process parameters that have to be controlled to produce a surface with desired properties or to quantify the relevance of a post image treatment for characterising a particular surface property, a practical problem of major interest is therefore to answer the question “are images related to surfaces X and Y similar at all the length scales?”. An original method, based on recent information theory assumptions and on the multi-fractal formalism, is proposed to quantify the degree of similarity of a set of images at all the length scales. The relevance of this method for characterising the morphological textures of surfaces was developed on simulated images generated by means of a 3D fractal function simulating an abrasion process.     

A practical high-latchup immunity design methodology for internalcircuits in the standard cell-based CMOS/BiCMOS LSIs

A practical high-latchup-immunity design methodology is proposed for high-density internal circuits in standard cell-based CMOS/BiCMOS LSIs. Both locally injected trigger current and uniformly generated trigger current were measured using a new test structure. Focusing on the difference in the well shunt resistance between local and uniform trigger currents, a practical latchup-free guideline based on an analytical model for uniformly generated trigger current in the well is presented for the periodic placement of well contacts dependent on parasitic device parameters, on generated trigger current level, and a layout pattern size     

Analysis of the degradation mechanisms occurring in the topside interconnections of IGBT power devices during power cycling

This paper presents an experimental technique to characterize the damage evolution of the topside interconnections of power semi-conductor devices during power cycling tests. DC power cycling tests are done on Semikron SKIM 63 power modules, a solder-free module with silver sintered chips, ensuring the degradations to appear in the top layers only. The cycled substrates are then extracted from the test bench at different steps of the aging for analysis. Four-probe measurements are implemented on the chips so that the evolution of physical parameters representative of the degradation in the metallization and the bond wire contacts can be obtained. Finally, optical microscopy analysis of cross-sections at the wire bond contact interface is carried out to corroborate the electrical measurements to the crack length growth after specific aging intervals.     

A practical method for the energy rating of c‐Si photovoltaic modules based on standard tests

The performance of a photovoltaic module at Standard Test Conditions (STC) is valuable for comparing the peak performance of different module types. It does not, however, give enough information to accurately predict how much energy a module will deliver when subjected to real operating conditions. There are several proposals for an energy rating for PV modules which attempt to account for the varying operating conditions that one encounters in the field. In this paper, we present an approach with the emphasis on simplicity and practicality that incorporates existing standard measurements to determine the energy output as a function of global in‐plane irradiance and ambient temperature. The method is applied to crystalline Si modules and tested with outdoor measurements, and a good accuracy of prediction of energy production is observed. Finally, a proposal is made for a simple Energy Rating labeling of PV modules. Copyright © 2005 John Wiley & Sons, Ltd.     

A new TCAD-based statistical methodology for the optimization andsensitivity analysis of semiconductor technologies

A new TCAD-based statistical methodology for the optimization and sensitivity analysis of semiconductor technologies has been developed and demonstrated on a 0.18-μm SOI CMOS process. Two new screening techniques applicable to deterministic systems (Lenth's test and normal probability plots) were introduced and compared with correlation analysis. The graphical nature of the new techniques provided easier analysis of the screening results by clearly displaying which process factors surpass predefined significance limits. A multiresponse steepest ascent analysis was developed to locate regions of improved process performance before beginning response surface experimentation. To perform the analysis, a composite function representing the response criteria was constructed using desirability functions and incorporated within the steepest ascent methodology. Locating the region of improved performance allowed smaller experimental designs to be used for the response study significantly improving model accuracy. The response models were used to optimize the SOI CMOS process and perform sensitivity analyzes on both the baseline and optimized processes. Optimization resulted in a 15% increase in I_dsat without violating any other criteria. The results of the sensitivity analyzes, which showed the greatest benefit from the increased model accuracy, indicated no conspicuous device performance degradation caused by anticipated manufacturing variations     

A new process of grid structure formation for end point detection during substrate thinning of transit time devices

The influence of u.v. exposure on developed positive resist pattern followed by hard baking and etching at low temperature has been utilized in the present work to produce grid structures without using metal pattern mask during substrate thinning of transit time devices. The present process eliminates one step of metallization which is required in the conventional method, and this reduces the overall cost of fabrication. The process reported in this paper can be used in selective etching of silicon in other areas of device fabrication as well.     

一种基于方向特性识别电磁辐射源的新方法

通过获取电磁辐射源周围空间的电场强度分布,从而确定辐射源的方向特性,利用方向特性这种辨识度高的特性参数,基于支持向量机对电磁辐射源进行了准确的区分识别.文中分析了三个基本的天线辐射模型,在相同位置建立正方体接收阵获取其远区场强值,并采用支持向量机方法对数据进行处理,建立评判模型对识别准确率进行了分析.结果表明提出的方法具有很高的识别准确率.最后从抗噪性能、数据归一化方法和F1值三个方面综合分析了方法的合理性.     

A new thermal model for power MOSFET devices accounting for the behavior in unclamped inductive switching

The main aim of this work was the analysis of the transient thermal behavior of several typologies of power MOSFET devices. The commonly used thermal model has been applied to different device families with different breakdown voltages. The large difference between the experimental results and the simulation runs, performed with the classic approach for some kinds of devices, leads to correct the traditional mathematical thermal model and to build up a new one in which the real size of the epitaxial layer is taken into account. A new model will be shown performing a better fitting with the experimental evidence and confirming its suitability for all the proofed families of devices. The mathematical process developed to build up the model is shown, and a comparison is carried out between the measured temperatures on the device and estimation by the model. The results discussed in the paper show how the developed model allows a better fitting of the achieved model with the experimental measurements and demonstrate the suitability of the proposed approach.     

A new approach for modeling of current degradation in hot-electrondamaged LDD NMOSFETs

An analytical model describing current degradation in hot-electron damaged LDD NMOSFETS is proposed. The basic idea of the model is that the drain current degradation can be explained in terms of an increase in the parasitic resistance only. Good agreement with measured data over at least three decades of stress time is obtained with our model     

半导体器件DPA不合格的根源研究

破坏性物理分析（DPA）是用于检测半导体器件的。经检测发现，不合格原因既有半导体器件生产厂的，也有使用厂和其它方面的。且使用厂的问题比例不低，不容忽视。本文最后指出，正确的技术分析和公正的判断对DPA工作极为重要。