Nonvolatile memory with a metal nanocrystal/nitride heterogeneous floating-gate

Heterogeneous floating-gates consisting of metal nanocrystals and silicon nitride (Si/sub 3/N/sub 4/) for nonvolatile memory applications have been fabricated and characterized. By combining the self-assembled Au nanocrystals and plasma-enhanced chemical vapor deposition (PECVD) nitride layer, the heterogeneous-stack devices can achieve enhanced retention, endurance, and low-voltage program/erase characteristics over single-layer nanocrystals or nitride floating-gate memories. The metal nanocrystals at the lower stack enable the direct tunneling mechanism during program/erase to achieve low-voltage operation and good endurance, while the nitride layer at the upper stack works as an additional charge trap layer to enlarge the memory window and significantly improve the retention time. The write/erase time of the heterogeneous stack is almost the same as that of the single-layer metal nanocrystals. In addition, we could further enhance the memory window by stacking more nanocrystal/nitride heterogeneous layers, as long as the effective oxide thickness from the control gate is still within reasonable ranges to control the short channel effects.     

Trimming analog circuits using floating-gate analog MOS memory

A floating-gate MOS analog memory circuit that can be electrically programmed for positive and negative voltage changes and that can be fabricated in a standard CMOS IC process is described. Unlike existing electrically erasable floating-gate memory circuits, this circuit does not require special fabrication techniques like ultrathin tunneling oxides or textured polysilicon. Instead, mask geometry is used to cause field-enhanced Fowler-Nordheim tunneling of electrons from a floating gate. Retention measurements at elevated temperatures indicate that the loss of floating-gate charge should be less than 0.1% over a ten-year period at temperatures below 100°C. One limitation of this structure is that the rate of change of the floating-gate voltage can be quite small (e.g. 10 mV/s). A general trimming circuits, whose novel feature is that any number of trimming circuits can be independently and simultaneously adjusted across an entire IC, has been incorporated into a prototype CMOS op amp to decrease its input offset voltage from 10 mV to less than 0.5 mV     

A nonvolatile analog neural memory using floating-gate MOS transistors

Simple floating-gate transistors fabricated by a conventional double-polysilicon process show excellent programming and charge-retention characteristics. A five-transistor synapse cell achieves 8-bit resolution and at least 6-bit accuracy for analog neural computation. It occupies 67 m×73 m in a 2-m CMOS process and can retain charge accuracy for over 25 years.This research was partially supported by DARPA under Contracts MDA972-90-C-0037 and MDA972-88-C-0048 and by TRW, Inc.     

Nonvolatile semiconductor memory devices

An attempt is made to survey and assess the nonvolatile semiconductor memory devices including charge-storage devices and FET's with ferroelectric gate insulators. The charge-storage devices are further divided into two groups: 1) charges-trapping devices such as the MNOS and the MAOS, and 2) floating-gate devices such as the FAMOS and the DDC. Approaches for achieving virtual nonvolatility in otherwise volatile semiconductor memories are briefly disscused. Novel structures which provide nonvolatility as well as the theoretical limit of memory array density are also explored.     

A PWM analog memory programming circuit for floating-gate MOSFETswith 75-μs programming time and 11-bit updating resolution

This paper describes a programming circuit for analog memory using pulsewidth modulation (PWM) signals and the circuit performance obtained from measurements using a floating-gate EEPROM device. This programming circuit attains both high programming speed and high precision. We fabricated the programming circuit using standard 0.6-μm CMOS technology and constructed an analog memory using the programming circuit and a floating-gate MOSFET. The measurement results indicate that the analog memory attains a programming time of 75 μs, an updating resolution of 11 bit, and a memory setting precision of 6.5 bit. This programming circuit can be used for intelligent information processing hardware such as self-learning VLSI neural networks as well as multilevel flash memory     

Nonvolatile static read/write memory cell using CMNOS structure

A new type of nonvolatile static read/write memory cell constructed with three MOS transistors and one MNOS transistor is proposed. The MNOS transistor and one of the MOS transistors involved are complementary combined to offer binary states in the Λ-shapedI-Vcurve for memory operation under normal power supply. Upon power failure, the MNOS transistor acts as a back-up element for nonvolatility. The new cell is characterized by advantageous features such as small cell size, simple peripheral circuit, operation with a unipolar power supply and low standby power consumption.     

A floating-gate analog memory device for neural networks

A floating-gate MOSFET device that can be used as a precision analog memory for neural network LSIs is described. This device has two floating gates. One is a charge-injection gate with a Fowler-Nordheim tunnel junction, and the other is a charge-storage gate that operates as a MOSFET floating gate. The gates are connected by high resistance, and the charge-injection gate is small so that its capacitance is much less than that of the charge-storage gate. By applying control pulses to the charge-injection gate, it is possible to charge and discharge the MOSFET floating gate in order to modify the MOSFET current with high resolution over 10 b. The charge injection can be carried out without disturbing the MOSFET output current with high voltage control pulses. This device is useful for on-chip learning in analog neural network LSIs     

Nonvolatile analog memory in MNOS capacitors

Long-term storage of analog signals of wide dynamic range has been successfully demonstrated for the first time in single MNOS capacitors. After a reset state is established by majority carrier tunneling, measured pulses of light are used to generate minority carriers which tunnel to nitride traps and in turn induce shifts in the flat-band voltage proportional to the minority carrier charge. Linear voltage windows of 12 volts are observed, and logarithmic decay rates are as low as 30 mV per decade of storage time per volt of initial flat-band shift. Analog signals can be stored linearly over a dynamic range of 40 dB for 30 hours.     

Effects of floating-gate interference on NAND flash memory celloperation

Introduced the concept of floating-gate interference in flash memory cells for the first time. The floating-gate interference causes V _T shift of a cell proportional to the V_T change of the adjacent cells. It results from capacitive coupling via parasitic capacitors around the floating gate. The coupling ratio defined in the previous works should be modified to include the floating-gate interference. In a 0.12-μm design-rule NAND flash cell, the floating-gate interference corresponds to about 0.2 V shift in multilevel cell operation. Furthermore, the adjacent word-line voltages affect the programming speed via parasitic capacitors     

A highly scalable opposite side floating-gate flash memory cell

In this paper, a Flash memory structure with the floating-gate at the opposite side of conduction channel (refer as OSFG-Flash) is proposed and demonstrated by two-dimensional (2-D) simulation. With the decoupling of the read oxide and tunneling oxide, very thin read oxide can be used to suppress short channel effect while a thick back-tunneling oxide around 10 nm can be used to provide sufficient charge retention time. Excellent scalability of the memory cell is demonstrated through a 2-D simulator down to 50 nm.     

Nonvolatile CCD memory with MNOS storage capacitors

The volatility of information stored in a charge-coupled device can be avoided by storing the information in metal-nitride-oxide-silicon capacitors added to a CCD. In the following, the function, layout, and measured results of test circuits are described, and different layouts of such memory circuits are discussed.     

Efficiency enhancement for power amplifiers using dynamic bias switching technique

A dynamic bias switching technique is presented which discretely switches supply voltages according to the signal envelope level. For the detected envelope signals which ate lower than an appropriate threshold, this technique dynamically switches the transistor's drain bias to a significantly lower voltage. For verification, a dynamic bias switching system, applied to a class-AB power amplifier for the 859 MHz band, was implemented. Using a down-link wideband code division multiple access (WCDMA) signal, improved output power of 0.5 dB from 30.5 to 31 dBm, and improved PAE of 8.1% points from 27.4 to 35.5% wete achieved at a given ACLR level of -30 dBc compared to the conventional single-supplied class-AB amplifier.     

Improved floating-gate devices using standard CMOS technology

A standard 2-μm, double-polysilicon, CMOS technology has been used to fabricate a floating-gate MOSFET. The 12-μm×17-μm device is electrically programmed using hot-electron injection and electrically erased using Fowler-Nordheim tunneling. Both operations can be performed with voltages lower than the junction breakdown voltage of the process, allowing high integration density and improved reliability. Programming times of hundreds of microseconds and erase times of tends of milliseconds are reported, both for a ΔV_t of 3 V. The programming time is about five orders of magnitude shorter than that of previously reported devices in a similar technology. The device is suitable for both analog and digital applications     

A new SONOS memory using source-side injection for programming

We reported a new polysilicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory using channel hot electron injection for high-speed programming. For the first time, we demonstrated that source-side injection technique, which is commonly used in floating gate nonvolatile memories for its high programming efficiency, can also be used in a SONOS device for achieving high-speed programming. Erase of the device is achieved by tunneling of electrons through the thin top oxide of the ONO charge storage stack. Since the thin top oxide is grown from the nitride layer, the self-saturated nature of the oxidation allows better thickness control. Endurance characteristics indicates that quality of the thin top grown from nitride is as good as the tunnel oxide grown from the silicon substrate. By increasing the top oxide thickness, it is possible to achieve ten years of retention requirement. The self-aligned sidewall gate structure allows small cell size for high density applications     

Nonvolatile Si quantum memory with self-aligned doubly-stacked dots

We propose a novel Si dot memory whose floating gate consists of self-aligned doubly stacked Si dots. A lower Si dot exists immediately below an upper dot and lies between thin tunnel oxides. It is experimentally shown that charge retention is improved compared to the usual single-layer Si dot memory. A theoretical model considering quantum confinement and Coulomb blockade in the lower Si dot explains the experimental results consistently, and shows that charge retention is improved exponentially by lower dot size scaling. It is shown that the retention improvement by lower dot scaling is possible, keeping the same write/erase speed as single dot memory, when the tunnel oxide thickness is adjusted simultaneously.     

Translinear circuits using subthreshold floating-gate MOS transistors

We describe a family of current-mode circuits with multiple inputs and multiple outputs whose output currents are products and/or quotients of powers of the input currents. These circuits are made up of multipleinput floating-gate MOS (FGMOS) transistors operating in the subthreshold regime. The powers are set by capacitor ratios; hence, they can be quite accurate. We analyze the general family of such circuits and present experimental data from several members that we fabricated in a standard 2m double-poly p-well process through MOSIS.     

High-voltage DMOS integrated circuits using floating-gate protection technique

An efficient low power protection scheme for thin gate oxide of high voltage (HV) DMOS transistor is presented. To prevent gate-oxide breakdown and protect HV transistor, the voltage controlling its gate must be within 5 V from the HV supply. Thus signals from the low voltage domain must be level shifted to control the gate of this transistor. Usually this level shifting involves complex circuits that reduce the speed besides requiring of large power and area. In this paper, a simple and efficient protection technique for gate-oxide breakdown is achieved by connecting a capacitor divider structure to the floating-gate node of HV transistor to increase its effective gate oxide thickness. Several HV circuits, including: positive and negative HV doublers and level-up shifters suitable for ultrasound sensing systems are built successfully around the proposed technique. These circuits were implemented with 0.8 μm CMOS/DMOS HV DALSA process. Simulation and experimental results prove the good functionality of the designed HV circuits using the proposed protection technique for voltages up to 200 V.     

Performance and reliability of HfAlOx-based interpoly dielectrics for floating-gate Flash memory

This paper discusses the performance and reliability of aggressively scaled HfAlO_x-based interpoly dielectric stacks in combination with high-workfunction metal gates for sub-45 nm non-volatile memory technologies. It is shown that a less than 5 nm EOT IPD stack can provide a large program/erase (P/E) window, while operating at moderate voltages and has very good retention, with an extrapolated 10-year retention window of about 3 V at 150 °C. The impact of the process sequence and metal gate material is discussed. The viability of the material is considered in view of the demands of various Flash memory technologies and direction for further improvements are discussed.     

DIFMOS—A floating-gate electrically erasable nonvolatile semiconductor memory technology

Electrically alterable read-only memories (EAROM's) or reprogrammable read-only memories (RPROM's) can be fabricated using a single-level metal-gate p-channel MOS technology with all conventional processing steps. Given the acronym DIFMOS for dual-injector floating-gate MOS, this technology utilizes the floating-gate technique for nonvolatile storage of data. Avalanche injection of hot electrons through gate oxide from a special injector diode in each bit is used to charge the floating gates. A second injector structure included in each bit permits discharge of the floating gate by avalanche injection of holes through gate oxide. The overall design of the DIFMOS bit is dictated by the physical considerations required for each of the avalanche injector types. The end result is a circuit technology which can provide fully decoded bit-erasable EAROM-type circuits using conventional manufacturing techniques.     

Nonvolatile memory characteristics of metallic nanodots as charge-storage nodes

The charge and discharge properties of NiSi nanodots in the gate oxide of MOS and MOSFET devices were investigated in order to utilize as the charge-storage nodes in a nonvolatile floating-gate memory. NiSi nanodots were formed by sputtering Ni and successive exposing to SiH₄ gas. The memory characteristics of MOS and MOSFET devices which contain the NiSi nanodots in the gate oxide were obtained through the capacitance-voltage measurements and the transient threshold voltage shift measurements. The window of threshold voltage shift was achieved to be 2.5 V when the gate bias voltages of ±20 V were applied for 1 s and 500 ms, respectively. The retention time of MOSFET memory-cell was estimated to be about 10 years.