Modelling of SiGe heterobipolar transistors: 200 GHz frequencies with symmetrical delay times

Our basic approach is to develop a symmetrical design with equal delay times for collector, base and the total load to simulate the high frequency behaviour of SiGe heterobipolar transistors (HBTs). On this base we have investigated the feasibility of SiGe HBTs with transit frequencies f_T above 200 GHz. A symmetrical design reaching f_T=208 GHz is presented. The dependence of the high frequency behaviour on Ge content and vertical transistor design is shown. Critical parameters like the maximum current density and the breakthrough voltage are considered. An analytical model is compared to numerical simulations and experimental data.     

Emitter injection and collector current ideality in abrupt heterojunction AlInAs/GaInAs HBTs

We investigated the electron injection process for high-speed N-p-n AlInAs/GaInAs HBTs by measuring collector and base currents as a function of base-emitter voltage with collector-base voltage equal to zero (Gummel plots) at temperatures from 77 to 300 K. We compared the measured collector current with calculations based on electron injection from emitter to base by tunneling through the conduction band spike and thermionic emission over it, using a modified version of the thermionic-field emission theory developed by Crowell and Rideout. Good agreement was obtained between the experimental collector current ideality factor and tunneling-thermionic emission theory for all temperatures and currents. This is an improvement over drift-diffusion and thermionic emission models, which have been used for HBTs but which do not correctly describe the experimentally observed temperature and current dependence of the ideality of the collector current. The tunneling-thermionic emission model explains the increase in collector current ideality factor that occurs as the transistor is biased at high collector current density (J_C 10⁵ A cm⁻²), which is the regime of operation in which f_T is maximized and a low ideality factor is most important. The model also explains the experimentally observed variation of h_FE with ln I_C. Thus the tunneling-thermionic emission model is a useful aid in the design of the epitaxial structure for high-frequency HBTs.     

Analysis of carrier-blocking effect in AlGaAs/GaAs HBT's withinsulating external collector and design criteria for collector-up HBT's

Two-dimensional simulations of cutoff frequencies for AlGaAs/GaAs HBT's with perfectly insulating external collector are made, and the results are compared with those for a case with semi-insulating external collector and for a case with normal n^- external collector. It is found that in the case with perfectly insulating external collector, minority carriers injected into the base from the emitter are partially blocked by the insulating layer and accumulate in the external base region. These carriers increase the effective base delay time, resulting in remarkable degradation of the cutoff frequency. In relation to this effect, a collector-up HBT is also simulated, and the design criteria for it are discussed. It is concluded that the effective emitter width should be made narrower than the collector width     

Novel fabrication of C-doped base InGaAs/InP DHBT structures for high speed circuit applications

We have fabricated InGaAs/InP based DHBTs for high speed circuit applications. A process involving both wet chemical and ECR plasma etching was developed. Carbon was employed as the p-type dopant of the base layer for excellent device stability. Both the emitter–base and base–collector regions were graded using quaternary InGaAsP alloys. The extrinsic emitter–base junction is buried for junction passivation to improve device reliability. The use of an InP collector structure with the graded region results in high breakdown voltages of 8-10 V, with no current blocking. The entire structure is encapsulated with spin-on-glass. These devices show no degradation in d.c. characteristics after operation at an emitter current density of 90 kA cm⁻² and a collector bias, V_CE, of 2 V at room temperature for over 500 h. Typical common emitter current gain was 50. An f_t of 80 and f_max of 155 GHz were achieved for 2×4 μm² emitter size devices.     

High/fmax collector-up AlGaAs/GaAsheterojunction bipolar transistors with a heavily carbon-doped basefabricated using oxygen-ion implantation

AlGaAs/GaAs collector-up heterojunction bipolar transistors (HBTs) with a heavily carbon-doped base layer were fabricated using oxygen-ion implantation and zinc diffusion. The high resistivity of the oxygen-ion-implanted AlGaAs layer in the external emitter region effectively suppressed electron injection from the emitter, allowing collector current densities to reach values above 10⁵ A/cm ². For a transistor with a 2-μm×10-μm collector, f_T was 70 GHz and f_max was as high as 128 GHz. It was demonstrated by on-wafer measurements that the first power performance of collector-up HBTs resulted in a maximum power-added efficiency of as high as 63.4% at 3 GHz     

Conditions at a p-n junction in the presence of collected current

An abrupt p-n junction, such as occurs at the collector junction of an n-p-n transistor, is considered. The ratio of n- to p-region conductivity is taken to be very high, so that the transition region is restricted almost entirely to the p-region. The electron density distribution n within the transition region is investigated as a function of the applied reverse bias V_c, and of the minority carrier electron current density J which is injected into the transition region from the neutral p-region. It is shown that significant departures occur from the conventional solutions in which the presence of current is neglected. In particular, the electron density n_c at the plane of injection and the transition region thickness w_t, used as collector boundary conditions in the analysis of transistor operation, are shown to be current-dependent.

Two cases are considered. In Case I, applicable to transistors with an epitaxial layer in the base region below the collector, the electron velocity is assumed much less than the limiting drift velocity. For low injection level, where the minority carrier density n is everywhere less than the equilibrium majority carrier density p_p, the transition region is essentially a depletion region and the injected electrons move in an electric field determined uniquely by the applied voltage. It is shown that n_c ∝ J and w_t ∝ V_c^1/2. For high injection level, when n p_p, the transition region is essentially an accumulation region, and conditions of space-charge-limited current flow are established for which n_c ∝ J^2/3 and . The low-level injection results are primarily of interest as analytical extensions of the classical treatment. The high-level injection results are also relevant to the treatment of the dielectric diode.

In Case II, applicable to most alloy and diffused-base transistors, the electron velocity is assumed equal to the limiting drift velocity throughout the transition region. Mobile carrier depletion at low injection again gives way to accumulation at high injection. The functional relationships remain as for Case I at low injection, but become at high injection.

Semi-quantitative and detailed quantitative treatments are developed, and normalized graphs of the minority carrier density as a function of distance within the transition region are given for various junction voltages and injected currents.     

Effects of high-injection barrier (HIB) position on bipolartransistor characteristics

This paper analyzes the effects of the vertical position over the n^$collector of the n-type layer formed by a high energy phosphorus implantation on the high current level characteristics of the n-p-n bipolar device. From the device simulation and measurement data, we demonstrate that the barrier located near the buried layer plays a more effective role in the suppression of both the base-widening effect and the avalanche multiplication effect in the high collector current region, whereas the barrier near the intrinsic base achieves base Gummel number reduction and high-current gain at a low collector current level. This paper is also concerned with a quasi-saturation phenomenon found in devices in which the barrier is near the base-collector junction. The factor accounting for this phenomenon is analyzed by way of two-dimensional simulations and measurements     

A New InP/InGaAs Double Heterojunction Bipolar Transistor With a Step-Graded InAlGaAs Collector Structure

An interesting InP/InGaAs double heterojunction bipolar transistor with a step-graded InAlGaAs layer at the base-collector (B-C) heterojunction is fabricated and studied. Simulated results reveal that the potential spike at the B-C heterointerface is completely eliminated. Experimentally, the operation regime is wider than 11 decades in magnitude of the collector current (I_c = 10^-12 A to I_c = 10^-1 A). Furthermore, the studied device exhibits a relatively high common-emitter breakdown voltage and low output conductance even at high temperature. In the microwave characteristics, the unity current gain cutoff frequency f_T = 72.7 GHz and the maximum oscillation frequency f _max = 50 GHz are achieved for a nonoptimized device (A_E = 6 times 6 mum²).     

Epitaxially-grown GaN junction field effect transistors

Junction field effect transistors (JFETs) are fabricated on a GaN epitaxial structure grown by metal organic chemical vapor deposition (MOCVD). The dc and microwave characteristics of the device are presented. A junction breakdown voltage of 56 V is obtained corresponding to the theoretical limit of the breakdown field in GaN for the doping levels used. A maximum extrinsic transconductance (g_m ) of 48 mS/mm and a maximum source-drain current of 270 mA/mm are achieved on a 0.8 μm gate JFET device at V_GS=1 V and V_DS=15 V. The intrinsic transconductance, calculated from the measured g_m and the source series resistance, is 81 mS/mm. The f_T and f_max for these devices are 6 GHz and 12 GHz, respectively. These JFET's exhibit a significant current reduction after a high drain bias is applied, which is attributed to a partially depleted channel caused by trapped hot-electrons in the semi-insulating GaN buffer layer. A theoretical model describing the current collapse is presented, and an estimate for the length of the trapped electron region is given     

Parallel parasitic conductance in narrow-width MOSFETs

One of the edge effects of narrow-width MOSFETs can be expressed as a parallel parasitic conductance G_P. G_P And the width reduction ΔW were determined from the variation of device's conductance G_T vs mask gate width W_M at different effective gate biases V_GS − V_T. The intersection point of these G_T vs W_M for different V_GS − V_T biases occurs at G_P and ΔW. A series of experiments in which external conductances were placed in parallel with the MOS transistor were performed, and the results verified the concept of the parallel parasitic conductance, and the algorithm for extracting both G_P and ΔW.     

On the recombination currents effect of heterostructure-emitter bipolar transistors (HEBTs)

In this paper, we will demonstrate the effect of recombination current on the electrical properties of heterostructure-emitter bipolar transistors (HEBTs). For comparison, an AlGaAs/GaAs and an AlInAs/GaInAs HEBT are fabricated with the same layer structure. The theoretical analysis shows that the neutral-emitter recombination current in the neutral emitter regime is a significant factor for determining transistor characteristics. For the AlGaAs/GaAs HEBT, the hole diffusion length is larger than the emitter thickness, so that most of holes can be reflected back at the confinement layer due to the hole recombination current being low in the neuter-emitter region. Thus, the high emitter injection efficiency and current gain can be achieved simultaneously. On the other hand, for the AlInAs/GaInAs HEBT, the increase of recombination current at neutral emitter regime and the existence of potential spike could reduce the emitter injection efficiency at large V_BE voltage. Hence, the non-1KT component of collector current is enhanced and the characteristics of transistor are degraded. However, a lower offset voltage of 40 mV is obtained attributed to the low base surface recombination current for the AlInAs/GaInAs HEBT. All of these experimental results are consistent with the theoretical analysis.     

Monte Carlo analysis of the space-charge effect in AlGaAs/GaAsballistic collection transistors (BCTs) under high currentinjection

AlGaAs/GaAs ballistic collection transistors (BCTs) are investigated by self-consistent Monte Carlo simulation, focusing on the space-charge effect in the collector region. In addition to the conventional BCT collector structure (i-p⁺-n⁺), modified collector structures which have n^--p⁺-n ⁺ and p^--p⁺-n⁺ doping profiles are examined. By taking account of the fact that the collector delay time is composed of transit time and capacitance charging time, it is shown that the n^--p⁺-n⁺ collector structure is effective for the suppression of the base-widening effect (Kirk effect) compared to the i-p⁺-n⁺ or p^- -p⁺-n⁺ structure. Donors in the n^- layer compensate for the negative space charges produced by near-ballistic electrons. For a simulated BCT with an n^--p ⁺-n⁺ collector, the smaller collector capacitance charging time leads to improvement in current-gain cutoff frequency under high current injection     

An 0.3-μm Si epitaxial base BiCMOS technology with 37-GHzfmax and 10-V BVceo for RF telecommunication

In this paper, a 0.3-μm BiCMOS technology for mixed analog/digital application is presented. A typical emitter area of this technology is 0.3 μm×1.0 μm. This technology includes high f _max of 37 GHz at the low collector current of 300 μA and high BV_ceo of 10 V NPN transistor, CMOS with L_eff=0.3 μm, and passive elements. By using the shallow and deep trench isolation technology and nonselective epitaxial intrinsic base, the C_jc can be reduced to 1.6 fF, which is the lowest value reported so far. As a results, we have managed to obtain the high f_max at the low current region and high BV _ceo concurrently. These features will contribute to the development of high-performance BiCMOS LSI's for various mixed analog/digital applications     

A theory of transistor cutoff frequency (fT) falloff at high current densities

It is shown that the observed falloff in the fTof a transistor at high currents is due to the spreading of the neutral base layer into the collector region of the device at high current densities. The base layer spreading mechanism derives from an analysis of the effect of the current-dependent buildup of the mobile-carrier space-charge density in the collector transition layer. Calculations show that at sufficiently high collector current levels, the mobile space-charge density in the collector transition layer cannot be considered negligible in comparison to the fixed charge density of that region. The over-all effect of taking the mobile space charge into account in analyzing the collector transition region is that, at high current densities, the transition region boundary adjacent to the neutral base layer is displaced toward the collector metal contact with increasing collector current. The attendant widening of the neutral base layer results in the observed, high-current falloff in fT. The application of this theory to transistor structures of both the alloy and mesa variety yields, in each case, calculated curves of fTvs Icwhich are in reasonably good agreement with experiment.     

Small-signal performance and modeling of sub-50 nm nMOSFETs with fT above 460-GHz

We have fabricated and tested the performance of sub-50 nm gate nMOSFETs to assess their suitability for mixed signal applications in the super high frequency (SHF) band, i.e. 3–30 GHz. For a 30 nm × 40 μm × 2 device, we found f_T = 465 GHz at V_ds = 2 V, V_g = 0.67 V, which is the highest cut-off frequency reported for a MOSFET produced on bulk silicon substrate so far. However, our measurements of f_max and noise figure indicate that parasitics impose limitations on SHF operation. We also present a high frequency ac model appropriate to sub-50 nm gate length nanotransistors, which incorporates the effects of the parasitics. The model accurately accounts for measurements of the S- and Y-parameters in the frequency range from 1 to 50 GHz.     

Reduction of the base-collector capacitance in InP/GaInAsheterojunction bipolar transistors due to electron velocity modulation

The base-collector capacitance of an InP/GaInAs heterojunction bipolar transistor (HBT) was measured as a function of collector current and base-collector voltage. The experimentally obtained results were considerably smaller than the expected dielectric capacitance. For example, at a collector current density of 50 kA/cm² the value of the intrinsic C_bc was 33% less than the expected dielectric capacitance. A model that takes into account modulation of electron velocity in the collector depletion region by the base-collector voltage was employed to account for the experimental results. An arbitrary profile of the electron velocity in the collector, which accounts for the velocity overshoot effect, was assumed in developing this model. Excellent agreement was obtained with no fitting parameters. The model relates the change in C_bc to the variation of the collector delay time with base-collector voltage     

Numerical simulation of GaAs MESFETs with a p-buffer layer on asemi-insulating substrate compensated by deep traps

A numerical analysis of GaAs MESFETs with a p-buffer layer on a semi-insulating substrate is performed in which impurity compensation by traps in the substrate is considered. It is shown that the use of a thick p-buffer layer results in a lower device current due to the formation of a steep barrier at the channel-substrate interface. It is also shown that with higher trap and acceptor densities in the substrate, the drain current is reduced due to the decrease in the substrate current. This decrease occurs because a negative-space-charge layer is formed in the substrate. It is demonstrated that when the p-buffer layer is fully depleted, its acceptors play the same electrical role as the acceptors within the space-charge region of the semi-insulating substrate. Thus, using a thick p-buffer layer has the same effect as using a substrate with a high density of traps, i.e. it minimizes the short-channel effects in GaAs MESFETs. Therefore, if the trap density in the substrate is low, the short-channel effects can be reduced by introducing a p-buffer layer or a buried p-layer     

Profile design considerations for minimizing base transit time inSiGe HBTs for all levels of injection before onset of Kirk effect

An iteration scheme to calculate the base transit time (τ_b) for a given collector current density is developed in order to determine the optimal doping profile and Ge profile in the neutral base for minimizing the τ_b of SiGe HBTs under all levels of injection before the onset of the Kirk effect. We adopt a consistent set of SiGe transport parameters, tuned to measurement data, and include important effects such as the electric-field dependency of the diffusion coefficient and plasma-induced bandgap narrowing in our study. The scheme has been verified with simulation results reported in the literature. Our study shows that under both low and high injection, for a given Ge dose, intrinsic base resistance, and base concentration near the emitter, a retrograde doping profile with a trapezoidal Ge profile gives the minimum τ_b     

Collector capacitance and high-level injection effects in bipolar transistors

A simple model for the behavior of the collector capacitance of bipolar transistors has been developed with the aim of studying high-level injection phenomena in epitaxial collectors. The Collector capacitance (Cc) calculated from the results of a dynamic small-signal measurement. It is Observed that Ccincreases by more than an order of magnitude as the collector current is increased from a low value into the quasi-saturation regime at a fixed collector-emitter voltage of 1 V. The collector capacitance is composed of a transition capacitance, which is due to the presence of unneutralized charges in the collector region, and of a diffusion capacitance, which is due to the presence of neutralized charge in transit across the base and the collector regions. The transition capacitance is the dominant component at low-current levels. However, at high-current levels, the diffusion capacitance predominates if the one, dimensional "base-widening" model (Kirk effect) becomes operative and the total capacitance becomes very large. This capacitance is found to be about an order of magnitude larger than that expected if the two-dimensional "lateral-spreading" model were dominant. Good agreement is observed between the experimental data and the theoretical Ccestimates using the one-dimensional model. Thus it is concluded that the base-widening model controls the behavior of our devices at high levels of injection in the collector.