一种基于MPP的并行归并算法

文中提出并分析了并行归并算法ＰＭＦＳ;基于曙光－１０００大规模并行计算机系统,给出了ＰＭＦＳ算法应用实例的实验结果,并将ＰＭＦＳ算法推广得到的并行归并排序算法与ＰＳＲＳ算法进行了比较。     

映射循环算法到脉动阵列的一种有效方法

本文提出了把任意ｎ维嵌套循环算法映射和划分到２维固定大小的Ｓｙｓｔｏｌｉｃ阵列的一种自动设计方法，由于考虑了数据相关性，运用该方法产生的ＶＬＳＩ算法的执行时间少，而且不会引起时空冲突。因为平面ＶＬＳＩ阵列容易构造，所以该方法有良好的可行性的实用性。     

基于自适应分块的TIN三角网建立算法

ＴＩＮ三角网在ＧＩＳ／ＶＲ中具有重要用途,在ＴＩＮ生成算法中,分割－归并法、三角网生长法各有其优缺点,为兼顾空间的时间性能,因而提出了一种基于自适应分块思想的ＴＩＮ三角网建立算法,它融合传统的分割－归并法、三角网生长等Ｄｅｌａｕｎａｙ三角网主流生成算法于一体。实验结果表明,算法建立的三角网无交叉和重复,并具有Ｄｅｌａｕｎａｙ三角网的特性,同时兼顾了空间的时间性能,具有较高的执行效率,算法的设计思想     

高级程序设计语言中归并数据类型的研究

本文讨论如何用归并类型来代替高级程序设计语言中指针和记录（如ＰＡＳＣＡＬ），归并类型的设计除了具有统一之外，还具有更高可靠性，本文已将归并类型插入到Ｍｐｄｕｌａ－２程序语言中。     

一个新的基于3D纹理映射及Shear—werp变换的快速体绘制方法

介绍了一个新的基于纹理映射及Ｓｈｅａｒ－ｗａｒｐ变换的快速体绘制方法。所提出的方法吸收了纹理映射方法的长处，通过纹理硬件的加速，并在纹理装载时提出了可适应性的纹理分割方法，使该算法不受纹理内存的限制。在进行纹理映射时，通过剪切（Ｓｈｅａｒ）变换和三维图象的分割，加快绘制速度。与多种经典的快速体绘制方法进行测试比较，该方法达到了交互的效果和更高的绘制速度。     

基于密码逻辑阵列的分组密码高能效映射方法

分组密码是应用最为广泛的密码体制之一,密码逻辑阵列实现分组密码算法的方式兼具灵活度和高性能。基于项目组设计的密码逻辑阵列结构,分析分组密码的基本特征,在此基础上提出了分组密码在阵列上高能效映射的模型和基本原则,减少了映射消耗的计算资源和互连资源,通过循环并行映射方式加速密码处理,论述了典型分组密码算法的映射方法。在阵列芯片上对映射结果进行实测分析,其AES算法处理能效为9.54 Mbps/mW,相较于其他密码处理结构有着明显能效优势,结果表明本文提出的映射方法在分组密码处理上具有较好的能效特性。     

用NURBS表示的几何实体的纹理映射方法

本文实现了一个用于基于ＮＵＲＢＳ表示的几何造型系统的纹理映射算法，该算法采用曲线的弧长作为基本的纹理映射参数，减少了纹理映射中的图形混淆。该系统能对用ＮＵＲＢＳ表示的各种几何实体使用统一的算法进行纹理映射，算法简单、占用存储空间小。     

Systolic算洁和结构求解代数Riccati方程

本文基于矩阵的符号函数法，提出了一种Ｕ－Ｄ分解算法和脉动（Ｓｙｓｔｏｌｉｃ）结构有效地求解代数Ｒｉｃｃａｔｉ方程以及用固定大小的方形阵列解决大型问题的方法．     

Systolic算法和结构求解代数Riccati方程

本文基于矩阵的符号函数法，提出了一种Ｕ－Ｄ分解算法和脉动（Ｓｙｓｔｏｌｉｃ）结构有效地求解代数Ｒｉｃｃａｔｉ方程以及用固定大小的方形阵列解决大型问题的方法。     

异构计算系统的任务调度算法SMT=GA

给出一种对异构计算系统进行任务映射与调度的遗传算法－ＳＭＴ－ＧＡ算法。首先对ＨＣＳ任务调度问题作出形式描述,然后分别介绍ＳＭＴ－ＧＡ算法的总体框架,染色体设计,从染色体获得调度方案的方法,染色体适合度函数设计,交叉与变异遗传算子设计等。     

Mapping of Neural Network Models onto Systolic Arrays

This paper presents a mapping scheme for the proposed implementation of neural network models on systolic arrays. The mapping technique is illustrated on the multilayer perceptron with back-propagation learning. Dependency graphs have been given that represent the operations in the execution phases of the neural network model and later suitable algorithms are presented to realize the operations in a linear bidirectional systolic array. The speedup metric has been used to evaluate the performance of the proposed implementation.     

General-purpose systolic arrays

The extension of systolic array architecture from fixed- or special-purpose architectures to general-purpose, SIMD (single-instruction stream, multiple-data stream), MIMD (multiple-instruction stream, multiple-data stream) architectures, and hybrid architectures that combine both commercial and FPGA (field-programmable gate array) technologies is chronicled. The authors present a taxonomy for systolic organizations, discuss each architecture's methods of exploiting concurrencies, and compare performance attributes of each. The authors also describe a number of implementation issues that determine a systolic array's performance efficiency, such as algorithms and mapping, system integration through memory subsystems, cell granularity, and extensibility to a wide variety of topologies     

Systolic Array Synthesis using SFG Representations

One of the important design problems in systolic array processing is the development of a systematic methodology for transforming an algorithm represented in some high level constructs into a systolic architecture specified by the timing of data movement and the interconnection of processing elements such that the design requirements are satisfied. In this paper a method using the SFG (signal flow graph) of a given algorithm to design systolic arrays through graphic mapping and retiming is presented. An algorithm is first represented by a DG (dependence graph). Then the DG is mapped into an SFG by a graph projection. Cut-set retiming procedures are then applied to derive a regular localised SFG from which a systolic array design can be obtained for the given matrix examples i.e. LU and QR decompositions.     

Forty-three ways of systolic matrix multiplication

This paper investigates different ways of systolic matrix multiplication. We prove that in total there are 43 arrays for multiplication of rectangular matrices. We also prove that, depending on the mutual relation between the dimensions of rectangular matrices, there is either 1 or 21 arrays with minimal number of processing elements. Explicit mathematical formulae for systolic array synthesis are derived. The methodology applied to obtain 43 systolic designs is based on the modification of the synthesis procedure based on dependency vectors and space-time mapping of the dependency graph.     

蒙哥马利算法到脉动阵列的规范映射方法

蒙哥马利算法是在RSA密码系统中广泛应用的模乘法算法。该文介绍蒙哥马利算法到脉动阵列的映射过程,阐述了从算法到脉动阵列的规范映射方法。阵列的时钟周期长度大致是两个单位全加器延迟,n位模乘法的计算延迟是2n+2个时钟周期。模块化、规则化、通信局部化等特征,使得脉动阵列特别适合采用深亚微米VLSI技术实现,并获得很高的工作频率,从而提高处理速度。     

矩阵相乘的并行计算及其DSP实现

矩阵相乘的速度在阵列信号处理中具有重要意义,并行处理是提高系统运算能力最有效的方法.本文根据矩阵相乘的特点,提出了矩阵相乘的并行算法.同时经分析推导出了矩阵相乘的脉动矩阵方法,得出其在超立方及其平面阵列上的映射,提高了矩阵的运算速度.最后,给出了用DSP实现脉动矩阵的系统方案.     

Path planning on the warp computer: using a linear systolic array in dynamic programming ∗

Given a map in which each position is associated with a traversabihty cost, the path planning problem is to find a minimum-cost path from a source position to every other position in the map. The paper proposes a dynamic programming algorithm to solve the problem, and analyzes the exact number of operations that the algorithm takes. The algorithm accesses the map in a highly regular way, so it is suitable for parallel implementation. The paper describes two general methods of mapping the dynamic programming algorithm onto the linear systolic array in the Warp machine developed by Carnegie Mellon. Both methods have led to efficient implementations on Warp. It is concluded that a linear systolic array of powerful cells like the one in Warp is effective in implementing the dynamic programming algorithm for solving the path planning problem