14.2 W/mm internally-matched AlGaN/GaN HEMT for X-band applications

High-performance X-band AlGaN/GaN high electron mobility transistor (HEMT) has been achieved by Γ-gate process in combination with source-connected field plate. Both its Schottky breakdown voltage and pinch-off breakdown voltage are higher than 100 V. Beside, excellent superimposition of direct current (DC) I-V characteristics in different V_ds sweep range indicates that our GaN HEMT device is almost current collapse free. As a result, both outstanding breakdown characteristics and reduction of current collapse effect guarantee high microwave power performances. Based upon it, we have developed an internally-matched GaN HEMT amplifier with single chip of 2.5 mm gate periphery, which exhibits power density of 14.2 W/mm with 45.5 dBm (35.5 W) output power and a power added efficiency (PAE) of 48% under V_ds = 48 V pulse operating condition at 8 GHz. To the best of our knowledge, it is the highest power density at this power level.     

Ultra low voltage, ultra low power low noise amplifier for 2 GHz applications

In this paper, a 0.29 V, 2 GHz CMOS low noise amplifier (LNA) intended for ultra low voltage and ultra low power applications is developed. The circuit is simulated in standard 0.18 μm CMOS MOSIS. A two-stage architecture is then used to simultaneously optimize the gain and noise performance. Using forward-body-biased, the proposed LNA can operate at 0.29 V supply voltage, successfully demonstrating the application potential of dynamic threshold voltage technology in the radio frequency region. The LNA provides a good gain of 26.25 dB, a noise figure of 2.202 dB, reverse isolation (S₁₂) of −59.04 dB, input return loss (S₁₁) of −122.66 dB and output return loss (S₂₂) of -11.61 dB, while consuming only 0.96mW dc power with an ultra low supply voltage of 0.29 V. To the best of authors’ knowledge this is the lowest voltage supply and the lowest power consumption CMOS LNA design reported for 2 GHz to date.     

A 1.25 Gbps DC-coupled laser diode driver with VBE compensation technique

A 1.25 Gbps integrated laser diode driver (LDD) driving an edge-emitting laser has been designed and fabricated in 0.35 μm BiCMOS technology. The IC can provide independent bias current (5-100 mA) with automatic power control, and modulation current (4-85 mA) with temperature compensation adjustments to minimize the variation in extinction ratio. This paper proposed an unique modulation output driver configuration which is capable of DC-coupling a laser to the driver at +3.3 V supply voltage; and combined a V_BE compensation circuit, the IC can operate at a wide temperature range (−40 to 85 °C) for date rates up to 1.25 Gbps. V_BE compensation technique is used to compensate for variation in V_BE over the operating temperature range so as to minimize the variations in rise and fall time of modulation output over temperatures.     

A 0.5 V 320 MHz 8 bit×8 bit pipelined multiplier in 130 nm CMOS process

This paper presents an 8×8 bit pipelined multiplier operating at 320 MHz under 0.5 V supply voltage. Using PMOS forward body bias technique, the modified full adder and the new D flip-flop with synchronous output are combined and implemented in the proposed pipelined multiplier to achieve high operation speed at supply voltages as low as 0.5 V. The proposed pipelined multiplier is fabricated in 130 nm CMOS process. It operates up to 320 MHz and the power consumption is only 1.48 mW at 0.5 V. Moreover, the power consumption of the proposed pipelined multiplier at 0.5 V is reduced over 5.7 times than that of the traditional architecture at 1.2 V. Thus, the proposed 8×8 bit pipelined multiplier is suitable for SoC and dynamic voltage frequency scaling applications.     

Design of adaptive supply voltage for sub-threshold logic based on sub-1 V bandgap reference circuit

This paper presents the design methodology to produce an adaptive supply voltage, which is used to drive digital sub-threshold logic system. Design guidelines to maintain constant speed and power via adaptive V_DD regulation are presented first. Then the paper discusses modification of sub-1 V bandgap reference (BGR) circuits using dynamic threshold MOSFET technique to provide the necessary adaptive reference voltage. Another well-known sub-1 V BGR circuit using current mode technique is also fabricated and compared. Both circuits are implemented in CMOS 0.18 μm technology. Empirical data from SPICE simulation and first order approximation techniques are used to derive analytical design models used inside BGR circuit. Measurement results of both the fabricated circuits show reference voltage output of 500 mV range; which are in good match of SPICE simulation.     

A new inverter-based charge pump circuit with high conversion ratio and high power efficiency

The current paper presents a new inverter-based charge pump circuit with high conversion ratio and high power efficiency. The proposed charge pump, which consists of a PMOS pass transistor, inverter-based switching transistors, and capacitors, can improve output voltage and conversion ratio of the circuit. The proposed charge pump was fabricated with TSMC 0.35 μm 2P4M CMOS technology. The chip area without pads is only 0.87 mm×0.65 mm. The measured results show that the output voltage of the four-stage charge pump circuit with 1.8 V power supply voltage (V_DD=1.8 V) can be pumped up to 8.2 V. The proposed charge pump circuit achieves efficiency of 60% at 80 μA.     

Record gain at 3.1 GHz of 4H-SiC high power RF MESFET

In this paper, a very high gain 4H-SiC power MESFET with incorporation of L-gate and source field plate (LSFP-MESFET) structures for high power and RF applications is proposed. The influence of L-gate and source field plate structures on saturation current, breakdown voltage (V_b) and small-signal characteristics of the LSFP-MESFET was studied by numerical device simulation. The optimized results showed that V_b of the LSFP-MESFET is 91% larger than that of the 4H-SiC conventional MESFET (C-MESFET), which meanwhile maintains almost 77% higher saturation drain current characteristics. The maximum output power densities of 21.8 and 5.5 W/mm are obtained for the LSFP-MESFET and C-MESFET, respectively, which means about 4 times larger output power for the proposed device. Also, the cut-off frequency (f_T) of 23.1 GHz and the maximum oscillation frequency (f_max) of 85.3 GHz for the 4H-SiC LSFP-MESFET are obtained compared to 9.4 and 36.2 GHz for that of the C-MESFET structure, respectively. The proposed LSFP-MESFET shows a new record maximum stable gain exceeding 22.7 dB at 3.1 GHz, which is 7.6 dB higher than that of the C-MESFET. To the best of our knowledge, this is 2.5 dB greater than the highest gain yet reported for SiC MESFETs, showing the potential of this device for high power RF applications.     

Designing leakage tolerant, low power wide-OR dominos for sub-130 nm CMOS technologies

In this paper, we discuss the design of leakage tolerant wide-OR domino gates for deep submicron (DSM), bulk CMOS technologies. Technology scaling is resulting in a 3×-5× increase in transistor I_OFF/μm per generation causing 15-30% degradation in the noise margin of high performance domino gates. We investigate several techniques that can improve the noise margin of domino logic gates and thereby ensure their reliable operation for sub-130 nm technologies. Our results indicate that, selective usage of dual V_TH transistors shows acceptable energy-delay tradeoffs for the 90 nm technology. However, techniques like supply voltage (V_cc) reduction or using non-minimum L_e transistors are required in order to ensure robust and low power operation of wide-OR domino designs for the 70 nm generation.     

A tunable highly linear CMOS transconductor with 80 dB of SFDR

This paper presents a new tunable CMOS differential transconductor with an SFDR ranging from 80 to 94 dB. It is based on a core of two voltage buffers with local feedback loops to achieve low-output impedance. The two buffers drive an integrated polysilicon resistor, which is the actual transconductance element. The current generated at the resistor is delivered directly to the output using source coupled pairs. This avoids distortion generated by conventional architectures using current copying cells. The voltage buffers are based on the compact flipped voltage follower (FVF) cell. The proposed transconductor relies on the gain of local feedback loops instead of harmonic cancellation. This leads to a simpler design and less mismatch sensitivity. The proposed transconductor bandwidth is closer to that of the typical open-loop design than to one with global feedback, since the local feedback loop is much faster than a global one. It can be tuned down 20% of its maximum g_m which is enough to compensate for process variations. The proposed circuit was fabricated in a 0.5 μm CMOS technology and powered by a 5 V single supply. It was measured with 2 Vpp input signals up to 10 MHz. The maximum g_m value is 660 μA/V. The transconductor consumes 30 mW and occupies roughly a die area of 0.17 mm². Experimental results are presented to validate the proposed circuit.     

Integrated circuits using fully solution-processed organic TFT devices with printed silver electrodes

We have demonstrated fully solution-processed inverter, NAND and NOR circuits using pseudo-CMOS logic and p-type organic TFT devices with printed electrodes that were fabricated using ink-jet printed silver nanoparticle inks at low temperatures. In order to optimize the gate electrode profiles, we thoroughly assessed the surface wettability of the silver nanoparticle inks. The pseudo-CMOS inverter circuit exhibited exceptional switching characteristics with a high signal gain of 34 at a supply voltage of 20 V. The NAND and NOR circuits also exhibited excellent logic characteristics, whereby the switching voltage was approximately V_DD/2 with a high noise margin and short delay time of 12.5 ms.     

A resonant half bridge driver with novel common mode rejection technique implemented in 1.0 μm high voltage (650 V) DIMOS process

In this paper, a half bridge convert driver IC with novel common mode rejection technique is designed and implemented in 1.0 μm high voltage (650 V) Dielectric Isolation MOS (DIMOS) process. The Designed IC is suitable for medium power (under 500 W) applications such as consumer electronics. Half bridge converter driver IC with a novel common mode rejection technique, which is composed of noise filter and set inhibitor, shows high dv/dt noise immunity up to 66.67 V/ns. Spectre simulation was performed to verify the electrical characteristics of the designed IC.     

Highly controllable dual-gate microcrystalline silicon thin film transistor processed at low temperature (T < 180 °C)

The addition of a top-gate to a bottom gate microcrystalline silicon thin film transistor (TFT) that is processed at a maximum temperature of 180 °C, is shown to lead to a very efficient control of the threshold voltage V_TH. A real time control of CMOS pairing is then possible. The value of the coupling coefficient that is the ratio of the variation of V_TH on the variation of the voltage of the top-gate control is 0.7. This efficient control is mainly due to the use of very thin, 50 nm thick, active layer and to its electrical quality that leads to a full depletion.     

AlGaN/GaN self-aligned MODFET with metal oxide gate for millimeter wave application

As promising candidates for future microwave power devices, GaN-based high-electron mobility transistors (HEMTs) have attracted much research interest. An investigation of the operation of AlGaN/GaN n type self-aligned MOSFET with modulation doped GaN channels is presented. Liquid phase deposited (LPD) SiO₂ is used as the insulating material. An analytical model based on modified charge control equations is developed. The investigated critical parameters of the proposed device are the maximum drain current (I_Dmax), the threshold voltage (V_th), the peak DC trans-conductance (g_m), break down voltage (V_br) and unity current gain cut-off frequency (f_T). The typical DC characteristics for a gate length of 1 μm with 100 μm gate width are following: I_max=800 mA/mm, V_break-down=50 V, g_{m_extrinsic}=200 mS/mm, V_pinchoff=−10 V. The analysis and simulation results on the transport characteristics of the MOS gate MODFET structure is compared with the previously measured experimental data. The calculated values of f_T (20-130 GHz) suggest that the operation of the proposed device effectively, has sufficiently high current gain cutoff frequencies over a wide range of drain voltage, which is essential for high-power performance at microwave frequencies. The proposed device offers lower on-state resistance. The results so obtained are in close agreement with the experimental data.     

Ultra wideband, low-power, 3-5.6 GHz, CMOS voltage-controlled oscillator

In this paper, a low-power inductorless ultra wideband (UWB) CMOS voltage-controlled oscillator is designed in TSMC 0.18 μm CMOS technology as a part of a ultra wideband FM (UWBFM) transmitter. The VCO includes a current-controlled oscillator (CCO) which generates output frequencies between 1.5 and 2.8 GHz and a voltage-to-current (V-to-I) converter. A low-power frequency doubler based on a Gilbert cell, which operates in weak inversion, doubles the VCO tuning range achieving oscillation frequencies between 3 and 5.6 GHz. Thus, the well-known proportionality between the oscillation frequency and the bias tuning current in CCOs is avoided for the entire achieved tuning range, resulting in a lower power design. The employed architecture provides high suppression, over 45 dB, of the 1st and 3rd harmonics, while enabling high-frequency operation and conversion gain due to the unbalanced structure and the single-ended output. The current consumption is 5 mA at a supply voltage of 1.8 V. The VCO exhibits a phase noise of −80.56 dBc/Hz at 1 MHz frequency offset from the carrier and a very high ratio of tuning range (60.4%) over power consumption equal to 8.26 dB which is essential for a UWBFM transmitter.     

Power performance and scalability study of AlGaAs/GaAs double-recessed pseudomorphic high electron mobility transistors on unthinned substrate for coplanar waveguide circuit applications

We have investigated the power performance and scalability of AlGaAs/GaAs Double-Recessed Pseudomorphic High Electron Mobility Transistors (DR-PHEMTs) at 10 GHz on an unthinned GaAs substrate for CoPlanar Waveguide (CPW) circuit applications. It was found that the output power varied linearly with the logarithm of the device’s gate width ranging from 200 to 1000 μm. It increased at a rate of 0.01 dB/μm. That worked out to a doubling of output power (or 3 dB) for every 300 μm increase in the gate width. Gain decreased at a rate of about 0.005 dB/μm while PAE generally improved when the gate width was increased. As for DC measurement, the maximum transconductance of the device was about 375 mS/mm at V_G = −0.5 V and V_DS = 3 V. The gate-drain breakdown voltage (BV_GD) measured was −20 V, defined at I_G = −1 mA/mm. The microwave performance of the devices was measured on-wafer using a load-pull system at a bias of V_G = −0.5 V and V_DS = 8 V. For a device with a gate width of 1 mm, its saturated CW output power, gain and PAE value at 10 GHz was 27.5 dBm (0.55 W), 8 dB and 48%, respectively. At this same set of bias conditions, the value of f_t and f_max was 40 and 80 GHz, respectively.     

Open-circuit voltage up to 1.07 V for solution processed small molecule based organic solar cells

With the goal of increasing the open-circuit voltage, two new solution-processable A–D–A structure small molecule donor materials, named DCAO3TF and DCAO3TCz, using two weak electron-donating units, fluorene and carbazole as the central block have been designed and synthesized for photovoltaic applications. While bulk heterojunction photovoltaic devices based on DCAO3TF:PC₆₁BM and DCAO3TCz:PC₆₁BM as the active layers exhibit moderate power conversion efficiencies of 2.38% and 3.63%, respectively, devices based on DCAO3TF:PC₆₁BM do exhibit an impressively high open-circuit voltage (V_oc) up to 1.07 V, which is one of the highest V_oc in organic solar cells based on donor:PCBM blend films.     

A 33 mW 12.5 Gbps BiCMOS transmitter for high speed backplane applications

This paper describes a 12.5 Gbps voltage mode transmitter with a high speed signal conditioning capability. Using a linear equalizer that is followed by a power efficient output stage, the transmitter achieves pre-emphasis at very low power consumption. In measurements, the transmitter can reliably transmit a 12.5 Gbps PRBS7 signal through a lossy 14 in. FR4 stripline commonly used in backplanes. It achieves a peak to peak jitter of 24 ps, a differential eye opening amplitude of 120 mV, and a maximum common mode ripple of 40 mV. The proposed topology consumes 33 mW at-speed power which includes both the output stage and the linear equalizer. It also passes 8KV HBM ESD testing without compromising the high speed capability. The transmitter is fabricated in a 130 nm BiCMOS technology with 100 GHz maximum f_t and packaged in a commercial leadless leadframe package.     

A sub 1 V high PSRR CMOS bandgap voltage reference

A Bandgap circuit capable of generating a reference voltage of less than 1 V with high PSRR and low temperature sensitivity is proposed. High PSRR achieved by means of an improved current mode regulator which isolates the bandgap voltage from the variations and the noise of the power supply. A vigorous analytical approach is presented to provide a universal design guideline. The analysis unveils the sensitivity of the circuit characteristic to device parameters. The proposed circuit is fabricated in a CMOS technology and operates down to a supply voltage of 1.2 V. The circuit yields 20 ppm/°C of temperature coefficient in typical case and 50 ppm/°C of temperature coefficient in worst case over temperature range −40 to 140°C, 60 ppm/V of supply voltage dependence and 60 dB PSRR at 1 MHz without trimming or extra circuits for the curvature compensation. The entire circuit occupies 0.027 mm² of die area and consumes from a 1.2 V supply voltage at room temperature. Twenty chips are tested to show the robustness of the topology and the measurement results are compared with Monte Carlo simulation and analysis.     

0.5 V bulk-driven analog building blocks

Basic analog building blocks, such as voltage follower (VF), second generation Current Conveyor (CCII), and Current Feedback Operational Amplifier (CFOA), capable for operating under 0.5 V supply voltage, are introduced in this paper. The input stage of the proposed blocks is based on bulk-driven pMOS devices, and simultaneously offers the advantages of almost rail-to-rail input/output voltage swing and capability for operation under the extremely low supply voltage. Their performances have been evaluated and compared through simulation results using a standard 0.18 μm n-well process. The bandwidth of the voltage and current followers for both CCII and CFOA is 11 MHz and 10 MHz, respectively. The power consumption of CCII and CFOA is 30 μW and 50 μW, respectively.     

A 77 GHz FMCW radar transmitter with reconfigurable power amplifier in 65 nm CMOS

A frequency modulated continuous-wave (FMCW) radar transmitter in 65 nm CMOS is presented. The transmitter consists of one FMCW signal generator, one reconfigurable power amplifier and bias circuits. FMCW chirp signal comes from a sigma-delta modulated fractional-N phase-locked loop (PLL) with an integrated digital triangle-wave generator to control the output division-ratio of the sigma-delta modulator. A four-way power combining power amplifier is employed to improve the output power with a reconfigurable output power to satisfy different detection distance requirements. The measured results show that the chirp bandwidth achieves 2 GHz, from 76 GHz to 78 GHz, and the power amplifier achieves 13.1 dBm output P1dB with 8.1% PAE. The power amplifier and FMCW signal generator consume 228 mW and 56 mW power, respectively, with a 1.0 V power supply. The core die area is only 2.6×0.88 mm².